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Hamed Aminzadeh and Reza Lotfi

DESIGN GUIDELINES FOR HIGH-SPEED TWO-STAGE CMOS OPERATIONAL AMPLIFIERS

Hamed Aminzadeh and Reza Lotfi

Integrated Systems Laboratory, Electrical Engineering Department Ferdowsi University of Mashhad Mashhad, I.R. Iran

:

(cascode) .(CMOS) . . . .

To whom correspondence should be addressed. E-mail: [email protected]

Paper Received: 28 February 2007; Revised: 30 June 2007; Accepted: 18 September 2007

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ABSTRACT This paper presents a well-defined procedure for the design of high-speed twostage CMOS operational amplifiers. Cascode-compensated amplifiers with good trade-offs between speed, power and stability that make them suitable for high-speed applications are discussed. The structures are analyzed to obtain the required circuitlevel parameters according to particular bandwidth and stability. A new technique to take into account the effect of transfer function zeros, which are traditionally neglected, is proposed. The effect of new capacitor sizing rules to split the compensation capacitance and increase the amplifier's speed has also been considered. Based on these novelties, a new methodology for the design of highspeed operational amplifiers is proposed. Key words: analog design, frequency compensation, high-speed design, operational amplifiers, stability, two-stage cascode-compensated amplifiers

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DESIGN GUIDELINES FOR HIGH-SPEED TWO-STAGE CMOS OPERATIONAL AMPLIFIERS

1. INTRODUCTION Operational amplifiers (opamps) with moderate DC gains, high output swings and reasonable open-loop gainbandwidth product (GBW) are usually implemented with two-stage structures. Without frequency compensation, these opamps are not stable in closed-loop applications [1­3]. A number of frequency compensation techniques are proposed to stabilize a closed-loop two-stage amplifier [4­8]. Among them, cascode compensation (Ahuja-style compensation) is becoming more popular in high-speed applications [7­9]. This is due to the fact that it results in lower power consumption (with similar speed), higher speed (with similar power consumption), and higher power supply rejection ratio (PSRR) when compared to its major competitors like Miller compensation. Nevertheless, the analysis of cascodecompensated opamps is somewhat complicated. The main reason for this complexity is the increase in the order of the system after the compensation is applied. This results in a considerable designing effort for the designer to find the optimized transistor dimensions and bias currents before implementing the circuit into a silicon die. The aim of the design methodology in this paper is to propose straightforward yet accurate equations for the design of high-speed cascode-compensated CMOS opamps. To do this, instead of performing a complex closed-loop analysis [10, 11], a new simple open-loop analysis with some meaningful parameters (phase margin, gain-bandwidth, etc.) is performed. The result is straightforward circuit-level expressions for the design of cascode-compensated opamps. The performed analysis in this paper is for conventional cascode compensation. Generally speaking, there are two types of cascode compensation techniques i.e. cascode compensation [6] and improved cascode compensation [7]. Although the improved cascode compensation is introduced later than cascode compensation and it might have some advantages in particular situations nevertheless due to its left-half-plane (LHP) zero which has the potential to produce a pole-zero doublet (as it is typically located near a LHP pole), it is usually avoided in high-speed applications [12]. However, hybrid cascode compensation [8] which combines the two techniques (cascode compensation with improved cascode compensation) seems to be more advantageous. This technique applies two separate compensation capacitors to stabilize the opamp. It is possible to demonstrate both mathematically and empirically that this method has a relatively better performance compared to each technique [8­12]. This is however at the cost of a very complicated behavior due to the higher order of the system. The induced pole­zero doublet generated in this technique is also an issue. This doublet can dramatically degrade the settling performance of the amplifier. Due to this, new capacitor sizing rules for suppressing its effect while preserving other advantages is proposed also. These rules are aimed to develop the proposed methodology for the design of two-stage hybrid cascode-compensated opamps. The rest of this paper is divided into four parts. Section 2 presents the required analysis for the design of cascode-compensated opamps. Cascode compensation and hybrid cascode compensation are the main topics discussed. The results of this section are then used in Section 3 to propose a simple yet accurate design methodology for high-speed operational amplifiers. Design examples and comparisons between simulated and expected results are described in Section 4 to show the efficiency of the proposed approach. 2. THE REQUIRED ANALYSIS 2.1. Cascode Compensation Open-Loop Analysis Figure 1 shows a two-stage fully-differential opamp composed of a folded-cascode amplifier as the first stage and a common-source amplifier as the second stage [11]. In this topology, cascode compensation technique is used to avoid closed-loop instability. Based on this technique, each half-circuit should employ an active capacitor for compensation purposes [9]. For this to happen, a current buffer (MB) should be applied in series with the compensation capacitor (CC), to reduce the direct capacitive loading of the passive compensation capacitors on the output nodes (VO). This pushes the nondominant poles and zeros to higher frequencies. In this structure, after compensation by neglecting the effect of high frequency parasitic poles and zeros, the open-loop transfer function has one dominant and two non-dominant poles [9]. Non-dominant poles might be real or complex depending on their damping factor (). The structure has also two zeros, one at the right-half plane (RHP) and one at the LHP. The RHP zero originates from the feedforward current which flows through CC towards VO [9]. The small-signal equivalent circuit of Figure 1 is shown in Figure 2 where CA, CB, CL and RoA, RoB, and RL are the total capacitances and

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resistances seen at nodes A, B, and VO respectively. The transconductance of each signal-path MOS transistor (namely Mi, MB, and ML) is also defined with an equivalent gm (gmi, gmB, and gmL). After solving the small-signal set of equations, making appropriate simplifications and performing some routine manipulations, the small-signal transfer function of this structure is obtained as follows [9]:

AV ( s) g mi g mL RoB RL (1 - s 2 /( g mB g mL / C B CC )) (1 + g mL RL RoB CC s)(1 + (C B (C L + CC ) / g mLCC )s + (C L C B / g mB g mL )s 2 )

.

(1)

This transfer function can be written in symbolic form as:

AV ( s ) ADC (1 - s 2 / z 2 )

2 (1 + s / 0 )(1 + s ( 2 / n ) + s 2 / n )

.

(2)

where ADC, z1,2 = ±|z| and 0 represent the open-loop DC gain, the magnitude of zeros and the magnitude of the dominant pole respectively. It is relatively hard to observe the effect of zeros in the transfer function shown in (2), and thus all of the previous studies neglect their effect [5-12].

VDD

MS

MU

VCMFB

C

B

CC

M Tail

IB

Vi +

MU

Vi -

VO -

CL

ML

MC

MB

Mi

Mi

C

CC

MS

IL

MC

Ii

B

A

MT

MB

VO+

CL

A

MT

ML

Figure 1. A two-stage cascode-compensated opamp

Figure 2. Small-signal differential mode half-circuit of the opamp

An elegant and efficient way to take the effect of zeros into account is to properly model them in the generic secondorder polynomial of the denominator. To this end, the new values of damping factor and natural frequency (n) called the effective damping factor ( ) and effective natural frequency ( n ) can be defined such that:

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1- s2 / z2 1 + s ( 2 / n ) + s

2 2 / n

=

1 1 + s ( 2 / n ) + s 2 / n2

.

(3)

This relation in this form does not result in straightforward relations between the effective damping factor and the effective natural frequency with small-signal parameters. However, Taylor expansion of zeros can be exploited to rewrite (3) as:

2 2 1 + s (2 / n ) + s / n =

1 + s (2 / n ) + s 1- s

2 2

2

/ n

2

/z

2

=

(4)

(1 + s (2 / n ) + s

2

/ n ) (1 + s

2

/z

2

+ ...).

By ignoring higher than second-order terms which are negligible when the zeros are located at high frequencies, (4) is simplified into:

2 2 1 + s (2 / n ) + s / n 2 2 2 1 + s (2 / n ) + s (1/ n + 1/ z ).

(5)

It has to be noted that approximation (5) may not hold true in the case of low-frequency zeros; in which higher order terms magnitude is significant. From (5), the relationship between the effective damping factor and the effective natural frequency with circuit parameters is estimated as follows:

=

1 2 g mB C B ( C C + C L )

2 g mL C C

,

(6)

n =

g mB g mL . C B (C C + C L )

(7)

Based on these equations, the transfer function can be approximated as:

AV ( s ) ADC (1 + s / 0 )(1 + s ( 2 / n ) + s 2 / n2 )

.

(8)

According to the definition of GBW (the angular open-loop unity­gain frequency where |AV (j)| becomes equal to unity), from (8) the relation between phase margin ( M) and GBW is obtained as:

M = 180 o - tan - 1 (

.G B W 2 ( .G B W / n ) ) - tan - 1 ( ). )2 0 1 - ( .G B W / n

(9)

As 0 is the dominant pole, the second term can be approximated as 90o, therefore:

tan( M ) = ( 1 - ( .G B W / n ) 2 ), 2 ( .G B W / n )

(10)

where is the feedback factor of the closed-loop amplifier. The only assumption made in deriving (9) is to ignore the effect of parasitic non-dominant poles and zeros on the magnitude of the loop-gain transient frequency (where the loopgain becomes equal to unity). This assumption makes it possible to express this parameter as .GBW (similar to a firstorder system). This is done to simplify the analysis and to express this equation in a more useful form. The approximation is fairly valid in typical values of phase margin.

By substituting n by its corresponding value from (7), the relationship between GBW, and M is obtained from:

GBW =

1

g mB g mL 1 C B (C C + C L ) tan( ) + 1 + 2 tan 2 ( ) . M M

(11)

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On the other hand, by substituting by its corresponding value from (6) and performing some manipulations we can obtain:

GBW = 1

g mB 2 C C ( tan( M ) + 1 + 2 tan 2 ( M ) )

.

(12)

This equation shows that a lower effective damping factor leads to a higher GBW. However, this might not be advantageous because for the same value of phase margin, the relative distance between the effective natural frequency ( n ) and the GBW decreases. This finally leads to an induced peak in the frequency region of interest which significantly degrades the opamp stability. Due to this, keeping tan( M) greater than a threshold around unity is essential for proper stability of the closed-loop and a lower should be compensated by a higher phase margin. To further proceed with the analysis, it is straightforward to show that there is also another relationship for the GBW based on the transconductance of input transistors (gmi) [1]:

GBW = ADC 0 =

g mi . CC

(13)

The three equations for the GBW, namely (11), (12), and (13), will be employed in Section 3 when the new design methodology is presented. 2.2. Hybrid Cascode Compensation, the Proposed Capacitor Sizing Rules Cascode compensation and improved-cascode compensation can be combined together to form a two-stage hybrid cascode-compensated opamp. Figure 3 shows an instance. As can be seen, this technique employs two compensation capacitors between the output node and the two low-impedance nodes of the first stage (namely nodes A and C). Hence two current buffers (MB and MC) instead of one in the previous case which act in parallel are formed to feedback the output AC signal into node B. Due to this, for a fixed amount of power consumption the frequency response and the settling behavior of the resultant amplifier are improved. To compare cascode compensation with hybrid cascode compensation, assuming the total compensation capacitor (CC) to be a particular value, if gmB = gmC and CA = CS, the AC feedback current gain in hybrid cascode compensation is twice that of cascode compensation. Due to this, the magnitudes of parasitic poles and zeros are now 2 times greater than their equivalent values in the cascodecompensated structure (Figure 1). This can be observed by performing small-signal analysis as well [12].

VDD

MS

MU

VCMFB

C

CS CA

M Tail

IB

Vi +

MU

Vi -

VO -

CL

ML

MC

Mi

Mi

C

CS

CA

MS

MC

IL

B

MB

Ii

B

MB

VO+

CL

A

MT

A

MT

ML

Figure 3. A two-stage hybrid cascode-compensated opamp

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Although the highlighted point predicts a significant improvement in the response of this amplifier, in practice, the usual ringing of the output response usually influences the result. The ringing is due to the existence of a pole­zero doublet in the output response. To gain more insight into the proposed method for suppressing this doublet, the magnitudes of second pole and first zero of the opamp are now presented [12]:

P2 - g mB g mC (C A + C S ) C A C S ( g mB + g mC ) =- g mB || g mC C A || C S

,

(14)

z1 -

g mC CS

.

(15)

As can be seen, the values of the first zero and the second pole are at the same order of magnitude. Thus they have the potential to produce a doublet in the output response. The reason why this doublet is generated can be qualitatively explained by considering that in Figure 3, there are two distinct AC feedback paths for the output signal to propagate towards the first stage output. These two paths are shown in Figure 4. When the output signal experiences two different delays in these two paths, it amplifies and comes back to the output with different delays. This can be the source of a doublet in the output response. To minimize the effect of this doublet, the difference between the two delays (1 and 2) should be made zero. In ideal case, we should have:

1 =

CA g mB , 2 = CS g mC 1 = 2.

(16)

Figure 4. The two capacitive feedback paths existed in hybrid cascode compensation

It is interesting to note that the magnitude of the first zero and the second pole ((14) and (15)) will be identical provided that condition (16) is satisfied. Hence equating (14) with (15) has the same result as (16). Based on the above discussion, the required compensation capacitors in Figure 3 for a perfect pole­zero cancellation can be found through equating (14) with (15):

C A + C S = CC ,

(17)

,

CA =

CC 1 + g mC / g mB

CC 1 + g mB / g mC

(18)

CS =

.

(19)

where CC is the predetermined value assigned for the compensation capacitor based on the kT/C noise constraints. Equations (18) and (19) are the general restrictions for the value of capacitors in hybrid cascode compensation scheme. The only consideration when applying them is to guarantee a reasonable matching because high accuracy of non-integer integrated capacitor ratio may be difficult to achieve.

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3. THE PROPOSED DESIGN METHOLOGY It is now possible to present a simple well-defined design procedures for high-speed cascode-compensated opamps based on the derived equations. First, it is essential to specify some parameters. The methodology is based on the load and total compensation capacitors (CL, CC), the required gain-bandwidth (GBW), the required slew-rate (SR), the feedback factor (), the phase margin ( M), and finally the needed effective damping factor ( ). Other important parameters such as DC gain, CMRR, and PSRR, will not be used during the design steps since they depend on the output resistance of MOS transistors that is not easily modeled. Such parameters greatly depend on the amplifier topology and can only be predicted by simulation using accurate transistor models [13]. A recommendation for the values of and M can be based on obtaining a third-order Butterworth style for the poles of the opamp in unity-feedback structure. This results in a maximum unity-feedback flat band [14, 15] which is required in many applications. For this to happen, these two parameters should be set equal to = 2 / 2 and M = 60o. Although it is the best choice to have an ideal unity-feedback frequency response, to optimize the output settling behavior, the point is located somewhere else [14­16]. As a result, if the aim of the design is for a settling-based application (like for switched-capacitor circuits), the optimized point should be found through simulations. The design procedure starts with determining the required transconductance for the input transistors to satisfy the required GBW. Using (13), we can find:

gmi = GBW.Cc.

(20)

Other transistor transconductances in the signal path should be adjusted to satisfy the required , M, and . Beginning from (11) and (12) and performing some routine manipulations, it follows that the required gmB and gmL will be:

g mB = 2. . .( tan( M ) + 1 + 2 tan 2 ( M ) ) g mi ,

g mL = 1 C B (C L + CC ) ( )( tan(M ) + 1 + 2 tan 2 (M ) ) g mi . 2 2 C

C

(21) (22)

Equation (22) shows that an initial value for the parasitic capacitance of the first stage (CB) is required to start the calculations. In fact, it can then be updated through simulation results. After determining gmi, gmB , and gmL, the required current for the input transistors (Ii in Figure 1) can be determined to satisfy the needed fully-differential slew-rate (SR). According to the definition of slew-rate, it follows that:

Ii = 1 2 SR .C C .

(23)

As the required transconductance for the input transistors (Mi) is also determined formerly, it is possible that (23) does not yield adequate overdrive voltage for these transistors [11]. In such cases, the transistor might work in subthreshold region which is not appropriate. To avoid this to happen, the current should be increased adequately to allow the transistor to have enough overdrive voltage. After setting Ii, the current of the folded branch (IB in Figure 1) can be determined by choosing an appropriate overdrive voltage for MB (Vov,B). As is clear, the following equation between the current and transconductance of MOS transistors is valid in strong-inversion [1­3]:

IB = 1 2 g mB . ov , B . V

(24)

The second-stage current (IL in Figure 1) can then be derived by equating the second-stage slew-rate (SR2) [17] with the first-stage and total required slew-rates (SR1, SR):

SR 2 = 2I L , C L + CC

(25)

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SR = SR 1 = SR 2 I L = (1 +

CL )I i . CC

(26)

After determining IL, (18) and (19) can be used to split the total compensation capacitor (CC) into two distinct capacitors in order to convert the compensation to hybrid cascode compensation (Figure 3) and further improve the frequency response and settling behavior. As highlighted previously, the required capacitor values in Figure 3 should be:

CA = CC 1 + g mC / g mB , CS = CC 1 + g mB / g mC .

(27)

4. SIMULATION RESULTS To verify the effectiveness of the derived equations, several simulations were performed in 0.25µm BSIM3v3 level 49 mixed-signal CMOS technology using HSPICE models. A high-speed cascode-compensated opamp with Figure 1 structure is simulated in this technology. According to the application, the load capacitance was estimated as 6.5pF. For this value, the compensation capacitance was determined by kT/C thermal noise constraints and area limitations to be 2pF [18]. In addition, the required open-loop GBW was determined to be 300 MHz (according to the required closedloop unity-feedback bandwidth). The damping factor (the effective damping factor after taking into account the effect of zeros) and the phase margin were adopted equal to 0.7 and 60o respectively. As highlighted earlier, these are the best choices to obtain a maximally closed-loop unity-feedback flat-band amplifier. Using (20), the input transistors transconductance was obtained as gmi = 3.77mA/V. From (21), the transconductance of MB was calculated to be gmB = 14.67mA/V. At last, by assuming an initial value for CB equal to 1pF, the transconductance of the second-stage input transistors was obtained equal to gmL = 15.91mA/V. Of course, according to the actual value of CB, this value was revised through simulations. A good agreement between simulation results and calculated results especially for the values of effective damping factor, phase margin, and GBW is observed. The transistors aspect ratios which were empirically determined to satisfy the highlighted constraints are shown in Table 1. The frequency response of the amplifier is shown in Figure 5. The designed opamp is then employed in the unity-gain flip-round sample-and-hold amplifier (SHA) shown in Figure 6 [1]. In this structure, sampling capacitors (CS) are charged by the input in the sampling phase (p1). The output voltage is then forced to settle to the input sampled value by the stored charge when the capacitors are connected to the output in the holding phase (p2). In p2, the opamp load capacitance, including the output stage transistors parasitics, the next stage input capacitance, and the serial result of SHA sampling capacitance with opamp input parasitic capacitance (Cin) was equal to 6.5pF. It is worth mentioning that the actual feedback factor of the SHA in the holding phase is equal to:

=

CS . C S + C in

(28)

Figure 7 depicts the settling behavior of the simulated Butterworth pole-style flip-round unity-feedback SHA. A comparison between simulation results and calculated results are also presented in Table 2. The settling time (tS) is computed for 0.2% total error [19, 20]. Finally, the efficiency of converting the compensation technique to hybrid cascode compensation is considered in simulations. As proposed in [12], we first split the compensation capacitor into two equal capacitors and connect them to nodes A and C (Figure 3). The pole-zero analysis of the resultant structure shows that the first zero and the first nondominant pole are located at two different frequencies namely 362MHz and 441MHz respectively. Next, (27) is used to split the compensation capacitor. At this time, the first non-dominant pole and the first zero are approximately located coincidently (436 MHz and 420MHz respectively). This results in an improvement in the frequency response and settling performance of the amplifier as the effect of doublet is suppressed. At this time the 0.2% settling time of the amplifier is reduced to 2.86ns.

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Table 1: Transistors Aspect Ratios for the OPAMP Transistor W/L (µm /µm) 120/0.25 400/0.25 200/0.25 280/0.5 100/0.25 80/0.4 200/0.5 120/0.25

Mi MB MC MU MTail MT MS ML

70 60 50 40 30 20 10 0 10100

200 150 100 50 0

-50

|A.ß| = 0 dB PM = 64o

101 102 103

-100 -150 -200

Frequency (Hz)

104

105

106

107

108

Figure 5. Frequency response of the simulated opamp

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Phase (deg.)

Gain (dB)

Hamed Aminzadeh and Reza Lotfi

p2

p1 +

CS

Cin +

Vin

p1

VCM,i

CS

p1 p1 Cin

+

p1

+

VO

-

p2

Figure 6. The simulated unity-gain flip-around sample-and-hold structure

Figure 7. Step response of the simulated sample-and-hold circuit

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Table 2. Comparison Between Simulated and Calculated Results Parameter Simulation Results 276

0

Calculated Results 300 60 0.707 60 ---

GBW (MHz)

Phase Margin ( )

64 0.612 62 3.18

DC Gain (dB)

tS (0.2%) (ns)

5. CONCLUSIONS Simulation results confirm that the proposed design procedure can be utilized to design opamps that meet all the required specifications. The proposed procedures are useful for pencil-and-paper design and can easily be utilized in analog knowledge-based CAD tools. The proposed methodology is relatively accurate because a new technique to take into account the effect of transfer function zeros which are traditionally neglected is employed. In addition, the designed amplifiers have no ringing in their transient response because a new method to suppress the doublet effect is proposed. Finally, an important approach about the settling time of cascode-compensated opamps is that although simulations confirm that the settling time can be further improved by increasing the value of GBW (while keeping other parameters unchanged) the relationship between settling time, effective damping factor, and phase margin is somewhat complicated. Nevertheless, it seems that the optimized settling time is achieved for a value of between 0.6 and 1 and a value of phase margin between 60 and 80 degrees. REFERENCES

[1] [2] [3] [4] [5] [6] [7] [8] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001. P. Gray and R. Meyer, "MOS Operational Amplifier Design: a Tutorial Overview", IEEE J. Solid-State Circuits, SC17(1982), pp. 969­982. D. O. Pederson and K. Mayaram, Analog Integrated Circuits for Communication (Principles, Simulation and Design). Norwell, MA: Kluwer Academic, 1991. R. G. H. Eschauzier and J. H. Huijsing, Frequency Compensation Techniques for Low-Power Operational Amplifiers. Boston, MA: Kluwer, 1995. G. Palmisano and G. Palumbo, "A Compensation Strategy for Two-Stage CMOS OPAMS Based on Current Buffer," IEEE Trans. Circuits Syst. I, Fund. Theory App., 44(3)(1997), pp. 252­262. B. K. Ahuja, "An Improved Frequency Compensation Technique for CMOS Operational Amplifiers," IEEE J. SolidState Circuits, December 1983, pp. 629­633. L. Yao, M. Steyaert, and W. Sansen, "Fast-Settling CMOS Two-Stage Operational Transconductance Amplifiers and their Systematic Design," in Proc. IEEE Int. Symp. Circuits & Systems (ISCAS 2002), vol. 2, May 2002, pp. 839­842. M. Yavari and O. Shoaei, "Low-Voltage Low-Power Fast-Settling CMOS Operational Transconductance Amplifiers for Switched-Capacitor Applications", in Proc. IEEE Int. Symp. on Low Power Electronics and Design (ISLPED 2003), Aug. 2003, pp. 345­348. P. J. Hurst, S. H. Lewis, J. P. Keane, F. Aram, and K. C. Dyer, "Miller Compensation Using Current Buffers in Fully Differential CMOS Two-Stage Operational Amplifiers," IEEE Trans. Circuits and Systems I: Fund. Theory, 51(2), (2004), pp. 275­285. Feldman, "High-Speed, Low-Power Sigma-Delta Modulators for RF Base-Band Channel Applications", Ph.D. Dissertation, University of California, Berkeley, 1997.

[9]

[10]

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[11] [12] [13] [14] [15] [16] [17] [18] [19]

R. Lotfi, M. Taherzadeh, M. Yaser Azizi, and O. Shoaei, "Low Power Design for Low-Voltage Fast-Settling Operational Amplifier in Switched Capacitor Applications," INTEGRATION, the VLSI Journal, 36(2003), pp. 175­189. M. Yavari, O. Shoaei, and F. Svelto, "Hybrid Cascode Compensation for Two-Stage CMOS Operational Amplifiers," in Proc. IEEE Int. Symp. Circuits & Systems (ISCAS 2005), March, 2005, pp. 1565­1568. G. Palmisano, G. Palumbo, and S. Pennisi, "Design Procedure for Two-Stage CMOS Transconductance Amplifier: A Tutorial," in Analog Integrated Circuit and Signal Processing, vol. 27. Norwell, MA: Kluwer, 2001, pp. 179­189. G. Palumbo and S. Pennisi, "Design Methodology and Advances in Nested-Miller Compensation," IEEE Trans. Circuits Syst. I, Fund. Theory App., 49(2002) pp. 893­903. K. Leung and P. Mok, "Nested Miller Compensation in Low-Power CMOS Design," IEEE Trans. Circuits Syst. II, 48 (2001), pp. 388­394. H. Yang and D. Allstot, "Considerations for Fast Settling Operational Amplifiers," IEEE Trans. Circuits Syst., 37 (1990) pp. 326­334. S. Rabii and B.A. Wooley, "A 1.8-V Digital-Audio Sigma-Delta Modulator in 0.8-µm CMOS," IEEE J. Solid-State Circuits, 32(1997)(6), pp. 783­796. J. Mahattanakul and J. Chutichatuporn, "Design Procedure for Two-Stage CMOS OPAMP with Flexible Noise-Power Balancing Scheme," IEEE Trans. Circuits Syst. I, Fund. Theory App., 52(8)(2005), pp.1508­1514. J. Ramirez-Angulo, A. Torralba, R. G. Carvajal, and J. Tombs, "Low-Voltage CMOS Operational Amplifiers with Wide Input-Output Swing Based on a Novel Scheme," IEEE Trans. Circuits Syst. I, Fund. Theory App., 47(5)(2000), pp. 772­774. G. Giustolisi, G. Palmisano, G. Palumbo, and T. Segreto, "1.2-V CMOS Op-Amp with a Dynamically Biased Output Stage," IEEE J. Solid-State Circuits, 35(4)(2000) pp. 632­636.

[20]

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