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SOC REALIZATION

White Paper

The linchpin to enabling electronics innovation

This White Paper deals with the way SoCs are designed, a process of substantial complexity. This design process is undergoing significant transformation, and those changes are a central part of this piece.

Table of Contents

FOREWORD .............................................................................................................................................3 CHAPTER 1: THE SYSTEM ON CHIP ERA ..........................................................................................5 CHAPTER 2: THE SHIFT IN THE VALUE CHAIN ........................................................................... 10 CHAPTER 3: SOC REALIZATION ....................................................................................................... 15 CONCLUSION ....................................................................................................................................... 19

Every decade EDA steps up to solve the relentless challenges of complexity. This time complexity management is just the table stakes as cross-functional considerations trump monolithic solutions to interdependent problems. At its core, this white paper essentially describes a very real cross dependence between hardware, software, IP and process technology. And so far, the issues are only contemplated by companies like Atrenta. While there is much to do to overcome the development challenges at and beyond 28nm, it is also true that only a thoughtful and multi-disciplinary view will even begin to yield the timely success of next generation SoCs. Atrenta has taken the high ground for this decade. Is it concept or Atrenta SoC Realization? My money is on the latter.

Jack Harding, Chairman, President & CEO, eSilicon Corporation Sunnyvale, CA 2011

At its essence SoC Realization is about being able to analyze and verify design concepts much earlier in the design process, and at much higher levels of abstraction, in order to avoid costly errors downstream. It focuses on the use and reuse of IP as a core strategy in SoC design and addresses the critical issues related to choosing, assembling, verifying and integrating IP blocks, regardless of source. While not just a tool chain, SoC Realization requires new tools and also combines data management, design, manufacturing process and application expertise. It becomes the cockpit to guide a design from concept to implementation, allowing the developer to "tune the knobs" on critical operating characteristics like performance, power, and area, and also ensuring that the platform is synchronized for both the hardware and software aspects of the system's functionality.

Jim Hogan, Independent Investor Santa Cruz, CA 2011 SoC Realization | The linchpin to enabling electronics innovation Foreword 1

With the reduction in feature dimensions to 32/28nm and 22/20nm, IC designs are increasingly evolving into system designs. In addition to a range of hardware IP, software IP also needs to be embedded. Atrenta's design capabilities are effective in not only supporting the assembly and optimization of complex IC designs but also bridging SoC and system design flows.

Dr. Handel Jones, CEO, IBS, Inc. Los Gatos, CA 2011

The core of SoC Realization is the Silicon Virtual Prototype (SVP). We've been writing about it for over ten years. Partly because it is the most technically challenging tool EDA has worked on. And partly because of the Big Four's justifiable fear that the SVP will negatively impact their RTL revenue. That has been fortunate for Atrenta as they have had the time to develop their version of the SVP, which looks like the answer to the design engineer's SoC Realization problems.

Gary Smith, Founder & Chief Analyst, GarySmithEDA Santa Clara, CA 2011

SoC Realization | The linchpin to enabling electronics innovation Foreword

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F OREWORD

There are significant changes occurring in the electronics industry. The widespread consumerization of electronic devices has permanently changed our lives for the better. The rate at which hand-held, personal electronic products are evolving is staggering by any historical measure. These rapid advances are facilitated by system on chip (SoC) devices, the microelectronic marvels of engineering that compress entire systems onto a sliver of silicon that is smaller than a penny. This White Paper deals with the way SoCs are designed, a process of substantial complexity. This design process is undergoing significant transformation, and those changes are a central part of this piece. We will discuss the shifting value in the semiconductor ecosystem. The implications of those shifts will create new markets and new types of companies to serve those markets. A critical enabler for these changes is the ability to make the marvels of SoC devices available to a large customer base. This means changes in the semiconductor supply chain and changes in the way SoCs are designed. At a high level, one can decompose the design process for SoCs into three distinct, but interrelated parts: System Realization ­ Is the process of defining the architecture of the end product, both hardware and software, typically supported by multiple SoC devices. This is a fairly well defined and growing market. Companies such as MathWorks provide high-level modeling tools to support this market. Hardware emulation and prototyping products from a variety of suppliers are also used here. Silicon Realization ­ Is the process of designing and building the actual semiconductor devices that will implement the system. This market is served by the electronic design automation (EDA) community. Companies such as Synopsys, Cadence Design Systems and Mentor Graphics are the primary suppliers in this market. SoC Realization ­ Forms an all-important bridge between System Realization and Silicon Realization. It is here that the architecture of the semiconductor devices is defined, the semiconductor IP, or building blocks for the chip, are chosen and the design is matured to a stage where it is ready to be handed off to Silicon Realization. Atrenta is convinced that the SoC Realization market will play a major role to facilitate the anticipated growth in the electronics industry in the years ahead. This market forms a "bridge" between the heretofore isolated markets of System Realization and Silicon Realization. Without this bridge, true top-down design is not possible. Without the efficiencies of such an integrated design flow, the cost of SoC design will increase exponentially, resulting in a dramatic slow-down in the growth of the electronics sector.

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I am proud of the pioneering work being done at Atrenta to serve the needs of the SoC Realization market. Our SpyGlass product family has become the de facto standard to ensure a design is implementation ready. Its use as a reference standard for semiconductor IP quality is also well documented and growing. Our new GenSys product family is establishing a complete methodology for automated chip assembly ­ a critical ingredient for SoC Realization. I believe our company is poised to be one the first broad-line suppliers to the emerging SoC Realization market ­ we look to the future with great optimism. I invite you to read on and learn more about the emerging SoC Realization market. This paper is organized into three chapters. In Chapter 1 we outline the changing market dynamics that are fueling the rapid growth we are seeing in the electronics sector. In Chapter 2 we discuss some of the shifts occurring in value aggregation, the cost challenges of SoC design and some of the key ingredients to address those cost challenges. Chapter 3 provides a detailed overview of SoC Realization for those who want to dig deeper. (I expect some readers may choose to skip this chapter unless they are motivated to dive into the details.) I hope you enjoy this White Paper and the journey it describes. Dr. Ajoy K. Bose, Chairman, President and CEO, Atrenta Inc. San Jose, CA 2011

® ®

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C HAPTER 1: T HE S YSTEM ON C HIP E RA

The concept of a system on chip (SoC) device has evolved over the past decade, influenced by significant advances in semiconductor design and manufacturing technologies. Most notably, the consistent scaling of Moore's Law continues to extend the capabilities and the levels of function integration (i.e., for integrated circuits or ICs). The business and economic dynamics of the electronics industry are equally, if not more significant an influence on how complex chips are designed and manufactured. More digitally-enabled products are proliferating through all levels of increasingly interconnected economies and geographies. Consumer markets are becoming the main driver for this proliferation and the consumer market is fast-paced, with a thirst for new products on a regular basis. The electronics industry that services this proliferation must become more nimble and efficient to keep up. At its essence an SoC represents the natural progression of the industry to design and build things that perform more functions in smaller, more efficient ways. The functionality that a decade ago may have been contained on a printed circuit board (PCB) and executed by multiple discrete chips (e.g., memory, processors, interface, graphics, etc.), can now be integrated on a single IC, commonly called an SoC. This integration is achieved largely through the emergence of compact and robust techniques to represent the important functions or applications contained in an SoC. These techniques leverage high-level design languages and synthesis technology to deliver complete, yet flexible descriptions of SoC components in synthesizable or "soft" form. This new level of design abstraction to represent critical building blocks, known as semiconductor intellectual property (IP), provides access to micro components designed to optimally perform specific functions. These IP blocks are then integrated or assembled to form a working SoC. A substantial portion of an SoC may contain parts of previous generation chips that are reused to save time and ensure reliability. Often, critical functions not within the core competence of the system developer can be obtained elsewhere in the SoC ecosystem. Indeed, the SoC era has spawned a cottage industry within the semiconductor business of companies whose sole business is to provide pre-built IP blocks to the developers of the complete SoC. Suppliers such as ARM (microprocessors), MIPS (video processing), Rambus (memory), Imagination Technologies (graphics) and CEVA (digital signal processing) have been successful in mastering the implementation of specific functions and licensing that knowledge through their IP that is delivered in "soft" or synthesizable form. Modern SoCs are true systems that save product developer's time, money and product real estate thanks to their efficiency. As the concept of SoC becomes more widely adopted throughout the electronics industry, both the opportunities this approach offers, as well as the challenges it presents, are becoming clearer.

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On the opportunities side, SoCs have vast potential to expand the scale of innovation and functionality offered by system developers of all types. SoCs not only enable a virtually infinite number of new capabilities to be contained in smaller and nontraditional products, they also lower the barrier to entry for new players into new markets that are increasingly consumer oriented. In many ways this effect is similar to the impact the application specific integration circuit (ASIC) business model had in the late 1980s. During that time, ASICs essentially made semicustom integrated circuits accessible to many by lowering the cost of design through automated techniques. One of the more significant differences between the ASIC and SoC era is that the ASIC supplier provided all the IP, whereas the SoC supplier must assemble all the IP from both internal and commercial sources. The ASIC approach ensures that the assembled ASIC would be manufacturable in the ASIC supplier's foundry, whereas most SoCs are manufactured in pure play commercial foundries. SoCs are having a similar effect as ASICs, except the scale is larger. The promise of an efficient "mix-and-match" approach to product development, enabled at a new level of design abstraction, holds the potential to dramatically reduce the time, costs and resources required to introduce new products at consumer-market pace. But the economic and technical challenges of SoCs are daunting and increasing. The complexity of modern devices requires new approaches to design and a re-thinking of supply chain models. Manufacturing costs for leading-edge semiconductor processes add to the challenge. And the pitfalls of design reuse - sourcing and integrating building blocks from a variety of places - introduce more risks still. More than ever, the most cost-, time- and risk-efficient methodologies are needed. A critical gap exists in today's SoC development process that threatens to undermine the potential of SoC breakthrough technology. On one end, the detailed process for implementing complex designs in advanced silicon is well understood and is served adequately by traditional electronic design automation (EDA) tools and their tight connection to device physics and manufacturing. On the other end, the process of conceptualizing and analyzing designs at a system level, a high level of abstraction and without the restrictions of physical operating constraints, is also a well-proven, albeit somewhat less rigidly defined area. Ideally, this system level implementation would be available to software application developers before the SoC is actually manufactured to test and debug the software and uncover any SoC architectural problems. Operating at these two different levels of abstraction, most often performed by two (at least) different sets of operations, introduces a variety of risks and design management challenges. The most fundamental challenge is ensuring that what is intended at the highest level of abstraction actually gets implemented in silicon by the steps performed at lower levels of detail. Thus ensuring architectural intent or design coherence, making sure nothing gets "lost in translation" is a major issue within the current SoC design flow.

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This void has emerged as an under-served and emerging link called SoC Realization(1), where important system level information must be transformed to the next level of abstraction and analyzed. Functions must then be assembled (both hardware and software) and implemented in an optimized way in silicon. It is here where an SoC has more degrees of optimization and critical decisions are made on issues such as which building blocks are used, what operating characteristics the SoC will have, and whether it will work as intended once committed to a silicon device. It is the cockpit for guiding the design from concept to implementation and ensuring design coherence from one level to the next. SoC Realization represents the next natural and necessary step up in abstraction from existing EDA methodologies, and a necessary bridge from the more abstract world of system-level design that is helping drive SoC-enabled products.

(1) "EDA360, THE WAY FORWARD

FOR

ELECTRONIC DESIGN", CADENCE DESIGN SYSTEMS, APRIL 2010

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SOC

DRIVES ELECTRONICS INNOVATION

Today's electronics industry is driven by pressures that have broken traditional business and technology models. Largely a result of the massive proliferation of electronic capabilities into consumer products, the cost, time and risk factors exist on a scale never seen before. Companies competing in the high stakes game of consumer electronics are constantly searching for approaches that can meet the demanding market requirements, while still allowing them to differentiate and be profitable. The growing paradox in electronics is that as products must conform to more demanding consumer market dynamics ­ faster development times, lower costs, more efficient derivative designs ­ the technical and economic realities of sophisticated electronic design and manufacturing are driving costs and cycle times in the opposite direction. The SoC concept has long been viewed as a catch-all holy grail that could help align these diverging factors. At its essence, SoC promises a way to reduce design effort and costs by:

· · ·

Combining multiple functions (e.g., microprocessor, memory, application processor) that previously existed in discrete semiconductors onto a single chip or subsystem Enabling the efficient reuse of portions of previous designs, and/or the use of 3rd-party supplied design elements to be combined quickly to create new chip designs Providing a platform for a true "system" on a chip, that is a combination of both the hardware and software required to provide product developers the functionality they require in their next generation devices Indeed, the industry has embraced SoC as a mechanism to address functionality, cost and time to market requirements. Companies have been implementing multi-function devices with continual integration of sub-systems for many years. Market researcher Semico pegs the current SoC market at roughly $45B (2010) and expects revenues to top $54B in 2011. Similarly, the market for semiconductor intellectual property (IP), the fundamental building blocks for SoCs also continues to expand, both in volume and in SoC Realization | The linchpin to enabling electronics innovation Chapter 1: The System on Chip Era 8

influence, with sales of third-party supplied IP reaching almost $3B in 2011 and growing at a 15% annual rate. More telling is the increased prevalence of SoCs and their associated ecosystem in the parlance of the electronics industry, even at its highest level. One need only look to the most recent Consumer Electronics Show to see a range of announcements from end product suppliers touting their SoC-enabled devices. Noteworthy among them: Microsoft trumpeted that its next generation Windows OS would support SoC architectures from Intel, AMD, nVidia and ARM. The added noteworthiness of that particular announcement is the inclusion of ARM, itself a by-product of the SoC era and now a legitimate SoC platform in its own right. In fact, more than half of the top semiconductor companies in the world license IP from ARM. SoC devices are defining a new ecosystem of SoC platform suppliers and system companies making use of them to run their application software. Other interesting and non-traditional semiconductor players are entering the SoC landscape as well. Google, with its Android platform is an ideal example of the importance and control that software has in the new SoC ecosystem. Android is the driving force behind a wide variety of SoC implementations, a dramatic shift from the days when mastery of transistors, interconnect and other "hard wired" aspects of chips were the vital control points. These days software is king and programmability is the key, a departure from the hardware-focused era of gates-and-switches chip design. Application software defines the differentiated value of the system for the consumer. Oracle recently acquired Sun Microsystems, a computer and software supplier, and has gone on the record indicating a thirst to acquire chip companies. Apple has gone so far as to develop its own SoCs internally as a means to optimally implement its strategically advantageous software platform. This has contributed to Apple's ability to deliver 10 hours of battery life for the iPad, for example. Apple's biggest problem is now keeping up with demand and finding foundry capacity. Apple curiously manufactures its SoCs at their lead competitor, Samsung. This raises many questions about IP. There is little question that a new chapter in the SoC era has arrived and it holds the key to continued innovation in electronics, particularly in high-pressure, high volume consumer markets. The question is: what does this require of the electronics industry infrastructure to ensure that the potential of SoC is realized?

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C HAPTER 2: T HE S HIFT IN THE V ALUE C HAIN

THE

SH I F T T O WA R D S O F T WA R E

The shift toward SoC is about more than just incorporating more functionality on a single chip. As evidenced by the examples of Google, Apple, Microsoft, Sun/Oracle and others, it reflects a fundamental shift in the electronics value chain and a new transition point between a design concept and how it gets implemented. In conjunction, the handoff between the product vision and how it gets built continues to move up in abstraction. At the top of the abstraction level is the system concept, which is driven by the OEM. While in the past this system company may have owned the entire implementation chain down to the silicon, the SoC era has resulted in the handoff point shifting ­ as well as what's being handed off. From a chip standpoint, these days a "system" company (think: Google, Microsoft, Sun/Oracle in terms of how this definition has changed) mainly focuses on software as a differentiator, partly because that's where its expertise is and partly because what's required at the silicon implementation level is too difficult, too distracting and too expensive to be attempted by anyone other than dedicated specialists. The result is a greater burden on the semiconductor link in the chain, although not necessarily resulting in more value derived. Semiconductor suppliers, whether independent fabless companies or even captive operations within integrated OEMs, are being asked to provide much more of an entire end user platform, including basic or "bare metal" software instead of a discrete processor-centric chip. That architecture must consist of optimized hardware and software and be able to accommodate rapid changes in functionality via application software and even IP strategies.

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"The customers want their IC vendors to provide an increasing part of the application architecture and functionality, which includes both the software as well as the hardware." --Handel Jones, IBS We have seen these shifts in the past, and they typically revolve around a move upwards in abstraction in how a design is represented and verified. In the chip design world, the transition from gate-level, to register transfer language (RTL)-level, to synthesis-based design styles were all moves toward using less detailed description formats as a means of dealing with increased complexity and increased customer demand. Now, we are on the cusp of another one of these changes in the supply chain and the EDA products that support it. The sheer volume of availability of silicon-proven semiconductor intellectual property (SIP), as well as evolving methodologies to integrate it, has brought design reuse to the forefront of design strategies. Systems have become very complex, but there is an enormous amount of semiconductor IP available from captured and commercial sources. A major challenge is how to qualify, verify and validate IP and integrate it efficiently. Historically, chips were largely structured with a microprocessor-centric view of the world whereby IP blocks were considered to be peripherals ­ application processors, I/O, memory - attached to microprocessors through complex interconnect structures. Today the "system" is thought of entirely at the software level. There is very little differentiation, or value, in the SoC itself beyond the scaling due to new processes to enable advancements in area, performance or power. These advances, as impressive as they have been, are largely considered to be a constant by system companies, who rely on the expertise of foundries and silicon implementation specialists to ensure Moore's Law stays on track with scaling integration. Most importantly, this trend is also an acknowledgement that software comes first. Most of the software for a chip already exists on the prior implementation of the system and the first priority for the new SoC is not to break the software. A company like Cisco is a great example. Their routers must be compatible with the millions of lines of code written in prior products but integrate new features, protocols, security, etc. as well. An SoC Realization | The linchpin to enabling electronics innovation Chapter 2: The Shift in the Value Chain 11

executive at Renesas Mobile Europe had stated, "Productivity loss is due to not having enough software developers to write/change the code for new hardware. One of the most important design objectives should be to redesign the hardware so that software compatibility is maintained". Today, the purpose of an SoC is just to run the software load optimally. Semiconductor process nodes offer new opportunities to optimize how the software load is matched to implementation so that the system runs fast enough, at lower power and at lower cost. This is known as PPA, or performance, power and area tradeoffs to be considered during a design optimization.

THE SOC

DE V E L O PM E N T PR O C E SS : M O V I N G U P I N A BST R A C T I O N

SoCs hold the key to continued scaling of innovation in electronics and are a linchpin to growth in all sectors. But significant challenges exist on both the technical and business levels of SoC development. The inability to meet some of these fundamental challenges threatens to limit the vast potential for growth of the entire industry. First and foremost, SoCs, which require the most advanced manufacturing process and design methodologies, are expensive to develop. Market researchers estimate that the total cost of a design at 22nm is more than double that of a 45nm-based design. A significant portion of that cost is related to time-consuming iterations to ensure the design functions properly and at the right specifications (timing, area and power being the most critical constraints). At 32nm it is estimated that a typical design is likely to meet just 50% of its objectives; at 28nm that number drops to 30%. This is a very high risk game! As mentioned, historically the electronics industry has addressed the need to manage greater complexity by moving design representation up in abstraction. This continues to be true, but perhaps not through new languages or formats, as has previously been the practice. The great hope of next-generation SoC development is that design reuse at an abstraction level beyond logic gates or RTL ­ whether through pre-existing internally developed blocks, or the use of the vast 3rd party market of IP available ­ will save time and reduce risk in putting together multi-function chips. The areas for consideration will be modeling, analysis, simulation and optimization. In concept that is true, but as with most things the devil is in the details and IP reuse has no shortage of pitfalls that can trip engineering teams up. To understand where the greatest opportunities for improvement exist, it's important to view the big picture of SoC development. Today's SoC development process progresses essentially through three main steps:

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·

System Realization: The development of a complete hardware/software platform that will provide all necessary support for end-user applications. The platform includes one or more SoCs and adds an embedded software infrastructure that typically includes an OS, middleware, and reference applications. This step is increasingly driven by the software applications that will run on the completed system. SoC Realization: The new and critical "bridge" step to take a system concept to a real design that can be implemented at a detailed level. It involves the all important steps of choosing the right architecture and IP, validation of the IP, assembling it all on a workable platform, and performing a variety of analysis and verification tasks to ensure that it can be implemented as a viable, working SoC device. Silicon Realization: This represents the set of steps necessary to take a verified SoC design consisting of hardware and software functions, and implement it in working silicon. This is the domain of traditional EDA providers, who work closely with semiconductor manufacturers such as Taiwan Semiconductor Manufacturing Corporation (TSMC). We often call this "EDA Classic". Of the three steps, SoC Realization holds the most potential to dramatically improve SoC development time and bring new levels of value to the electronic design process. It is also the most adjacent area to EDA Classic to consider and is serviced by a fractured collection of in-house and commercial offerings. At its essence SoC Realization is about being able to analyze and verify design concepts much earlier in the design process, and at much higher levels of abstraction, in order to avoid costly errors downstream. It focuses on the use and reuse of IP as a core strategy in SoC design, and addresses the critical issues related to choosing, assembling, verifying and integrating IP blocks, regardless of source. While not just a tool chain, SoC Realization requires new tools and also combines data management, design, manufacturing process and software application expertise. It becomes the cockpit to guide a design from concept to implementation, allowing developers to "tune the knobs" on critical operating characteristics like performance, SoC Realization | The linchpin to enabling electronics innovation Chapter 2: The Shift in the Value Chain 13

·

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power and area, and also ensuring that the platform is synchronized for both the hardware and software aspects of the system's functionality. There are three critical areas driving today's IP-based SoC Realization solution: · · IP Sourcing: Is the IP chosen of sufficient quality? Is it silicon proven? Will it meet my power, performance and area requirements and is it implementation ready? Soc Creation: Is the architecture chosen for the SoC the "right" one? Will it allow the entire system to be synchronized, hardware and software? Will it be scalable across at least two generations of systems products? SoC Handoff: Once the IP and platform has been chosen, is the resulting SoC ready for implementation based on the desired specifications? Can the impact of decisions associated with cost, time and market be measured? There is also an important modeling issue that spans all three areas. · Design Coherence: As one moves up and down the design hierarchy and associated levels of abstraction, is there confidence that the accuracy and completeness of the system model is maintained? Is system intent maintained in the translation to more silicon specific implementations? An SoC Realization environment addresses each of these issues with a set of tools, methods and integrated approaches that streamline the process from a higher level concept to a "ready to implement" design. The result of a design concept being transformed through an SoC Realization environment is that the design intent is targeted optimally for silicon implementation and that the developer can be assured that it will work as intended once passed to the next phases of the process ­ design implementation and manufacturing.

·

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C HAPTER 3: S O C R EALIZATION

THE

ANATOMY OF EFFECTIVE

SOC REALIZATION

There are many tasks and functions that must be addressed in the SoC Realization process, and they can broadly be categorized under three general steps. In addition to these interrelated steps, there needs to be an overall design management infrastructure that these steps are built on as a way to manage the variety of iterations and handoffs essential in realizing the SoC at this level. This infrastructure becomes even more critical as the design goes through derivative iterations, as well as during the process of debugging the design. It should be noted that not everything in an electronic system falls neatly into the software-focused implementation approach that is SoC Realization. For example, analog and mixed-signal functions represent the SoC's connection to the outside world. The design of these subsystems requires specialized tools and methods that are unique. Once designed and debugged, these subsystems will also be abstracted to a higher level so they can be integrated into the SoC. These are the basic steps of SoC Realization:

IP S OURCING

IP sourcing (for both hardware and software functions) encompasses all tasks related to preparing IP for integration. Since reuse is becoming a dominant practice, a significant focus is on preparing pre-existing IP, whether internally developed or from partners/3rd parties. It is also very important to support generation of IP instances from configurable IP (bus fabrics are a good example) and IP generators (e.g., memory generators). Additionally, some IP will be created to drive differentiation, typically through highlevel/behavioral synthesis. However the IP is initially created, IP sourcing must provide the following for both soft (synthesizable) and hard (polygon level) IP:

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·

Authoring: For new IP, this typically means high-level synthesis. For configurable IP, it means generators. Memory generators are typically developed in-house or by commercial suppliers. Configurable soft-IP generators are often developed in-house also but through ad-hoc scripting which makes the generators difficult to share in a standards-driven environment. This area also includes methods to capture register structure and driver information for an IP. PPA (performance, power, area or cost) feasibility: However developed, it is important in IP selection to know if a particular implementation is likely to contribute positively or negatively to overall PPA goals. This assessment is necessarily approximate prior to integration, but it is important to have this data to screen out potentially expensive mistakes. It is also important to explore PPA within the context of the SoC. Does a particular IP block deliver the advertised PPA once placed in the SoC? Optimization: Most in-house IP is still not developed with extensive reuse in mind, and particularly not with emerging standards in mind. In many cases there are opportunities to improve test readiness and optimize power. Also, IP optimization is generally done with no system application in mind. The concept of a reconfigurable or adaptive processor approach holds great promise here. Implementation readiness: The IP must be signed off against quality metrics, ideally provided by the manufacturer. IP that is silicon ready and system proven is an absolute requirement for the SoC Realization process to work reliably. IP delivery and packaging: The SoC architect needs to be able to browse an IP repository for suitable choices and select the right IP to insert in the assembly. A complete IP deliverable should include all the above views but also a number of generated views, including IP-XACT (a standard developed by Accellera), datasheet, power model (for use in architectural analysis), TLM model (a standard developed by the Open SystemC Initiative), dashboard status and HTML entry in a yellow pages browser.

·

·

·

·

S O C C REATION

SoC assembly covers all phases of building the SoC description and validating its suitability to meet PPA (power, performance and area) goals. · Assembly: Few design teams have the opportunity to start from scratch. An important requirement is the ability to import legacy design data ­ both components and designs ­ from standard languages such as Verilog, VHDL, SystemVerilog, SystemC and associated documentation. Additionally, assembly must provide support for intuitive and highly productive incremental methods for stitching, significant focus on correct-byconstruction assembly, and flexible hierarchy manipulation. The system also needs broad, deep and customizable rule-checking to provide real-time feedback on hookup.

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·

PPA feasibility: It is essential that the integrator get early feedback on potential PPA problems. Designers need to re-characterize performance, power and the physical floorplan as assembly of the SoC evolves. Implementation planning: While functional focus is on end-point IPs, the bus fabric and the memory subsystem, it is not unusual to find 60% or more of the integration task dedicated to control functions such as power management, test and debug, clock and reset, IO and other logic. These subsystems have close interdependence with the functional subsystem and with each other. Planning and efficiently creating this logic (given that it may need to be ripped up and redesigned following functional changes) is a critical part of the assembly task. Further, this is the stage where high-level power intent is mapped to the detailed implementation. Physical planning: Floorplanning to cluster blocks that perform together or are in some way relevant to each other is an important step. This can avoid unnecessarily long routing in the implementation phase that introduces timing and latency issues. Floorplanning is then used as a directive for the Silicon Implementation phase. Implementation readiness: Readiness testing at this stage is an iterative task, tightly coupled with assembly. The intent is to have exercised all degrees of freedom available at the SoC Realization level for an optimal design. This will ensure successful implementation at the Silicon Implementation phase where the degrees of design optimization are significantly less.

·

·

·

S O C H ANDOFF

These steps prepare the assembled SoC for delivery both to downstream silicon implementation and to upstream system designers. This phase recognizes and leverages the fact that the assembly phase has gathered all important information to drive these tasks ­ therefore, there is really no need to require manual assembly of simulation and emulation setup and other tasks. The flow of information is automated, both reducing human error and increasing the opportunity to drive additional experiments in verification and silicon implementation. · Consistency checking: However the initial SoC specification was defined, whether through high-level models or table-based requirements, it is important to check consistency between the multiple dimensions of the elaborated design and the initial specification. This process today is often very ad-hoc and manual; a more predictable approach would ensure that initial requirements capture and subsequent checking against the design would be more structured and automated. Validation setup: Functional verification and validation continues to be a dominant task in full system delivery. SoC Realization provides the bridge from creation to verification through such tasks as generating a simulation control file, re-partitioning designs on the fly to target FPGA emulation, segmenting IP to achieve higher throughput verification runs and generating exception lists for coverage analysis.

·

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Virtual platform delivery: At this stage a virtual platform model that is faithful to the assembly model is delivered. It should be a portable (i.e., not dependent on hardware simulators/emulators/FPGA prototypes), cost-effective software model of the SoC that can be used to validate software development against the SoC as required. These models support bare-metal software development and validation with high confidence against the actual implementation. Verification that application software compatibility is maintained can be done with these models as well. The approach assumes that TLM models (at some level of accuracy, typically cycle-accurate) are available for each IP. Implementation setup: A part of implementation setup looks quite similar to validation setup, in that the assembly environment has most of the information required to create control files for synthesis, automatic test program generation (ATPG), place and route, etc. In addition, documentation can be auto-updated for multiple purposes, such as spec documentation, user documentation, product engineering documentation and so on. This is all in an attempt to ensure that design coherence from the product vision to the silicon implementation is maintained. Customer signoff package: This step ultimately results in the informal contract as to what will be delivered to the consumer of the SoC, whether internal or external. The package should include the final software interface files, power and performance profiles against a variety of use-cases, area (or equivalently, cost), package information including BGA pinout(s), IBIS models, BSDL files and muxing configuration tables, interrupt maps and external pins (if any), power management configuration tables and user documentation.

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SoC Realization | The linchpin to enabling electronics innovation Chapter 3: SoC Realization

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C ONCLUSION

Traditional EDA tools and methodologies have served the semiconductor and systems industries well and will continue to in the future. They are valuable links in the chain and provide the critical connection to advanced manufacturing processes as they scale according to Moore's Law. Increasingly there is a need for a much more robust and integrated ecosystem for preparing SoC designs better and more efficiently for handoff to that traditional EDA space. This void includes ways to evaluate and integrate IP blocks, verify systems containing hardware and software, and assemble those systems that have been more abstractly defined by OEMs and system architects. SoC Realization represents the next evolutionary step in the extension of EDA as it moves up another notch in abstraction and delivers new levels of value to system and semiconductor companies. In order to achieve the vision for true SoC Realization, a variety of tools and methods must be developed and integrated. The results will be a development approach that is much more in sync with the needs of the rapidly changing software rich electronics industry and continued worldwide growth of this promising business.

For more information on the tools and methodologies needed for SoC Realization, visit www.atrenta.com/soc-realization.

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