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Presenter Name Dan Kochpatcharin

Title orDirector job function Deputy Director, IP Portfolio Marketing

Design Infrastructure Support

TSMC Property

· Active Accuracy Assurance (AAA) Initiative · Accuracy-Centric Design Support Data

­ Model Accuracy ­ Tool Qualification ­ Comprehensive PDK

· Efficiency-Centric Design Methodology

­ SoC Design Platform ­ Low-power Approach

· Quality Centric IP/Lib Portfolio Support Quality-Centric

­ Availability ­ Quality

· Complementary Design Service Support

IP Strategy St t

TSMC Property

· Accelerate the development of IP ecosystem · Implement TSMC internal operation as "enabler" · S t first priority on foundation IP ( t d d cell, memory, Set fi t i it f d ti (standard ll ) p standard I/O) development · Provide TSMC validated "enablement circuits" to ecosystem partners f fast IP development for f d l

­ E.g. Serdes, Osc, PLL, DLL, Bandgap Ref, VCO, etc.

· Complement ecosystem partner in foundation IP and application IP development · Re-optimize IP with the process evolution

IP Strategy St t

Development Acceleration D l tA l ti

TSMC Property

eFlash

Accelerated IP Development

1T SRAM eFuse

DAC ADC USB DDR PCIe ARM MIPS PLL DLL Std Cell I/O, SRAM

Normal Market Dynamics

Time

IP Strategy St t

Many C M Considerations id ti

TSMC Property

Price & Schedule

Platform IP Vendors

....... Audio AD/DA HDMI SIMG SLI V1.3 V1.1 DDR USB GPIO Portable consumer .......

Application platforms

Spec variations

DTV

Baseband

Wireless .......

90

80

65

55

45

Technologies

Most Comprehensive IP Portfolio M tC h i P tf li

1800

TSMC Property

Over 1600 IP from 40+ vendors including TSMC Closest competitor has less than half Proper balance between advanced and mainstream portfolio

1600

90nm,65nm,45nm

1400 1200 1000 800 600 400 200 0 TSMC foundry1

0.13µm,0.18µm,...

foundry2

foundry3

Source: Chip Estimate, Design&Reuse, TSMC

Segment F S t Focus

TSMC Property

LP Focus Segments G/GT/GP Focus Segments

Mo bile Cel lula r Portable Consume r Digital Office Data Center

IP Categories C t i

IP List Li t

Wireless

Digital Home

Foundation Library/IP

Standard Cell Memory Compilers GPIO, 2.5V -> 1.8V OD 3.3V 800MHz~1GHz -> 2-3G PLL SD/MMC I/O Mobile DDR I/O DDR2 -> DDR3 Phy DLL USB2.0 OTG Phy PCI-e Gen 1/Gen 2 SATA 1.5G/3G -> 6G MIPI Phy HDMI Tx/Rx LVDS Tx/Rx LVDS I/O Xaui/Double Xaui 10 12.5Gbps 10~12 5Gbps Serdes TCAM OTP/ MTP Electrical Fuse Emb DRAM N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A

N/A N/A

N/A N/A

Memory Interface High Speed Interface Storage Interface Display

Networking

N/A N/A N/A N/A

Embedded Memory y

N/A

TSMC QA S t System

TSMC Property

Available IP in market

DRC/LVS ESD Silicon Report p

DDR

USB

TSMC-Online TSMC OnlineSM

SRAM SATA DAC DSP LVDS ADC

Production History

TSMC IP QA System

MCU Others

Design Margin Data Consistency

QA A Acceptance L t Level l

TSMC Property

Sub-Level

Level V Customer Product

1) Prototype 2) Production

QA Level

Level IV Evaluation deliverables

1) Remote test-run facilities 2) Models/Test-board availability

Level III Silicon verification

1) Functionality 2) Performance

Level II Handover Deliverables

1) IP documentation and deliverables acceptance 2) Design-for-Test and test deliverables acceptance 3) EDA tool views acceptance 4) QA acceptance

Level I Product definition

1) Definition of documentation and deliverables 2) Definition of design-for-test and test deliverables D fi iti fd i f t t d t t d li bl 3) Definition of EDA tool support

Acceptance level

Compliance Status on TSMC-Online C li St t TSMC O li

TSMC Property

Tight S Ti ht Screening for Quality i f Q lit

TSMC Property

Pre-screen Pre screen

# IP: 1052 Failure rate: 9.2%

Level-I Level I

# IP: 982 Failure rate: 11.8%

Summary

Level-III Level III

# IP: 85 Failure rate: 52.2%

PrePre-screen Type

Library SRAM Other Memory IP Total

LevelLevel-I

LevelLevel-III

Library Library/I Lib/IP Fail Library/I Fail Fail Lib/IP Lib/IP /IP P passe IP/Lib P IP/Lib IP/Lib p passed p passed count % count d % count % 509 462 9.2% 498 452 9.2 % 30 6 80.0 % 216 162 25.0% 203 165 18.7 % 81 43 46.9 % 300 133 1158 295 133 1052 1.7% 0.0 % 9.2 % 286 127 1114 279 86 982 2.4 % 32.3 % 11.8 % 48 19 178 22 14 85 54.2 % 26.3 % 52.2 %

Summary S

TSMC Property

· Comprehensive IP support from IP Vendors · Quality · P t Partnership Focus with IP Vendors hi F ith V d

Thank you o

TSMC Property

· Explore IP developed for TSMC at ChipEstimate.com · U TSMC foundry to plan your next chip! Use f d t l t hi ! · Please stay and talk with Dan Kochpatcharin

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