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Switching & Logic

Spring 2008

jeg/Rev 1

Lab 5 -- Pre-Laboratory Exercise

We will try to understand the inner working of counters using state diagrams and timing diagrams in this pre-lab.

State Diagram

A state diagram is a graphical representation of the states or unique output combinations from a group of related flip-flops. In the laboratory exercise decade down counters will be designed. The state diagram for this counter using decimal notation is shown in Figure 1.

9 0

Clk

Clk

8

Clk

7

Clk

1

State Transition Condition

Clk

6

Clk

2

Clk Clk

5

Clk Clk

3 4

Figure 1 Decimal Counter State Diagram

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Switching & Logic

Spring 2008

jeg/Rev 1

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Switching & Logic Group Members: ____

Spring 2008

jeg/Rev 1

_________________________________

________________________________________________ ________________________________________________ Laboratory Day ____________________________________ (Mon, Tue, Wed, Thur)

In the space below redraw decimal state diagram with the states translated from decimal to binary notation.

CLK

Q3Q2Q1Q0

The states in binary notation represent the outputs of four D flip-flops designated as Q3, Q2, Q1 and Q0 respectively. The Clk transition condition indicates that the counter only changes state on the leading edge of the counter clock pulse.

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Switching & Logic

Spring 2008

jeg/Rev 1

Timing Diagram

A timing diagram can be drawn that shows the value of Q3 through Q0 as it develops with each rising clock transition. The values are drawn with time evolving in a left to right manner. Complete the time diagram for the decade counter that was started in Figure 2. Note the state of any of the bits may only change on the rising edge of the clock pulse.

9 8 7 6 5 4 3 2 1 0

Clk Q3 Q2 Q1 Q0 Time

Figure 2 Decade Counter Timing Diagram

Complete this pre-lab and turn into the laboratory assistant on entering the laboratory.

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Microsoft Word - Lab 5 Prelab.doc