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Agilent De-emphasized Signal Generation with the Agilent 81250A ParBERT

Application Note

Overview

De-emphasis and equalization are commonly used techniques when transmitting electrical and optical signals at gigabit data rates. The term de-emphasis is used to describe signal conditioning on the transmitter, while the term equalization is used on the receiver side. Figure 2 shows the channel model with embedded loss. The Tx output uses de-emphasis, the Rx input uses equalization to improve signal integrity.

De-emphasis and equalization compensate for signal integrity issues caused by the loss in the channel on printed circuit boards, backplanes, and fiber optic links. The most popular high-speed electrical standards require transmitter de-emphasis. These standards are: PCI Express®, SATA 3 Gb/s, fully buffered DIMM, HyperTransport, CEI, and 10-Gb Ethernet. Figure 1 shows the principle waveform of a de-emphasized signal (two-tap). Sometimes this is called pre-emphasis, as one could see a boost of amplitude for the first cycle after a transition occurs. However, usually the signal's amplitude is reduced after a delay of 1 unit interval (UI) when the data content does not change. From this point of view the method is called de-emphasis. [1]

Figure 2. The channel model with embedded loss

This document explains how a de-emphasis can be achieved when using the Agilent 81250A ParBERT and covers the following topics: · The problem with inter-symbol interference (ISI) · Channel description, frequency domain · The definition of a de-emphasis frequency domain · Standards using a de-emphasis · Implementing a de-emphasis with ParBERT channels · How to configure the setup for IEEE 802.3ap (10 GBASE­ KR) [3] and IEEE 802.3aq (10 GBASE­LRM) [4]. Note: As a prestudy, the De-emphasis Application Note [1] and the Agilent N4916 De-Emphasis Signal Converter Signal Generation Data Sheet [2] are recommended.

Figure 1. The normal and complement waveform of a de-emphasized signal and its data content

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The Problem with ISI

Signal integrity issues on printed circuits, motherboards, and connectors arise from loss and reflections in the transmission channel that decreases signal performance. Loss causes eye closure or inter-symbol interference (ISI)-type of jitter. [5] Figures 3 to 5 show the eye closure/ISI from a data signal running through a 12-inch motherboard, while starting with a data rate of 2 Gb/s the data rate is doubled with each iteration. The eye closure/ISI reading is summarized in Table 1. The finding is that the eye closure/ISI jitter does not increase linearly with data rate. Instead, it increases with a higher magnitude than the data rate increases. This behavior results from the frequency-dependent loss of the trace on the motherboard. This is explained in the Channel Description section.

Table 1. Eye closure caused by ISI, depending on data rate

Figure 3. Signal from a PC board trace at 2 Gb/s

Data rate

Eye closure

2 Gb/s

44 mUI

4 Gb/s

122 mUI

8 Gb/s

431 mUI

Figure 4. Signal from a PC board trace at 4 Gb/s

Figure 5. Signal from a PC board trace at 8 Gb/s

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Channel Description

Frequency domain

One method to describe the channel characteristics is with the help of the scattering (S) parameters. [6] S-parameters describe the insertion and transmission behavior as a function of frequency. S21 describes the transmission behavior; it is a complex figure with real (magnitude) and imaginary (phase) parts. Figure 6 is the example of the magnitude of S21 (|S21|) of the motherboard used for Figures 3 to 5. It is important to understand that Figure 6 displays the magnitude only, which can be expressed as the loss. This loss typically has three root causes: · Di-electric conductivity · Skin effect (resistance in the surface of the conducting material) · Radiation The ISI cannot be explained by the |S21| alone. The S21 is a complex figure and can be represented with magnitude and phase relation. The phase relation is depicted in Figure 7. The S21 of an ideal device will show a straight line. The red curve shows the phase to rotate between ­180 degrees to +180 degrees for frequencies above 7.5 GHz. This means the frequency content above 7.5 GHz may be earlier or later than the frequency constant at lower frequencies. This kind of representation is limited to ±180 degrees. It cannot be seen if there are frequency components earlier/later than ½ UI.

Start .5 GHz

Start .5 GHz

Stop 10.5 GHz

60 degrees

Stop 10.5 GHz

10 dB

Figure 7. The phase of S21, above 7.5 GHz the phase gets non-linear

Figure 6. The |S21| of a PC board trace, the frequency on the x-axis is from 0.5 to 10.5 GHz, the y-axis scale is 10 dB/div

Figure 6 shows that the loss curve is not linear. The loss increases with a higher magnitude. The curve also shows some sharp dips. These dips are caused by two (or more) impedance mismatch points. Between such impedance mismatch points the PC board trace acts like a resonator for a certain frequency. At this frequency we obtain a standing wave within this resonator and this causes radiation, similar to that from an antenna. This specific radiation lowers the curve in the dips by another 10 to 20 dB.

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Time domain

Another way to describe ISI is with the help of the impulse/step response in the time domain. We send a single pulse into a PC board trace and record the output signal. Figures 8 and 9 depict the corresponding input and output signal with the same amplitude and timing scale for comparison. The pulse received from the PC board trace has changed in: · · · · Amplitude Edge speed Width Settling time

Figure 8. Input signal to the PC board

1 UI

Figure 9. Output signal from the PC board, the received pulse is attenuated and changed in 1 UI

The issues with the amplitude reduction and the settling time spreading out over multiple UIs are the reasons for the name ISI. The levels and the position of a pulse depend on the history. The settling explains why multiple consecutive bits are affected.

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Figure 10 shows the effect of ISI on a stream of data bits (PRBS7.) It is clearly visible how the levels of short bits depend on the history. Some standards use the ratio of reduced amplitude versus full amplitude as a metric for the ISI. With the help of the eye diagram in Figure 11 we also see the different positions in time of the edges. The positions depend on how many bits have the same value before the transition. As a rule of thumb, as more bits have the same value, the edge occurs later and a transition after a transition occurs earlier. The difference between earliest and latest transition is called ISI jitter.

Figure 11. Output signal from the PC board, multiple bits from the PRBS pattern shown as an eye diagram

The root cause of the distortion comes from the frequencydependent loss and phase relation as discussed in the Frequency Domain section. The frequency-dependent phase can especially cause different distribution times for each of the frequencies involved, which is expressed as: the group delay is not constant. Such effect is well known for optical links. In that instance it is called dispersion. It makes sense to leverage the wording from the optical to the electrical domain.

Figure 10. Output signal from the PC board, multiple bits from the PRBS pattern over time

In conclusion, we can say ISI is caused by pulse dispersion, or in the case of dispersion we will obtain ISI. The model of the pulse dispersion helps to understand the digital method of compensating for the ISI, which is explained further in this document.

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How to compensate

Ideally the de-emphasis and the equalization invert the channel behavior. The first attempts to do so used analog high-pass filters for compensation, see Figure 10. As this degrades noise performance of a system, this was not widely accepted. As a practical implementation, a chain of flip-flops clocked on UI basis is used, according to Figure 13. All flip-flop outputs are added together with variable gain. Consecutively we obtain a signal with advanced and delayed components, which add/subtract some adjustable energy to the original signal. As advanced signals are impossible to be generated, the implementation will use the main channel from the middle of the flip-flop chain.

Input signal

Output signal

Clock

Data

Gain & polarity

N-1

Figure 12. High pass filter to approximate channel inversion

N

+

N+1

Now the idea is to re-store the original shape by canceling out the energy before and after the cursor. Basically we pre-condition the signal by subtracting some energy before (pre-) and after (post-) the cursor. This is called pre- and post-cursor. As can be seen from Figure 9, the time of dispersion may spread over multiple UIs. Theoretically, we could think of dividing the time before and after the cursor in infinitesimal small windows and do the correction by adding/subtracting a small portion of energy. Practically, the granularity for the correction window is 1 UI, which can be derived from the underlying period in the data signal.

N+2 N­1 N N+1

Figure 13. Flip-flop chain approach to approximate the inversion of the step response

As shown in Figure 9 the real world dispersion is asymmetrical, the dispersion is more in time and magnitude on the right side. This indicates the higher need for the delayed signal. Basically, a rule of thumb for setting up compensation is: 1. Add a delayed signal (+1 UI) to the original signal 2. Add a advanced signal (­1 UI) 3. Add a second delayed signal (+2 UI)

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The Definition of a De-Emphasis

Figure 14 depicts a two-tap solution. One cursor is added to the main path; this cursor is delayed by 1 UI. This addition is a subtraction; the signal levels are lower after the 1 UI delay than after a transition. Figure 16 depicts a three-tap solution. There is a cursor before and after the main transition. In reference to the two-tap solution. The third tap is the precursor.

Input

x

1 UI delay

+

Output

x

1 UI delay

c(­1)

+

x

C(0)

+

x

C(+1)

­1

1 UI delay

c(0)

x

c(1)

Figure 14. Block diagram of a two-tap de-emphasis Figure 16. Block diagram of a three-tap de-emphasis

The output parameters are defined by C(0) as the transitional amplitude and C(+1), which reduces (C0) to the de-emphasized amplitude. The relation of C(+1)/C(0) is defined by the parameter of the de-emphasis value either as the ratio shown in equation (1) or in dB as shown in Equation (2):

The output parameters are defined by C(0) as the transitional amplitude, C(+1) and C(­1). The definition for the de-emphasis values are: Vpre Vss Vpst Vss

Rpre = ­

(Equation 3)

R = Vpre/ Vde R = 20 * log (Vpre/ Vde)

(Equation 1) Rpst = ­ (Equation 2) (Equation 4)

In reality the signal gets subtracted after a 1 UI delay. This results in a waveform shown in Figure 15.

It should be noted that the valid ranges of C(1) and C(­1) coefficients may have positive or negative values. Figure 17 shows the definition of the amplitude parameters of a three-tap de-emphasis.

Vpst

Vpre

Vde

A

Square wave test pattern (n 8)

Vss

Test pattern with equalization

Figure 15. Definition of the amplitude parameters of a two-tap de-emphasis

O

t0 Vpre ­A T

t1

Figure 17. Definition of the amplitude parameters of a three-tap de-emphasis

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Standards Using a De-Emphasis

PCI Express [7]

The PCI Express standard defines the de-emphasis by: Subsequent bits are driven at a differential voltage level (­3.5 ±0.5 dB at 2.5 GT/s and either ­3.5 ±0.5 dB or ­6 ±0.5 dB at 5.0 GT/s) below the first bit. At 5.0 GT/s de-emphasis is selectable via configuration register bits. The two de-emphasis values defined for 5.0 GT/s operation permit optimum equalization for both short, reflection dominated channels, and long, loss dominated ones. Note that individual bits, and the first bit from a sequence in which all bits have the same polarity, must always be driven between the minimum and maximum values as specified by VTX-DIFF-PP... The de-emphasis level is defined via CSR bits... Figure 18 shows the de-emphasized signal as defined by PCI Express Rev 2.

HyperTransport [8]

The HyperTransport standard defines a three-tap de-emphasis by: To support longer high loss channels for Gen3AC an additional post-cursor setting of ­11 dB is defined, as well as a pre-cursor setting of ­ 8 dB. Figure 19 shows the de-emphasized signal as defined by HyperTransport Gen3 for long, high loss, AC coupled channels.

Figure 19. The de-emphasized signal as defined by HyperTransport Gen3 for long, high loss, AC coupled channels

IEEE 802.3ap (10 GBASE­KR) [3]

The 10 GBASE­KR standard defines a three-tap de-emphasis similar to HyperTransport Gen3AC. The transmitter output waveform is based on three voltages: Vpre, Vpst, and Vss. The transmitter output waveform is verified with the square wave test pattern with n greater than or equal to 8.

Figure 18. The de-emphasized signal as defined by PCI Express Rev 2

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LRM (Long reach multi-mode, IEEE 802.3aq) [4]

The characteristics of the stressed test signal are defined in Chapter 68.6.9.2 of the IEEE 802.3aq standard and are based upon the parameters in Table 2. These parameters and the definition in Chapter 68.6.9.2 of the standard describe an ISI generator as a tapped delay line with four weighted taps having equally spaced delays. The resulting de-emphasis is illustrated in Figure 20. In addition to this impulse shaping, the standard requires the addition of Gaussian white noise as stress.

Table 2. Coefficients for the three defined channel characteristics of LRM Tap spacing, t, of ISI generator Pre-cursor tap weights {A1, A2, A3, A4} Symmetrical tap weights {A1, A2, A3, A4} Post-cursor tap weights {A1, A2, A3, A4} -- -- 0.75 {0.158, 0.176, 0.499, 0.167} UI

Figure 20 illustrates the three cases of de-emphasized signals as defined by the 10 GBASE­LRM standard

Pre-cursor pulse signal

Symmetric pulse signal

--

{0.00, 0.513, 0.00, 0.487}

--

{0.254, 0.453, 0.155, 0.138}

A2 A4 A3 t t t Time

Post-cursor pulse signal

A1

Figure 21. The timing definition for the cursor characteristics of 10GBASE-LRM

Figure 20. The three cases of de-emphasized signals as defined by IEEE 802.3aq (10GBASE-LRM)

Specific to this standard is the spacing of the cursors. In contrast to the prior examples shown in this document, here the spacing is less than 1 UI. The spacing required is 75 ps instead of 1 UI of 97 ps (10.3125 Gb/s.) as illustrated in Figure 21. The standard defines a comprehensive stressed receiver test procedure: ...the three ISI impairments...together with the appropriate OMA values...define six discrete signal conditions...select the required ISI...set the attenuator and Gaussian white noise source to obtain...the stressed sensitivity in OMA...Connect the test signal to the system receiver TP3 and a BER of better than 10 ­12 shall be achieved for each case Refer to How to configure the Isetup for IEEE 802.3ap and IEEE 802.3aq to setup the PaRBERT 81250A for these requirements.

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Implementing a De-Emphasis Using ParBERT Channels

Creating a three-tap de-emphasis with three generator channels

An 81250A ParBERT [9], [10] with three N4872A generators are used for the following experiment. The generator outputs are combined with help of two, 3-way 11636B power dividers as shown in Figure 22. The setup is asymmetrical for the three channels. A power divider comes with 6 dB attenuation (equals amplitude x.5) from input to output. Two channels run through two dividers, one channel through one only. So it is recommended to use the path with one divider only for the main channel and the channels responsible for pre- and post-cursor run through two dividers. Figure 23 shows the signal as obtained from the three-tap solution with programming values as given in Table 3. The signal as shown is obtained with a repetitive pattern of 8x ,0's followed by 8x ,1's. The connections of all three channels are done from the normal outputs. The channels for pre- and post-cursor are inverted from the user interface. The inversion causes the subtraction from the main channel. Practically proven is that the pre-and post-cursor always subtract from the main channel.

Figure 23. The three-tap signal at 10 Gb/s based on a repetitive 0000000011111111 pattern Figure 22. Two, 3-way divider combining the outputs of three modules Table 3. ParBERT programming for the three-tap signal

Timing wise, there is a propagation delay difference for the main channel which occurs ~250 ps earlier in the setup as shown. As a result, the setup needs a careful timing alignment. This is performed with the help of the deskew editor. The procedure is similar to that discussed in the next section of this document.

Main

Delay Levels Polarity 1 UI ±0.5 V Normal

Post_1

2 UI ±0.3 V Inverted

Pre

0 UI ±0.1 V Inverted

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Creating a four-tap de-emphasis with four generator channels

Four generators are combined with help of one, 5-way power divider (Aeroflex/Weinschel 1594 [11].) Refer to Figure 24. This setup is symmetrical as the five-way divider is symmetrical for all five connections.

Table 4. ParBERT programming for a four-tap signal

Main

Delay Levels Polarity 1 UI ±0.5 V Normal

Post_1

2 UI ±0.25 V Inverted

Pre

0 UI ±0.15 V Inverted

Post_2

3 UI ±0.15 V Inv (norm)

The experiments with various PC board traces show that the second post-cursor is needed without inversion. That is the reason why in Table 4 the polarity of post-cursor 2 is listed as "inv/(norm)". The delays of the four generators are adjusted to obtain a signal view as shown in Figure 26. It is important that the x-point of the four-channel occur at 50 percent of amplitude and with a 100 ps spacing (1 UI at 10 Gb/s.) The relative delay is important, not the absolute. The Timing calibration of the channels is performed with help of the 81250A ParBERT deskew editor.

Figure 24. Five-way divider combining the outputs of four modules

The four-tap signal is shown in Figure 25 with the programming values according Table 4. In this case, the second post-cursor is added inverted (subtracted) as the other cursors.

Figure 26. Calibrated four-tap signal at 10 Gb/s with a repetitive 00000001 pattern in each channel Figure 25. The four-tap signal at 10 Gb/s based on a repetitive 0000000011111111 pattern

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De-Emphasis Labs with PC Board Traces

Lab 1: A short de-emphasis lab with three different PC board traces: The improvement while adding taps for a 320 mm PC board trace (one of three.)

All experiments on this and the consecutive pages are performed at data rate of 10 Gb/s and the setup with the five-way divider described in the prior section. All experiments begin with the main channel stimulating a PRBS7 pattern while the other channels send a PAUSE0. The post1-cursor is then added by sending the same PRBS7 delayed by 1 UI. The pre-cursor channel is added by sending the PRBS7 by 1 UI earlier (in reference to the main channel.) Finally, the post2-cursor is added by sending the PRBS7 by 2 UI later (in reference to the main channel.) All cursor amplitudes are varied until the optimum eye opening is obtained. Table 5 lists the values for each of the cursors including the eye closure expressed by the remaining ISI value for a PC board trace 320 mm in length. Again, the cursors are added incrementally from left to right in Table 5.

Table 5. Programming values and resulting ISI for the 320-mm trace

Figure 27. Step response of the 320 mm trace, 00000001 pattern, no de-emphasis

320 mm

Delay Levels Polarity ISI

Main

1 UI ±0.8 V Normal 0.36 UI

Post_1

2 UI ±0.18 V Inverted 0.14 UI

Pre

0 UI ±0.038 V Inverted 0.13 UI

Post_2

3 UI ±0.038 V Inverted 0.1 UI Figure 28. Eye Diagram of the output of the 320 mm trace, PRBS7, no de-emphasis

Figure 27 shows the step response without any de-emphasis applied. This is taken with a pattern consisting of a single "1" surrounded by many "0"s. As can be seen, the step needs roughly 3 UI to settle 100 percent. Consequently, the eye is closed by roughly 1/3 as shown in Figure 28. Figure 29 adds the first post-cursor. The improvement of the eye opening is significant. The addition of pre- and post2-cursor (Figures 30 and 31) still improve the eye opening, but the necessary amplitudes for an optimization are small and the improvement is small.

Figure 29. Eye diagram of the output of the 320 mm trace, PRBS7, optimized two-tap de-emphasis

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Figure 30 depicts the step response with all three cursors in place (single one pattern, same as for Figure 25.) As can be seen, the step response is now clean and the signal settles mostly to 100 percent after one UI.

Figure 33. Waveform of the optimized four-tap de-emphasized input signal for the 320 mm trace

Figure 30. Eye diagram of the output of the 320 mm trace, PRBS7, optimized three-tap de-emphasis

Figure 31 shows the stimulus signal with all three cursors in place. The post1 cursor is dominant the pre- and post2cursors are hard to see as the programming values are small at the optimum setting.

Figure 32 illustrates the corrected step response with the optimized 4-tap de-emphasis in place for the 320 mm pc board trace (repetitive pattern of 00000001). Figure 33 shows the waveform of the optimized 4-tap de-emphazised signal which is sent into the 320 mm pc board trace (repetitive pattern of 0000000011111111).

Lab 2: A short de-emphasis lab with three different PC board traces: The improvement while adding taps for a 535-mm PC board trace (two of three)

The second example is done with a PC board trace 535 mm in length. Figure 34 shows the step response without any de-emphasis applied (this is taken with a pattern consisting of a single "1" surrounded by many "0"s.) As can be seen, the step needs roughly 5 UI to settle 100 percent. The eye is totally closed as shown in Figure 35 with the main signal only. Figure 36 adds the first post-cursor. The improvement of the eye opening is significant. The addition of pre- and post2-cursor (Figures 37 and 38) still improve the eye opening, but the necessary amplitudes for an optimization are small and the improvement is small.

Figure 31. Eye diagram of the output of the 320 mm trace, PRBS7, optimized four-tap de-emphasis

Figure 32. Step response of the 320 mm trace with optimized four-tap de-emphasis

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Figure 34. Step response of the 535 mm trace, 00000001 pattern, no de-emphasis

Figure 35. Eye Diagram of the output of the 535 mm trace, PRBS7, no de-emphasis

Figure 38. Eye diagram of the output of the 535 mm trace, PRBS7, optimized four-tap de-emphasis

Table 6 lists these values for each of the cursors including the eye closure expressed by the remaining ISI value for a PC board trace 535 mm in length. Again, the cursors are added incrementally from left to right in Table 6.

Table 6. Programming values and resulting ISI for the 535-mm trace

535 mm

Delay Levels Figure 36. Eye diagram of the output of the 535 mm trace, PRBS7, optimized two-tap de-emphasis Polarity ISI

Main

1 UI ±0.8 V Normal Closed

Post 1

2 UI ±0.19 V Inverted 0.16 UI

Pre

0 UI ±0.02 V Inverted 0.14 UI

Post_2

3 UI ±0.025 V Inverted 0.12 UI

Figure 37. Eye diagram of the output of the 535 mm trace, PRBS7, optimized three-tap de-emphasis

Figure 39. Step response of the 535 mm trace with optimized four-tap de-emphasis

Figure 39 depicts the step response with all three cursors in place (single one pattern). As can be seen, the step response is now clean, the signal settles mostly to 100 percent after 1 UI.

15

Figure 40. Waveform of the optimized four-tap de-emphasized input signal for the 535 mm trace

Figure 41. Step response of the 850 mm trace, 00000001 pattern, no de-emphasis

Figure 40 shows the waveform of the optimized 4-tap de-emphazised signal which is sent into the 535 mm pc board trace (repetitive pattern of 0000000011111111). The post1-cursor is dominating, the pre- and post2-cursors programming values are small at the optimum setting.

Lab 3: A short de-emphasis lab with three different PC board traces: The improvement while adding taps for an 850-mm PC board trace (three of three)

The third example is done with a PC board trace 850 mm in length. Figure 41 shows the step response without any de-emphasis applied. This is taken with a pattern consisting of a single "1" surrounded by many "0"s.) As can be seen, the step needs more than 8 UI to settle 100 percent. The eye is totally closed as shown in Figure 42 with the main signal only. Figure 43 adds the first post-cursor. The improvement of the eye opening is significant. The addition of pre- and post2-cursor (Figures 44 and 45) still improves the eye opening, but the necessary amplitudes for an optimization are small and the improvement is small. The optimized eye opening is still bad as the transition time of the optimized eye is slow. This is also obvious from the Figure 46, which depicts the step response with all three cursors in place (pattern is repetitive 00000001). As can be seen, the step response settles to 100 percent, but not within 1 UI. The de-emphasis does not restore the transition time, so the bandwidth limitation of the long line cannot be compensated and the optimized eye opening remains marginal. Figure 47 shows the waveform of the optimized de-emphasized signal with all three cursors in place. The post1-cursor is dominating, the pre- and post2-cursor's programming values are small at the optimum setting. Note that the optimum post2-cursor in this example adds in contrast to the prior two experiments.

16

Figure 42. Eye Diagram of the output of the 850 mm trace, PRBS7, no de-emphasis

Figure 43. Eye diagram of the output of the 850 mm trace, PRBS7, optimized two-tap de-emphasis

Figure 44. Eye diagram of the output of the 850 mm trace, PRBS7, optimized three-tap de-emphasis

Figure 46. Step response of the 850 mm trace with optimized four-tap de-emphasis

Table 7 lists these values for each of the cursors including the eye closure expressed by the remaining ISI value for a PC board trace 850 mm in length. Again, the cursors are added incrementally from left to right in Table 7.

Table 7. Programming values and resulting ISI for the 850-mm trace

850 mm

Delay Levels Polarity ISI

Main

1 UI ±0.8 V Normal Closed

Post 1

2 UI ±0.5 V Inverted 0.3 UI

Pre

0 UI ±0.05 V Inverted 0.26 UI

Post_2

3 UI ±0.022 V Normal 0.23 UI Figure 47. Waveform of the optimized four-tap de-emphasized input signal for the 850 mm trace

Lab summary

PC board traces have loss and bandwidth limitations, both increase with the length of the trace. The method with de-emphasis by multiple cursors compensates for the ISI caused by the loss and is able to open a totally closed eye. The method is limited for compensating bandwidth limitations: a degraded transition time cannot be compensated. Consequently, the method cannot correct every trace length at every data rate.

Figure 45. Eye diagram of the output of the 850 mm trace, PRBS7, optimized four-tap de-emphasis

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How to Set Up the ParBERT 81250A for IEEE 802.3aq (10 GBASE­LRM)

We use the setup of Figure 24: four modules combined with help of a five-way divider. The timing calibration has to be performed based on the 75-ps spacing and it has to be done channel by channel (in the overlay as shown in Figure 26 one could not see the transitions.) The output of the five-way divider is connected with a 7.46-GHz Bessel Thompson Filter to achieve the required shaping. Another important consideration is the bandwidth of scope to visualize the step response. The step response examples shown in this section assume a scope input bandwidth of 7.5 to 10 GHz. When using higher bandwidth, additional filtering is required. The programming of the four ParBERT channels is given in Table 8. It lists delay, levels, and pattern. Patt1 is a segment consisting of 1000000000000000 (1x ,1`, 15x ,0`.) To visualize the step response, the pattern with a single one is recommended. For a real test the desired pattern (e.g. PRBS) has to be loaded in all four channels except where Table 8 lists the PAUSE0.

Table 8. Programming values for pre-, symmetric, and post-cursor according to IEEE 802.3aq (base LRM)

The Figures 48 to 50 show the three cases as defined by the LRM standard depicted in Figure 20.

Figure 48. Channel characteristic from ParBERT 81250A for pre-cursor definition according IEEE 802.3aq (base LRM)

850 mm

Delay Pre Pre Levels Pattern

Channel 1 Channel 2 Channel 3

0 ps ±0.158 V Patt1 ±0.000 V Paused ±0.254 V Patt1 75 ps ±0.176 V Patt1 ±0.153 V Patt1 ±0.453 V Patt1 150 ps ±0.499 V Patt1 ±0.000 V Paused ±0.155 V Patt1

Channel 4

225 ps ±0.167 V Patt1 ±0.487 V Patt1 ±0.138 V Patt1 Figure 49. Channel characteristic from ParBERT 81250A for symmetric cursor definition according IEEE 802.3aq (base LRM)

Symm Levels Symm Pattern Post Post Levels Pattern

Figure 50. Channel characteristic from ParBERT 81250A for postcursor definition according IEEE 802.3aq (base LRM)

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References

[1] De-Emphasis Application Note, Agilent Technologies, 5989-7193EN [2] Agilent N4916A De-Emphasis Signal Converter, Data Sheet, 5989-7193EN [3] IEEE 802.3ap, Amendment: Ethernet Operation over Electrical Backplanes, Type 10GBASE-KR [4] IEEE 802.3aq, Amendment 2: Physical Layer and Management Parameters for 10 Gb/s Operation, Type 10GBASE-LRM [5] Calibrated Jitter, Jitter Tolerance Test, and Jitter Laboratory with the Agilent J-BERT N4903A, Application Note, 5989-4967EN [6] S-Parameter Techniques, 5989-9273EN [7] PCI Express® Base Specification, Revision 2.0, December 20, 2006 [8] HyperTransport I/O Link Specification [9] 10GbE Technology and Device Characterization with the 81250A ParBERT, 5988-6960EN [10] Agilent ParBERT 81250 Parallel Bit Error Ratio Tester, Product Overview, 5968-9188EN [11] http://www.aeroflex.com/ams/Weinschel/ pdfiles/wmod1550A&1594.pdf

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Revised: July 2, 2009

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"PIC-SIG" and the PCI SIG design marks are registered trademarks and/or service marks of PCI-SIG.

© Agilent Technologies, Inc. 2009 Printed in USA, October 1, 2009 5990-4053EN

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