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Fully-Depleted SOI CMOS for Analog Applications

Jean-Pierre Colinge, Fellow, IEEE (Invited Paper)

Abstract-- Fully-depleted (FD) SOI MOSFET's offer nearideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFET's at high temperature or at gigahertz frequencies is outlined as well. Index Terms-- Analog integrated circuits, HF amplifiers, microwave circuits, random access memories, silicon-on-insulator technology, SIMOX, thermal factors.

In weak inversion the value of the transconductance to drain , can be obtained from the latter relationcurrent ratio, ship (3) And, in strong inversion, becomes [1]

(4) I. INTRODUCTION In all instances, the body factor expression: with is given by the following

A

LTHOUGH most applications of CMOS are digital, there is a growing need for analog functions in mixed-mode integrated circuits. In addition, these analog functions should operate under a low supply voltage. The advantages of fullydepleted (FD) SOI devices for digital applications are well know: sharp subthreshold slope, high current drive, high transconductance, reduced parasitic capacitances, and absence of latchup. As far as analog circuit are concerned, one can take advantage of the high transconductance to drain current ratio and the low body factor of FD SOI MOSFET's to realize circuits operating at low supply voltage and delivering high performance. This paper describes the advantages of using FD SOI for analog applications, at low and high frequencies, as well as at high temperature, for which there is a growing demand as well. II. THE SOI MOSFET

-

(5)

is the capacitance between the channel where C (which is a channel "under formation" in the case of the subthreshold regime) and ground (the back gate in the case of a FD SOI MOSFET or the substrate in the case of a bulk is the capacitance between the gate and device), and C the channel. Typical values for range between 1.3 and 1.5 in a bulk transistor and between 1.05 and 1.1 in a FD SOI MOSFET [2]. We shall now see how this low body factor impacts the performance of analog circuit designs. III. VOLTAGE GAIN

OF A

The body-effect coefficient (also called body factor) of an MOS transistor, which is represented by the letter , is an image of the efficiency of the coupling between the gate and the channel. It plays a role in each regime of operation of the device. In strong inversion, it shows up in the expression of the drain current (1) It is also found in the expression of the subthreshold swing (2)

Manuscript received May 8, 1997; revised October 3, 1997. The review of this paper was arranged by Editor J. G. Fossum. The author is with the Department of Electrical and Computer Engineering, University of California, Davis, CA 95616 USA. Publisher Item Identifier S 0018-9383(98)02964-5.

MOSFET

The maximum voltage gain of a MOSFET is obtained when is largest, since the gain of a transistor the value of is given by [3] (6) where is the output drain conductance and is the Early voltage. The Early voltage of a FD SOI transistor is basically identical to that of a bulk device. The largest value of appears in the weak inversion regime for MOS transistors [4]. Because of the lower value of the body factor in FD SOI MOSFET's, values of significantly higher than in bulk devices can be obtained (Fig. 1). The ratio can be viewed as the quality factor of the device, since the transconductance represents the amplification delivered by the

0018­9383/98$10.00 © 1998 IEEE

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Fig. 1. g =ID ratios in saturation (VD : ) and FDSOI (n (n

= 1+ = 15

m

= 2:5 V) for = 1 + = 1:1) MOSFET's.

Fig. 2. CMOS analog switch. bulk

device, and the drain current represents the power dissipated ratio, the to obtain that amplification. The higher the more efficient the device. The dc gain ( ) and the transition unit-gain frequency and ( ) of a MOSFET are given by where is the Early voltage of the device and is its load capacitance. The high value of FD SOI devices should allow one to realize nearoptimal micropower analog designs. In FD SOI MOSFET's values of 35 V are obtained, while reaches only values of 25 V in bulk MOSFET's, as presented in Fig. 1 [5]. IV. BASIC ANALOG CIRCUITS In this section, basic analog circuit elements are presented. The performances of these elements, implemented using bulk and FDSOI devices, are compared. A. Pass Gate The CMOS analog switch (pass gate) provides a rough estimation of the lowest acceptable analog supply voltage that can be used in a circuit (Fig. 2). In order to transmit a signal without alteration through a switch with the gate of the NMOS transistor held at and that of the PMOS transistor at 0 V, must be larger than a minimum value which can be and body expressed as a function of the threshold voltage factor of the n- and p-channel MOSFET's. The following relationship must be satisfied [6]: (7) being close to 0.7 V and In bulk CMOS with close to 1.5, is classically limited to a minimum supply voltage of 3 V. In FD SOI CMOS with equal to 1.05 and the possibility to lower to 0.4 V without degrading the leakage current performance, can be as low as 0.85 V. This confirms the potential of FD SOI CMOS for lowvoltage analog applications, for example when using switchedcapacitor circuits. Circuits based on SOI pass gates and operating at a frequency of 260 MHz under a 0.5 V supply

(hybrid bipolar-MOS transistors, V in the off state and 0.05 V in the on state) have been demonstrated [7]. One important application of pass gates is the pass transistor of RAM cells, although, in this case, a single n-channel transistor is used to transmit the information between the bit line and the memory cell. Although DRAM's are not analog circuits, some transistors, such as the access transistors connecting a storage capacitor to the bit line and the sense amplifier transistors perform tasks which can be considered as more analog than digital. It is, therefore, of interest to briefly discuss the "analog" performance of SOI MOSFET's in these particular devices. In general, the advantages of SOI for DRAM's are a reduction of the bit line capacitance (by 25% compared to bulk), a reduction of the access transistor leakage current, and the reduction of the soft-error sensitivity. As a result, storage capacitance of 12 fF is sufficient for a 256 Mb, 1.5 V DRAM realized in SOI, while 34 fF are required for the equivalent bulk device [8]. The advantage of using SOI, in terms of reducing the memory cell area, is then obvious. It is also possible to realize DRAM's which can operate with a sub1 V power supply (which has not yet been demonstrated in bulk) [9], [10]. In order to achieve this level of performance, a ratio must be achieved ( and are the bit reduced line and the storage capacitances, respectively). The reduction of the bit line capacitance comes "for free" with the use of is achieved through the cell SOI, while the increase of design. Considering the cell retention time, it has be shown that thin-film SOI MOSFET's have a much lower leakage current than bulk or thicker SOI devices. Off-state leakage currents smaller than 1 fA/ m are indeed observed in FD, thin-film devices [11]. All the above features render SOI technology quite interesting for DRAM applications, but, most importantly, the DRAM architecture can take full advantage of the low body effect found in SOI devices. Indeed, bulk pass transistors suffer from body effect during the storage capacitor charging state, such that the word line voltage has to be boosted to , where compensates for the increase in the bulk pass transistor due to the body effect. Thus the body effect becomes a major issue in bulk pass transistor design [12]. As we already know from (7), the use of FD SOI significantly improves the performance of pass gates because of the low body effect found in SOI devices.

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Fig. 4. Synthesis of bulk (--) and SOI (- -) Miller amplifier for CL = 10 pF and fT = 10 MHz.

Fig. 3. Charging efficiency as a function of gate voltage overdrive [30].

In contrast to what happens in a bulk device, the body potential of a partially-depleted (PD) transistor follows the source node potential during the charging, so that the body-tosource potential difference is kept at a constant value. For FD SOI transistors there is no body potential change. Therefore, SOI transistors have a higher charging efficiency compared to bulk transistors. If the charging current is designed to be 1 A/ m, then the charging efficiency, defined as the ratio of source (the storage node) voltage at 1 A/ m to the drain (the bit line) voltage, is 80% for bulk transistors, and 88% and 98% for PD and FD transistors, respectively (Fig. 3). The higher charging efficiency of SOI transistors results in higher programming speed for the DRAM cell. At time ns after being activated by the word line a FD transistor can transfer 10 times more charge than a bulk transistor. For a bulk pass transistor to the same charging efficiency as an SOI transistor, the word line voltage has to be increased during the charging. As shown in Fig. 3, to reach a 90% charging efficiency, the gate voltage of a bulk transistor has to be 0.6 V higher than that of a FD SOI MOSFET. Such an increased word line voltage can degrade gate oxide integrity and is also not favorable for low-power operation. As a result of these considerations, it is possible to fabricate low-voltage DRAM's in SOI, such as the 16 Mb device demonstrated by Mitsubishi in 1966, which can operate with a supply voltage as low as 0.9 V [13], [14]. Bulk DRAM's operating under such a low supply voltage are yet to be demonstrated. B. Operational Amplifiers CMOS operational amplifiers (op amps) can be designed on the basis of the knowledge of and the Early voltage as a function of the scaled drain current [15]. This design technique was used to synthesize a simple one-stage ) and output opamp with specified active device size ( capacitance ( ). Fig. 4 clearly shows that the dc gain, , of the SOI amplifier is 25% to 35% larger than in bulk, while is reduced in the same proportion. the static bias current Fig. 5 shows the results of such a design, carried out under the assumptions that is close to 1.1 and 1.5 for FD SOI and

Fig. 5. Layout of a simple low-power Miller operational amplifier. Vdd = 3 V and Idd = 3 A (1 A in each branch of the circuit).

bulk MOSFET's, respectively, and that is similar for both device types. Taking into account the reduction of parasitic source/drain and intrinsic gate capacitances [16] found in SOI in addition to the lower value, it can be further demonstrated that a two-stage Miller opamp can be synthesized to achieve an 15 dB larger and a three times smaller in SOI than in bulk for similar area and identical bandwidth considerations (Fig. 4). Conversely, total area and can be divided by a factor up to 2­3 when all other specifications are kept constant. These theoretical predictions have been confirmed by the realization of a 100 dB, 3 AMiller opamp using a FD SOI CMOS process (Fig. 6). These results establish the potential of FD SOI CMOS to boost the speed ( ), gain ( ) and power ( ) performances of opamps well over those of bulk devices. Table I presents the performances of several operational amplifiers realized using FD SOI CMOS technology. It is most unlikely that high bandwidth, high dc gain, and low power consumption can all be achieved at the same time, but they have been demonstrated separately. Indeed, a dc gain of 115 dB, a bandwidth of 1.1 GHz, and a power consumption of 3.6 W have been demonstrated. Finally, it is worth mentioning that the use of an SOI instead of bulk allows for significant reduction of crosstalk in the chips [17]­[19]. Crosstalk immunity is enhanced if high-resistivity substrates are used [20]. This feature is particularly attractive for mixed-mode circuits. The excellent behavior of thin-film SOI MOSFET's at high temperature makes SOI technology highly suitable for high-temperature IC applications. Indeed, the major causes of failure in bulk CMOS logic at high temperature, i.e.,

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Fig. 6. Measured bode diagram of the Miller operational amplifier presented in the Fig. 5. Vdd = 3 V and Idd = 3 A (1 A in each branch of the circuit). Measurement was carried out six different temperatures (25, 50, 100, 150, 200, and 250 C). Cload = 60 pF.

Fig. 7. Measured bode diagram of the gain-boosting OTA presented in the previous figure. Measurement was carried out with a 10 pF load at 20 C and a 250 pF load at all other temperatures. The phase margin was measured at 20 C.

TABLE I PERFORMANCE OF SOI CMOS OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS (OTA), (3; ) 10 pF LOAD, (+) 60 pF LOAD, AND (}) 2 pF LOAD

excess power consumption and degradation of logic levels and noise margin, are much reduced in SOI circuits. Latchup is of course totally suppressed when SOI technology is used. SOI CMOS inverters exhibit full functionality and very little change in static characteristics at temperatures up to 320 C [21]. The performances of analog circuits depend on other device parameters than digital circuits. For instance, standby current consumption is fixed by the operating point of the circuit rather than by junction leakage. One important parameter is the output conductance of the transistors. Indeed, the dc voltage gain of an operational amplifier [operational transconductance amplifier (OTA)] is proportional to the product of the transconductance of the input transistors by the output impedance of the output transistors. As the temperature is increased, the transconductance of the input transistor decreases because of the reduction of carrier mobility with temperature. The output impedance (the inverse of the output conductance), on the other hand, increases as temperature is increased. Owing to this kind of compensation effect in the input transconductance-output impedance product, the resulting dc gain of the overall amplifier is expected to be relatively independent of temperature [22]. The measured characteristics of the device are consistent with what can be expected from theory: as the gate transconductance decreases and the output impedance increases, the dc gain of the SOI CMOS amplifier remains quite stable. It is also worth noting that the offset voltage of the amplifier remains between 0 and 2 mV for all temperatures between 20 C and 300 C.

In the case of analog circuits such as operational amplifiers, the increase of leakage current with temperature may result in the loss of the operating point, if bulk silicon technology is used. To illustrate this effect one can refer to Fig. 5, where the amplifier functions properly when a bias current of 1 A flows in each of the three branches of the circuit. In a bulk implementation, some (or most) of this bias current will flow to the substrate when the junction leakage increases with temperature. As a result the devices are no longer properly biased and the circuit no longer operates correctly (unless the bias current is increased to compensate for the leakage losses). If SOI technology is used the leakage current can only flow through the branches of the circuit, and the circuit operates without loss of the bias operating point (Fig. 6). Better performances can be obtained using circuit design techniques, such as the use of a cascode gain-boosting stage, which decreases the output conductance ( ) of the output stage and, therefore, increases the overall gain of the amplifier, and the zero-temperature coefficient (ZTC) concept, according to which there exists a bias point where the current is independent of temperature (the reduction of mobility is compensated by the reduction of threshold voltage). Fig. 7 presents the performances of such an amplifier. It is not a low-power device (25 mW), but it produces a high gain [115 dB--which corresponds to an amplification factor of 560 000--and a large bandwidth (100 MHz)]. The dc gain is still 50 dB at a temperature of 400 C [23]. Such amplifiers are suitable for A-to-D converters and switched capacitor circuits having to operate in a hightemperature environment. A switched-capacitor ladder filter realized in CMOS/SIMOX technology has been reported [24]. This seventh-order filter is capable of operating at 300 C under a supply voltage as high as 10 V. The operation of SOI A-to-D converters at a temperature of 350 C has been demonstrated as well [25]. V. MICROWAVE DEVICES Portable systems are, of course, a market of choice for low-voltage, low-power SOI circuits. Many of these systems

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TABLE II PERFORMANCES AND CHARACTERISTICS OF MICROWAVE n-CHANNEL SOI MOSFET's: (*) T-GATE TECHNOLOGY IS USED, (}) WITH METAL SHUNT ON THE GATE, AND (y) AT 3 GHz

will require telecommunication functions, which involves the need for microwave functions. Is it possible to realize these functions in SOI and to integrate them on the same chip as regular CMOS devices? It has been demonstrated that high-frequency n- and pchannel MOSFET's with transition frequencies above 10 GHz can be fabricated in SOI CMOS. In addition the use of highresistivity SOI substrates (5000 cm or higher) allows for the fabrication of passive elements, such as strip or slot lines with relatively low losses [26], [27], and planar inductors with a relatively good quality factor. Rectangular planar inductors with quality factors of 5, 8, and 11 have been obtained when realized on 20, 4000, and 10 000 cm substrates, respectively [28]. The highest performance SIMOX microwave MOSFET's were fabricated using a dedicated MOS process, called MICROX1), which uses nonstandard CMOS features, such as a metal (gold) gate and air-bridge metallization. In other approaches, standard CMOS SOI process was used. The latter devices are, therefore, compatible with lower-frequency (base band) analog and digital circuits fabricated using the same process. For correct microwave operation of a MOSFET the gate sheet resistivity must be low. If it is not the case, the gate behaves a delay line for the input signal and the part of the transistor which is farthest from the gate contact does not respond to high frequencies [29]. In addition, a low gate resistance is crucial for obtaining a low noise factor. Therefore, silicided gates (or metal-covered gates as in the case of MICROX) must be used. Table II presents the performances of SOI microwave transistors, and Fig. 8 presents the high-frequency performances of n-channel, FD devices having a gate oxide thickness of 32 nm. Nickel silicide was used to reduce the gate and S/D resistances. The subthreshold slope, the OFF current at V and V, the transconductance at V and the threshold voltage values are 71 mV/decade, 49 mS/mm, 1.25 nA per micron of channel width and 350 mV, respectively. The silicided gate and source/drain diffusions have a sheet resistance of 2.8 /square and 550 m, respectively. In order to obtain optimized microwave performances, the

1 MICROX

Fig. 8. Current gain (H21 ), the maximum available gain (MAG), and the unilateral gain (ULG) as a function of frequency in an n-channel SOI transistor having a length of 0.75 m and a width of 125 m at VDS = VGS = 1 V.

125- m gate width of the transistors is obtained using a comblike design of the polysilicon gate, which is composed of ten fingers having a length of 12.5 m each. Fig. 8 presents the current gain (H ), the maximum available gain (MAG) and the unilateral gain (ULG) as a function of frequency in an n-channel SOI transistor having a length of 0.75 m (L m). These parameters were measured through -parameter extraction under a supply voltage ( ) of 1 V. The unit-gain frequency (found when H dB) is equal to 13 GHz, and the maximum oscillation frequency (found when ULG 0 dB) is equal to 30 GHz. From all of these considerations, it appears that low-power SOI RF circuits can be used as a replacement to GaAs high-end chips in portable telecommunication systems, such as cellular phones. VI. CONCLUSION FD SOI MOSFET's offer near-ideal properties for analog applications. Their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and with a lower current consumption. The reduced body effect of FDSOI devices permits one to fabricate more efficient pass gates which makes it possible to fabricate DRAM's operating at a supply voltage lower than 1 V. The use of FDSOI CMOS makes it possible to fabricate analog circuits operating at high frequencies under low power supply. Finally, low-voltage, low-power SOI devices can operate at RF frequencies. All these features open the door to single-chip solutions for low-power telecommunication applications. In the field of high-temperature electronics, and as long as emerging technologies such as silicon carbide electronics are not available, SOI seems to be the only alternative for producing circuits operating up to 400 C. ACKNOWLEDGMENT The author wants to thank X. Baie, J. Chen, L. Deme^ s, u V. Dessard, J. P. Eggermont, L. Ferreira, D. Flandre, P.

is a registered trademark.

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Jean-Pierre Colinge (M'86­SM'89­F'96) was born in Brussels, Belgium, in 1956. He received the B.S. degree in philosophy, the M.S. degree in electrical engineering, and the Ph.D. degree in applied sciences from the Universit´ catholique e de Louvain, Louvain-la-Neuve, Belgium, in 1980, 1980, and 1984, respectively. From 1981 to 1985, he was with the Centre National d'Etudes des T´ l´ communications (CNET), ee Meylan, France, where he developed new siliconon-insulator (SOI) and 3-D integration technologies using laser recrystallization. From 1985 to 1988, he was with the HewlettPackard Laboratories, Palo Alto, CA, where he was involved in thin-film SOI CMOS and bulk bipolar technologies for high-speed digital applications. From 1988 to 1991, he was with the Interuniversitair Microelektronica Centrum (IMEC), Leuven, Belgium, where he was involved in SOI technology for VLSI and special device applications. From 1991 to 1997, he was Professor at the Universit´ catholique de Louvain, leading a research team in the field e of SOI technology. He is currently Professor at the University of California, Davis. He has published more than 170 scientific papers and three books in the field of SOI. Dr. Colinge has been on the committees of several conferences, including IEDM and SSDM, and was general chairman of the IEEE SOS/SOI Technology Conference in 1988.

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