Read Evaluation of HD4004 Photosensitive Polyimide for Semiconductor Applications text version

IBM Worldwide Packaging and Test

Evaluation of HD4004 Photosensitive Polyimide for Semiconductor Applications

T.H.Daubenspeck, A.L.Petrosky, W.Sauter, K.A.Ostrowski IBM Microelectronics

May 5, 2004

Symposium on Polymers

© 2004 IBM Corporation

Worldwide Packaging and Test

Agenda Introduction Background HD4004 Objective Packaging Considerations / CPI Photolithographic Data XPS Data Adhesion Data Packaging Qualification Status Summary

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Polyimide in Semiconductor Manufacturing

PI comprises final wafer "via" level for Pkg Interconnect

4-6 um typical cured thickness Damage protection layer during wafer finish and beyond Stress buffer for chip:package interface Planarization layer, interface for packaging Required Properties Adhesion integrity to wafer and package level films Mechanical, chemical, and thermal stability (>350°C Tg for C4) Small feature patterning capability for Wirebond (WB) Integration with processes and packaging materials Low cost

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HD4004 as "Common" Material

HD4004

High Tg (>360°C) PSPI Photosensitive Minimizes capital cost Minimizes C4 cycle time Improves C4 lithographic capability

OLD PROCESS NEW PROCESS Fab

C4 nonWB Common C4 and WB photosensitive photosensitive

photosensitive process

Previously - 200mm/300mm production

Photosensitive Low Tg Polyimide for WB Non-Photosensitive material used for C4

C4 wafer finish and assembly WB wafer finish and assembly

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300mm HD4004 Qualification Strategy

"T0" - Feasibility Checkpoint

­ Material performance ­ Preliminary packaging evaluation

"T1" - Technology / Manufacturability Checkpoint

­ Reliability qualification for chip and package ­ Costly, resource intensive, and time consuming

***Must cover all products and technologies*** Objective: Implement HD4004 upon completion of all T1 items

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Package Types

Ceramic

FC-PBGA HP

polyimide

FC-PBGA

EPBGA WB

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Representative Ceramic Package ­ Materials and CTE

Epoxy Underfill CTE= 25-30 x 10 -6 /C

97/3 Pb/Sn C-4 Solder Balls

Polyimide / PSPI

CTE= 29 x 10 -6 /C

Silicon Chip

CTE= 35 x 10 -6 /C

Aluminum Heatsink / Cap

CTE= 2.6 x 10 -6 /C Alumina substrate CTE= 6.5 x 10 -6 /C

CTE= 23 x 10 -6 /C

Alumina Substrate Module

Epoxy/Glass Board CTE= 16 - 20 x 10 -6 /C (Can join substrate to board by LGA, BGA, CGA)

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IBM Qualification Methodology ­ Introduction of CPI

Historical Model ­ SiO2 BEOL w/ industry standard Pkg `New' CPI Model ­ low-k BEOL w/ industry standard Pkg

Chip Technology Development Chip T1

`New' CPI Model

'CPI' Technology T1

Packaging Technology Development

Packaging T1

Low-k Technologies

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Expansion of CPI work

130nm technology

90nm technology

Wirebond

C

Wirebond

C4

HPBGA EPBGA FCPBGA

HPBGA

EPBGA

FCPBGA

Ceramic

Hyper BGA

High Pb

Pb reduced

Thick

High Pb

Pb reduced

Pb free

4 on 8 Pit

Small Chip Large Chip Thick Laminate

Thin Laminate

Sm

Underfill A

Underfill B

BLM 1on 4 9 2004 Symposium on Polymers

BLM 8 Pitch 2

3 on 6 Pitch

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Technology Qualification Variables for CPI

Wafer Level - 200mm/300mm

BEOL dielectric final level wiring option final pad level final via level - type, materials C4 BLM C4 Size/Pitch FTEOS vs Low K CVD 2x vs 4x vs 6x fatwire Multiple via, pad, metalization options WB vs C4 - LV, FV or DV via designs Polyimide ­ HD4K or PI5878 Pb Free, eutectic, or high melt solder Standard vs advanced options 4 on 9, 4 on 8, 4 on 7, 3 on 6

Chip and Package Level

Chip size / shape Pkg Type - square, rectangular, ~8-20 mm - WB: HPBGA, EPBGA + others - C4: ceramic - C4: "organic" -- FCPBGA + HyperBGA internal and external, Pb-Reduced, Pb'ed material, #build-up layers, core thickness, etc Underfill, heat sink, stiffener, Temp, etc

Pkg Assembly Substrate or laminate type materials&processes

IBM Confidential

WWP&T Integration Team / T. Daubenspeck

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CPI and Packaging Tests

CPI Test Structures - C4 "stitches" - perimeter rings - via chains - metal serpentines - strain gauge

Wiring under Bondpad

Serpentine Structures

Via Chain ­ Cross Section

Typical CPI Packaging Stresses for T1

Strain gauge

- Deep Thermal Cycle (-55 to 125°C;1000 cycles) - TH&B (85°C, 85%RH, 7.12psia; 1000 hrs) - HTS (150°C; 1000hrs) - HAST (130°C, 85%RH, 33.3psia; 96 hrs) Evaluated by E-test and Sonoscan

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PSPI Lithographic Performance Criteria

C4 Requirements

­ Smooth, tapered (<70 deg) PI via slope for BLM coverage ­ Typical via size range; ~47- 70 um diameter ·smaller openings ~20 um for support structures e.g. fusebays ·+/- 1-2 um 3sig image size tolerance ­ Mid-term 3on6 C4 pitch objective ·requires improved via size control, reduced tolerance ·smaller C4 w/ larger via size for performance ·BLM must always cover via opening

Wirebond Requirements

­ Minimum "web" structure width down to 4 um

PSPI Web (um and % ) 25

Percentage of PSPI Web as function of WB Pitch

Assuming constant 8 um PSPI web

consistent w/"roadmap"

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15 PSPI W eb 10 %-age of web

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Trend/Time

0 30 35 40 2005 45 50 55 60 2003 65 W irebond Pitch Production Year

2004

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Line Width and Space Structures

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8

Line Wi dth 6 4

2

1

1

13

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Space

6

8

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Polyimide Web Width

8 um

6 um

4 um

2 um

1 um

6 Wafers

Measurement 2 Measurement 1

2 Center die / wfr 2 Mid Radius die / wfr 2 Edge die / wfr

© 2004 IBM Corporation

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Polyimide Web Width Results

Average Measured Line Width for 1 - 10um

12.00

10.00 Measured Width (um)

8.00

6.00

4.00

2.00

0.00 Mid-Radius Mid-Radius Mid-Radius Mid-Radius Mid-Radius Mid-Radius Total Total Total Total Total Edge Edge Edge Edge Edge Center Center Center Center Center Center Edge Total

1 um

2 um

4 um

6 um

8 um

10 um

I-Line exposure, 225 mj (ASML) std develop w/ GBL/NBA formulation Linewidths slightly decrease from wafer center to edge

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3x StDev

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Wafer Edge to Center Variation

6 5 4 3 2 1 0

6 5 4 3 2 1 0

6 5 4 3 2 1 0

1 um width

2 um width

4 um width

12 10 8 6 4 2 0

12 10 8 6 4 2 0

12 10 8 6 4 2 0

6 um width

8 um width

10 um width

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Design vs. Actual Width for PSPI Structures

Average Measured Average Measured Line Width (um) (um)

1 2

Measured Line Width

1 0

Designed Line Width

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6 4 2 0

0 0 2 2

Delta between Measured and Designed Line Width y = 2.1 - 0.56Ln(x)

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6 6

8 8

1 0

1 2

1 4

Design Design Line Width (um) Line Width (um)

For Small PSPI Structures, the Actual Line Width is larger than Designed Line Width Delta is a Function of Designed PSPI Width and can be approximated

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Minimum Polyimide Opening

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12

10

8

6

4

2

Opening Dimension

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Design vs. Actual PSPI Hole Dimensions

Average Measured Via Width (6-14 um )

1 4.00 1 2.00

Via Width (um)

1 0.00 8.00 6.00 4.00 2.00 0.00

6 um

8 um

10 um

12 um

14 um

3x StDev

Measurements are taken at bottom of vias

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XPS Results: PMDA-ODA vs HD4004

Sample PMDA-ODA Post- Cure HD4K Post-Cure PMDA-ODA Finished Wafer (after C4 Processing) HD4K Finished Wafer (after C4 Processing) C 75.3 79.5 73.2 69.0 N 7.0 5.1 8.0 5.7 O 17.0 14.3 17.9 20.7 F <0.1 <0.1 <0.1 <0.1 Si 0.8 1.0 0.6 2.8 Sn <0.1 <0.1 0.1 1.6 Pb <0.1 <0.1 0.2 0.2

HD4K final surface - slightly higher O:C, slightly lower N vs PMDA-ODA As-cured HD4K surfaces have slightly lower O:C , N content No detectable F for any surface (courtesy of E.Adams IBM BTV)

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FCPBGA PI:Underfill Adhesion Data

Polyimide

Pull chip upward and look at failure mechanism

Cohesive failure (Underfill)

Silicon Chip 97/3 Pb/Sn C-4 Solder Balls

Epoxy Underfill

9 commercially available underfills were evaluated ­ T0 testing only (no stress) HD4K & PMDA-ODA adhesive interface to underfill is robust for all 9 materials All fails were cohesive - within underfill layer (courtesy of M.Paquet, IBM Bromont)

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HD4K Packaging Data Summary to Date

200mm (BTV)

D'Back Wirebond Sahara ceramic/C4 T0 2Q02 3Q02 - basic feasibility - RCE, DTC/HAST ­ 0 stress fails

300mm 130nm FTEOS BEOL

Admiral WB T1 Ceramic HyperBGA FCPBGA T0 3/04 1/04 4/04 5/28 - T1 complete ­ E&HPBGA - UF DTC/HAST MG - 0 fails (Sahara) 4/04 - THB/HAST/DTC - 0 fails (GRH) - UF 1000 cyc DTC MG - 0 fails - UF chkpt ­ 6-way split

Basic Material Testing

Peel test Chip Pull 4/04 1Q04 - strengths equiv to PI5878 - cohesive for all UF matls - ceramic+HypBGA ­ 0 fails T0 UF Eval (FCPBGA) 4/04

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Packaging Qualification Matrix / Status

Package Qual

Wirebond EPBGA HPBGA Wirebond EPBGA HPBGA Ceramic SCM&MCM Ceramic SCM&MCM HyperBGA

Tech

130nm

BEOL

FTEOS

B&A Location

Internal External Internal External Internal Internal Internal

B&A Condition

PbReduced laminate

I/O Pitch

50-55 um 8 um web 50-55 um 8 um web 4 on 8 mil 4 on 8 mil 4 on 8 mil

BLM

N/A

Status

T1 1Q04 Implementation 1Q04 (complete) T1 1Q04 Implementation 1Q04 (complete) T1 chkpt 2Q04 Tgt Implementation 3Q04 T1 chkpt 2Q04 Tgt Implementation 3Q04 T1 chkpt 2Q04 Tgt Implementation 3Q04 T1 chkpt 3Q04 Tgt Implementation 4Q04 T1 chkpt 3Q04 Tgt Implementation 4Q04 T1 chkpt 4Q04 Tgt Implementation 4Q04

90 nm

LowK

PbReduced laminate

N/A

130 nm 90 nm 130 nm

FTEOS LowK FTEOS

PbReduced laminate; Leaded; PbFree C4 PbReduced laminate; Leaded; PbFree C4 PbReduced laminate; Leaded, PbFree C4 PbReduced laminate; Leaded; PbFree C4 PbReduced laminate; Leaded; PbFree C4 PbReduced laminate; Leaded C4

std std std

FCPBGA Thin/thick FCPBGA Thin/thick All Existing Customers

130 nm

FTEOS

Internal External Internal External Internal External

4 on 8 mil

std adv std adv std

90 nm 130 nm

LowK FTEOS

4 on 8 mil 4 on 8 mil

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Summary / Conclusions

IBM Implementation of HD4004 Depends upon

T0 Feasibility and T1 Qualification, to include CPI / Packaging Evaluation

HD4004 T0 Feasibility Testing at IBM

Manufacturing-compatible Photo imaging performance demonstrated ­ major improvement for C4 Surface chemistry similar to PMDA-ODA Initial adhesion integrity to critical packaging interfaces is acceptable

HD4004 is in T1 Package/CPI Qualification Phase

Wirebond portion of T1 qualification is complete ­ HD4K Implemented Qual schedule to close by YE04 for Internal Products Preliminary package data indicate high probability of success

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Acknowledgments

W. Landers E. Adams M. Paquet R. Fournier B. Guthrie T. Lombardi K. Larsen Y. Wu

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Information

Evaluation of HD4004 Photosensitive Polyimide for Semiconductor Applications

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