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E.E. 451.3 ENEL 489

VLSI/Integrated Circuit Design

Verilog USER GUIDE:

Comprehensive Example

Dr. R.J. Bolton

Department of Electrical Engineering University of Saskatchewan 57 Campus Drive Saskatoon, Saskatchewan S7N 5A9

Andrew R. Kostiuk,

TRLabs University of Regina 108-2 Research Drive Regina, Saskatchewan

E.E. 451.3/ENEL 489 Verilog USER GUIDE: Comprehensive Example

Introduction

The following example is intended to be a comprehensive example to introduce the novice Verilog designer to the structure of Verilog design. To do this an 8-bit serial to parallel converter with parity will be designed. The implementation of the circuit follows that of the VHDL version presented in the VHDL USER GUIDE Comprehensive example. All items in bold lowercase in the listings to follow are either Verilog reserved keywords or user defined text macros.

Specification

Consider the example of a serial input bit stream (rxd) with a clock (clk). The input stream is to be formed into a byte (r) and a parity bit (pb) generated. The byte should be output in parallel (r(0), r(1), r(2), .., r(7)). A flag (char_available) should be set when an entire character (i.e., the r byte) has been received and it should be reset when the byte and parity are read (or the reset signal is asserted). From this description, we can already write the Verilog file preamble without worrying yet about what is inside the circuit. Lets call the circuit "s_to_p_with_p".

//**************************************************** // Design of Serial to Parallel Circuit with Parity //---------------------------------------------------//---------------------------------------------------// Designed by: Top Level Designer // Date: February 16, 1998 //---------------------------------------------------//**************************************************** // Since we have a byte, lets declare a text macro //---------------------------------------------------`define BYTE [7:0] //**************************************************** // Top Level Interface //----------------------------------------------------

Listing 1. Verilog code of Module (s_to_p_with_p).

Design

Now what is inside? Well, we will need an eight bit shift register to do the serialto-parallel conversion, call it "eight_shift". A parity generator, call it "parity_gen". A four bit counter to count the number of bits clocked in and a common reset. Call the counter "counter" and we get a circuit like Figure 1.

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E.E. 451.3/ENEL 489 Verilog USER GUIDE: Comprehensive Example

parity_g e n d(0) d(1) d(2) d(3) d(4) d(5) d(6) d(7)

parity

pb

8 inpu t clock q(0) q(1) q(2) q(3) q(4) q(5) q(6) q(7)

r

rxd clk

eight_s hift

reset

clock reset q0 q1

co unter q2 q3 char_ av ailable

Figure 1. Schematic Diagram of Module (s_to_p_with_p). Now we can write the Verilog architectural description.

//**************************************************** // s_to_p_with_p //---------------------------------------------------module s_to_p_with_p (rxd, clk, reset, r, pb, char_available); input rxd, clk, reset; output `BYTE r; output pb, char_available; eight_shift g1 (rxd, clk, r); parity_gen g2 (r, pb); counter g3 (reset, clk, , , , char_available); endmodule

Listing 2. Verilog code - Module (s_to_p_with_p). Note that the associated ports on the instances are matched up by order and cannot be quickly identified (since we have yet to see the sub-module definitions). For a large number of connections this can be a problem (since the order has to be exact). Note also that q0, q1, and q2 of instance "count" are left unconnected. Eight Bit Shift Register Now lets do eight_shift (see Figure 2). Assume that a shift register (shift) exists in some form appropriate to the fabrication technology we plan to use. In this case, it is assumed that a behavioral description will be written for this sub-module.

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E.E. 451.3/ENEL 489 Verilog USER GUIDE: Comprehensive Example

q(0) input input q shift clock clock

q(1) input q shift clock

q(2) input q shift clock ... ... ...

q(5) input q shift clock

q(6) input q shift clock

q(7) input q shift clock

Figure 2. Eight Bit Shift Register (eight_shift). The Verilog code for the Eight Bit Shift Register is shown below.

//****************************************************** // Eight Bit Shift Register //-----------------------------------------------------module eight_shift (in, clock, q); input in, clock; output `BYTE q; shift shift shift shift shift shift shift shift endmodule g4 (in, clock, q[0]); g5 (q[0], clock, q[1]); g6 (q[1], clock, q[2]); g7 (q[2], clock, q[3]); g8 (q[3], clock, q[4]); g9 (q[4], clock, q[5]); g10 (q[5], clock, q[6]); g11 (q[6], clock, q[7]);

Listing 3. Verilog code - Eight Bit Shift Register (eight_shift). Parity Generator A parity generator can be constructed as a network of xor gates as shown in Figure 3. Assume there is a xor gate called "xor" in the PRIMITIVEs for Verilog. See Appendix A for a list of Verilog PRIMITIVEs that should be defined in any Verilog compiler that you use.

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E.E. 451.3/ENEL 489 Verilog USER GUIDE: Comprehensive Example

d(0) d(1) d(2) d(3)

xor xor xor xor pa rity

d(4) d(5) d(6) d(7)

xor xor xor

Figure 3. Parity Generator (parity_gen). The Verilog code for the Parity Generator is shown below.

//***************************************************** // Parity Generator //----------------------------------------------------module parity_gen (d, parity); input `BYTE d; output parity; `define NIBBLE [0:3] `define DUAL [0:1] wire `NIBBLE inner; wire `DUAL inner2; xor xor xor xor xor xor xor endmodule g12 g13 g14 g15 g16 g17 g18 (inner[0], d[0], d[1]); (inner[1], d[2], d[3]); (inner[2], d[4], d[5]); (inner[3], d[6], d[7]); (inner2[0], inner[0], inner[1]); (inner2[1], inner[2], inner[3]); (parity, inner2[0], inner2[1]);

Listing 4. Verilog code - Parity Generator (parity_gen) Four Bit Ripple Counter Finally the four bit counter. Assume that a resettable D-type flip-flop (rdff) exists in some form appropriate to the fabrication technology we plan to use. In this case, it is assumed that a behavioral description will be written for this sub-module. If we keep it simple and do a ripple counter, we get Figure 4.

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E.E. 451.3/ENEL 489 Verilog USER GUIDE: Comprehensive Example

reset d ck reset rdff clock qb q q0 ck d reset rdff qb q q1 ck d reset rdff qb q q2 ck d reset rdff qb q q3

Figure 4. Four Bit Ripple Counter (counter). The Verilog code for the Four Bit Ripple Counter is shown below.

//***************************************************** // Four Bit Ripple Counter //----------------------------------------------------module counter (reset, clock, q0, q1, q2, q3); input reset, clock; output q0, q1, q2, q3; wire i0, i1, i2, i3; rdff rdff rdff rdff endmodule g19 g20 g21 g22 (i0, (i1, (i2, (i3, clock, reset, q0, i0); i0, reset, q1, i1); i1, reset, q2, i2); i2, reset, q3, i3);

Listing 5. Verilog code - Four Bit Ripple Counter (counter). Shift Register Since the shift register (shift) does not exist as a PRIMITIVE, the behavioral Verliog code for a shift register (shift) follows. Note the use of the always keyword (designating a concurrent process) and the use of the "@" trigger designation.

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E.E. 451.3/ENEL 489 Verilog USER GUIDE: Comprehensive Example

//***************************************************** // Shift Register //----------------------------------------------------// // The shift module does not exist (as a primitive). // Use a behavioral description for it. // module shift (d, ck, q); input d, ck; output q; reg q; always @(posedge ck) q = d; endmodule

Listing 6. Verilog code ­ Behavioral Shift Register (shift). Resettable D-type Flip-Flop Since the resettable D-type flip-flop (rdff) does not exist as a PRIMITIVE, the behavioral Verliog code for a resettable D-type flip-flop (rdff) follows. Note the use of the always keyword (designating a concurrent process) and the use of the "@" trigger designation.

//***************************************************** // Resettable D Flip-Flop //----------------------------------------------------// // The rdff module does not exist (as a primitive). // Use a behavioral description for it. // module rdff (d, ck, reset, q, qb); input d, ck, reset; output q, qb; reg q, qb; always @(posedge reset or posedge ck) if (reset) begin q = 1'b0; qb = 1'b1; end else begin q = d; qb = ~q; end endmodule

Listing 7. Verilog code ­ Behavioral Resettable D Flip-Flop (rdff).

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E.E. 451.3/ENEL 489 Verilog USER GUIDE: Comprehensive Example

Stimulus

In order to determine that the circuit works as intended, a behavioral test-bench for the circuit is written (in Verilog). For this a module is written (stimulus) that has no ports and only one instantiated sub-module, namely s_to_p_with_p. Since the submodule is driven with a behavioral description, reg variables are used (they are not driven and they hold their value). Note the use of multiple initial and always statements (i.e., one per behavioral signal).

//***************************************************** // Test-Bench Stimulus //----------------------------------------------------// // Verilog allows us to specify the stimulus for the. // circuit. VHDL does as well (except in our compiler). // module stimulus; reg serial_in; reg clock; reg reset; wire `BYTE rdata; wire parity; wire done; // Circuit Instantiation: // // The first form of making the connections (by port list order). // Signals are matched up by the port order. Signals must be in // exact order. An open signal has to be included (i.e., reset, , parity). // s_to_p_with_p s_to_p (serial_in, clock, reset, rdata, parity, done); // // The second form of making the connections (by port list name). // Signals are matched up using the port name. Signals can be in // any order. An open signal has to be left out. // //s_to_p_with_p s_to_p (.rxd(serial_in), // .clk(clock), // .reset(reset), // .r(rdata), // .pb(parity), // .char_available(done)); // // Serial_in details. Initialize to 1 and after 160 time units // set to 0 for another 160 time units. Note that the $finish // stops our simulation (i.e., DON'T FORGET TO USE IT!). //

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E.E. 451.3/ENEL 489 Verilog USER GUIDE: Comprehensive Example

initial begin serial_in = 1'b1; #160 serial_in = 1'b0; #160 $finish; end // // Clock details. Initialize to 0 and clock every 10 time units. // initial clock = 1'b0; always #10 clock = ~clock; // // Reset details. Initialize to 0 and after 1 time unit // pulse for 5 time units. // initial begin reset = 1'b0; #1 reset = 1'b1; #5 reset = 1'b0; end // // // // // // SILOS 3 Simulator Monitor details. Specify the data you want to output to screen. Output data is in "tabular" form. Student edition has built-in limits.

//initial // $monitor($time, " Output: %b %b %d %b %b %b", // serial_in, clock, reset, rdata, parity, done); // // // // // // Veriwell 2 Simulator Monitor details. Specify the data you want to save to file. Save is in "waveform" form. Only 10 signals saved. Student edition has built-in limits.

initial $vw_dumpvars(0, serial_in, clock, reset, rdata, parity, done); endmodule

Listing 8. Verilog code ­ Test-Bench Stimulus (stimulus).

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E.E. 451.3/ENEL 489 Verilog USER GUIDE: Comprehensive Example

Summary

Note that while the completed Verilog description may appear to be somewhat sparse it is basically self-documenting and, once written, easy to change. Some things to note when writing Verilog code: ·case does matter. Use lowercase for reserved keywords ·if you plan on using buses, use a text macro definition ·use comments (a line starting with //) liberally ·make sure your spelling is correct ·don't forget the semicolons at the end of most lines (not endmodule) ·port types must match (i.e., INPUT and OUTPUT, etc.) Please note that the example shown above may not be usable with the particular library of PRIMITIVEs that you are using. In this case changes may have to be made to the Verilog code, most notably in the names of the lower-level leaf cells. Good luck!

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E.E. 451.3/ENEL 489 Verilog USER GUIDE: Comprehensive Example

Appendix A

Verilog Primitives

Primitives in Verilog are simple functions implemented in a behavioral description that is specified by using a truth table. There are 26 Verilog primitives. Primitive

and nand or nor xor xnor buf bufif0 bufif1 not notif0 notif1 pulldown pullup nmos pmos cmos rnmos rpmos rcmos tran tranif0 tranif1 rtran rtranif0 rtranif1

Description

and nand or nor xor xnor buffer input buffer input if 0, otherwise hi-z buffer input if 1, otherwise hi-z not input not input if 0, otherwise hi-z not input if 1, otherwise hi-z Pulldown to supply 0 Pullup to supply 1 Unidirectional NMOS transistor Unidirectional PMOS transistor Unidirectional CMOS transistor Unidirectional NMOS transistor (resistive) Unidirectional PMOS transistor (resistive) Unidirectional CMOS transistor (resistive) Bi-directional pass gate Bi-directional pass (if 0) gate Bi-directional pass (if 1) gate Bi-directional pass gate (resistive) Bi-directional pass (if 0) gate (resistive) Bi-directional pass (if 1) gate (resistive)

Outputs

output output output output output output output output output output output output output output output output output output output output inout, inout inout, inout inout, inout inout, inout inout, inout inout, inout

Inputs

in1, .., inN in1, .., inN in1, .., inN in1, .., inN in1, .., inN in1, .., inN input input, control input, control input input, control input, control none none input, gate input, gate input, ngate, pgate input, gate input, gate input, ngate, pgate none control control none control control

Note: Primitive modules have the output port(s) given first. Watch out for this since your normal convention may to be to list inputs first. Note: The generic logic gates can be multiple input. The first port is the output while the following port(s) are inputs. Note: The resistive modules decrease the "strength" of the signal when operating. Note: The transistor modules are unidirectional (source to drain). Note: The tran and rtran modules are bi-directional devices.

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