Read lab4.pdf text version

Laboratory Four

Combinational Logic Design: 7-Segment Displays

Basic Concepts

1. A block diagram is a picture which quickly defines the inputs and outputs of a logic circuit design problem. 2. The relationships between inputs and outputs of a block diagram are established by truth tables. We are going to develop a truth table and design a circuit for a sevensegment display. Truth tables for such problems can contain 1s, 0s, and even don't cares (Xs). 3. Optimized circuit design equations may be formulated from truth tables through the use of Karnaugh Maps. 4. Review these video tutorials to see how to set up a new project, enter a design and implement your design. Note: This lab has a 10 point prelab.

Task One: Example minterms and K-maps

1. (Pre) Plot the function F1=m(0,2,4,6) on the K-map and read the map to simply F1.

2. (Pre) Simplify F2 already plotted on the map at right

3. (Pre) Plot the function F3=m(4,5,10,11,12,13,14,15) on the K-map and read the map to simply F3.

4. (Pre) Simplify F4 already plotted on the map at right

5. (Pre) Plot the function F3=m(1,7,9) + X(5,11,13,15) where X = don't care, on the K-map and read the map to simply F5.

Task Two: Seven-Segment Display Decoder

1. A 7-segment decoder circuit is to be designed to light up the display on the Digilent board, shown in Figure 2.3 of the textbook. The four inputs represent the 4-bit binary numbers between 0 and 9, (often called binary-coded decimal = BCD) and the seven outputs are the anode drivers for a figure 8 shaped display, called a through g, shown at right. (Click the link for an animated demonstration.) Draw the block diagram for this circuit (in the textbook), in your lab notebook. 2. Your instructor will have you draw one column of the truth table for the 7-segment decoder shown in Table 2.6 of the textbook for one of the outputs a through g. Now, list the minterms in your column as m(). Notice that there are also some don't cares Xs in the truth table; write these down also as X(). 3. Your instructor will now ask your group to draw a K-map for your chosen seven-segment decoder output in your lab notebook, filling in the maps with 1s, 0s, and Xs. Use W,X,Y,Z labels instead of the usual A,B,C,D. (A different K-map should be given to each group.) 4. [Discussion] Read your K-map and record a SOP expression for one of the seven outputs, using the don't cares to help simplify your equations. Your lab instructor will have students share answers between groups and discuss if the various derived solutions are correct. 5. Use VHDL to directly input all the design equations for your 7-segment decoder into Xilinx. 6. Proceed to Task Three where you will implement your design into hardware.

Task Three: Implementing the Decoder

After creating your 7-segment decoder, you are now ready to implement this design into the XCR3064XL complex PLD chip residing on the Digilent XCRP board. Review these video tutorials to see how to set up a new project, enter a design and implement your design. 1. Since we are using an evaluation board, pins from the CPLD are hard wired to I/O components like switches, LEDs, buttons etc. To use these, terminals in our design have to be mapped to specific pins on the CPLD. This is done using user constraints file (*.ucf): a. In Project Navigator select design panel and Implementation radio button in the view pane. b. In Project Navigator, select ProjectNew source to open the New Source Wizard. Select Implementation Constraints File and enter a file name. c. Click Next, then Finish. A blank document opens in the text editor. d. Go to the desktop on your lab computer and open the "generic_ucf.txt" text file. Copy the contents of this file and paste into the empty text editor. Do the necessary changes according to your design and save the file. For example : If W is a switch in your design, then replace "sw1" with "W". Any unused lines should either be deleted or commented out by placing a # sign at the beginning. 2. In the Hierarchy panel, select the top level design file. In the Processes pane, expand Implement DesignConfigure Target Device and double-click Manage Configuration Project (iMPACT). 3. While this is running, connect the programming and the power cable to the board. 4. Finally the iMPACT window opens. Double click on Boundary scan. 5. Now on the white workspace, right-click and select Add Xilinx Device. 6. In the Assign New configuration File window, select the *.jed file and click Open. 7. to download the program, right-click on the xcr3064xl device and select Program. Click OK on the Device Programming Properties window. You should see "Programming Succeeded" if this operation was successful. 8. Enter some numbers on the switches and see if your design is functioning properly.

Task Four: A 2-Digit Seconds Counter

Your instructor will now show you how to write some code for a 2-digit seconds counter which will count between 00 to 59 using the two 7-segment displays on the Digilent board. You will first make a Xilinx library symbol for your 7-segment decoder. Then you will download the VHDL code for the seconds counter, and make a second symbol. Finally, you will connect the counter and decoder together on the schematic editor, and upload the results into the Digilent board. 1. With the project for task 3 still running, select your 7-segment design file in the Hierarchy panel. Under the Processes panel expand Design Utilities, and double click Create Schematic Symbol. 2. Now you will add the seconds counter to your project. Download the seconds counter code (also in the network-folder) and save it as "SecClk.vhd" in your current project directory. Click on Project -> Add Copy of Source, open SecClk.vhd. Then click Ok. Review the code with your instructor. Finally create a symbol for this code, as explained in step 1. 3. Create a new Schematic Source, like you did in the previous labs. In the Schematic window click on Symbol Tab. You can see that there is a symbol(chip) added to the Symbols pane with the name of "seg7dec" (your 7 segment design file name) and "SecClk". These are the symbols you will be using shortly. 4. Use schematic capture to connect the seconds counter to the 7-segment decoder, such as illustrated below. Save your work. 5. Open the constraint file (*.ucf) and modify the contents to reflect the changes in your design. 6. To download the design into the PLD, follow the steps used in earlier task 3. 7. After successfully programming the board, you should see the 7-segment displays on the board light up. 8. Turn the screw on the blue pot which controls MCLK all the way clockwise to see how both displays light up. Notice that only one display is lit at a time. 9. Finally, calibrate your counter, by comparing its count value in a 30 second period as measured by your watch. [Alternatively, skip to step 10 if you have an iPhone.] Turn the potentiometer on your Digilent board until your counter counts 30 seconds in a 30 second period 10. Your lab instructor will now show you how you can use the iPhone iMSO to view the 4kHz, 2kHz, 1kHz and 1 Hz outputs of the SecClk block. Turn on the purple, yellow, blue and orange digital inputs on the iMSO and connect those same colored leads to the 4kHz, 2kHz, 1kHz and 1 Hz SecClk outputs. Pause the display and arrange the waveforms so they look like the display shown below. Next, enable the cursor display and move them across one period of the blue (1 kHz) output. Unpause the display and turn the potentiometer on your Digilent board until the frequency reading of the blue channel (on the bottom) says 1.00 kHz. SecClk is now calibrated and the seconds output should now be accurate. (Step 9 verifies!)

Information

4 pages

Report File (DMCA)

Our content is added by our users. We aim to remove reported files within 1 working day. Please use this link to notify us:

Report this file as copyright or inappropriate

539708


You might also be interested in

BETA