Read Microsoft PowerPoint - Ex_02_LED_7seg_keypad.ppt [ ] text version

7-Segment, LED

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FPGA 7-segment, LED ARM 7-segment, LED ARM keypad

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· · ·

1. FPGA 7segment LED IP . 2. APB slave 7segment LED IP ARM . 3. Keypad 7segment IP IP .

IP FPGA APB Keypad

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Chapter 1. FPGA 1 7-Segment, LED

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LED 7-Segment LED 7-Segment LED 7-Segment 7 Segment LED 7-Segment ModelSim Simulator EasySoC

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LED 7-Segment

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LED 7-Segment (1)

LED light emitting diode luminescent diode . , ( 700nm), ( 550nm). , , . , , . .

RED

1.8V 2.0V 3.0V 3.4V 3.4V

2.3V 2.8V 3.6V 3.8V 4.0V

() 20 mA 20 mA 20 mA 20 mA 20 mA

() 50 mA 50 mA 50 mA 50 mA 50 mA

Real Yellow Real Green Real Blue White h

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LED 7-Segment (2)

7-Segment A~G DP 8 LED . 7-segment FND(Flexible Numeric Display-) . , . LED . LED . 7-Segment A~F . 7Segment 0~9, A~F 16 BCD 16 .

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LED 7-Segment (3)

7-Segment LED Anode Cathode . (1) A(Anode) A(A d ) COM VCC "0" . ) COM VCC, A "0" 7-Segment A Segment .

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LED 7-Segment (4)

(2) K(Cathode) COM GND "1" . ) COM VCC B "1" VCC, 7-Segment B Segment .

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LED 7-Segment (5)

7-Segment 0~9, DOT . EasySoC Cathode 7-Segment Cathode C th d .

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LED 7-Segment (1)

EasySoC FPGA LED 8 LED(D1 ~ D8) ALTERA Cyclone-II (EP2C50F672C8) FPGA I/O '1' (HIGH) LED '0' (LOW) LED 1 0 .

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LED 7-Segment (2)

12 341 .

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LED 7-Segment

·

HDL EasySoC FPGA Quartus-II Modelsim LED 7-segment .

(Quartus-II) (Verilog HDL) & Easy-SoC

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(1)

1) > > Altera > Quartus II 7.1 > Quartus II 7.1 Web Edition 2) Quartus II File > New Project Wizard .

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(2)

3) Project Wizard Project (C:\work\easy_clock) Project Name (easy_clock) Top-level design entity (easy_clock) . "Next" "Finish" .

| 6.7 |

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(3)

4) . "(Y)" . .

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(4)

5) Finish Next Design . "Next" Next .

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(5)

6) Family Cyclone II , Available device EP2C50F672C8 "Next" .

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(6)

7) Quartus II .

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(1)

clock : - 25MHz 1 . - 1 , , seven_seg . seven_seg : - clock , , 7-SEG .

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(2)

File > New ( Ctrl + N) New 7-Segment HDL 7S t VHDL File Verilog HDL File OK .

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(3)

Quartus II Editor HDL .

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(4)

HDL module . "Add file to current project"(default) .

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(5)

"Project Navigator" "File" . .

rtl / bin2seg.v rtl / clock.v rtl / easy_clock.v l l k rtl/seven_seg.v

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-

4 .

easy_clock.v clock.v clock v seven_seg.v bin2seg.v

.

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- (1)

easy_clock.v

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- (2)

clock.v ­ (1)

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- (3)

clock.v ­ (2)

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- (4)

seven_seg.v ­ 7 Segment (1)

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- (5)

seven_seg.v ­ 7 Segment (2)

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- (6)

bin2seg.v ­ 7 Segment

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(1)

Top-Level Entity (easy_clock.v) Project > Set as Top-Level Entity(Ctrl+Shift+J) Top level .

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(2)

processing > Start Compilation (Ctrl + L) Compile . Full Compilation was successful .

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ModelSim Simulator (1)

. modelsim 7-Segment, LED . > > Altera > ModelSim-Altera 6.1f (Quartus II 7.1) > ModelSim-Altera 6.1f . ( .)

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ModelSim Simulator (2)

. File > Change Directory

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ModelSim Simulator (3)

. File > New > Project

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ModelSim Simulator (4)

Add Existing File . Browse.. .

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ModelSim Simulator (5)

"Add file to Project" . Reference from current location , Copy to project directory . OK "Add items to the Project Add Project" close .

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ModelSim Simulator (6)

. stimulus , .

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ModelSim Simulator (7)

, (compile all) (simulate) ( i l t ) . "compile all" . Status . Transcript .

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ModelSim Simulator (8)

simulate . top easy_clock OK .

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ModelSim Simulator (9)

Transcript .

- view wave : wave . - add wave * : wave . - force clk_in 0 0,1 20ns -repeat 40ns : 20 0 40 1 ( = 1 / = 1 / 40ns) 20ns 0, 40ns 40 ) - force resetn 0 0,1 80ns : 1 80ns 0 - run 2000ms : 2

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ModelSim Simulator (10)

F(Full view), I(zoom In), O(zoom Out) . .

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EasySoC (1)

configuration FPGA . . . Assignments > Pin "design_name.qsf" .

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EasySoC (2)

, Location "PIN_#" , .

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EasySoC (3)

"desing_name.qsf" "easy_clock.qsf" .

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EasySoC (4)

.

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EasySoC (5)

Processing > Start Compilation . , Tools > Programmer .

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EasySoC (6)

, PC ByteBlaster-II . . "Hardware Setup" "Add Hardware" ByteBlasterMV or ByteBlaster II / LPT1 .

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EasySoC (7)

"Currently selected hardware:" ByteBlasterII[LPT1] Available hardware items .

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EasySoC (8)

EasySoC FPGA JTAG , EEPROM Active Serial . EEPROM Mode "JTAG" "Active Serial Programming"( JTAG Active Programming ( AS ) . AS .

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EasySoC (9)

"Add File" "easy_clock.pof" .

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EasySoC (10)

"Add File" "Program/Configure" "Start" . 1) DEVICE : Device 1 silicon ID is 0x14 2) DEVICE : Erasing ASP configuration device(s) 3) DEVICE : Programming device 1 4) DEVICE : Device 1 silicon ID is 0x14 5) : Successfully performed operation(s)

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EasySoC (11)

Process "100%" . ByteBlasterII (CON6) Power Off > On FPGA .

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EasySoC (12)

, 7segment LED ..

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Chapter 2. ARM APB 2 LED, 7-Segment

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EasySoC

FPGA AMBA EasySoC

LED 7-Segment Control IP

H-JTAG H JTAG AXD LED 7 Segment LED, 7-Segment

ARM control software ARM AXD

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FPGA IP AMBA APB Slave : AMBA ModelSim APB Simulation : AMBA Signal H-JTAG/AXD H JTAG/AXD IP IP

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EasySoC

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FPGA AMBA

Design_top - AMBA address decoder - IP module

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EasySoC Platform

ARM926 core : AHB2AHB bridge AHB slave AHB2AHB bridge AHB slave master 1 AHB Slave Master AHB master : AHB slave : master AHB matrix : 4 AHB master 10 AHB slave P i l Port AHB MUX arbiter APB bridge : AHB matrix slave '1' AHB bus APB bus

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EasySoC Platform

AHB master dummy AHB matrix master master dummy AHB slave dummy AHB matrix slave Slave dummy APB slave dummy APB bridge slave slave dummy Design IP : LED / 7-Segment IP APB slave '1' l

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LED 7-Segment EasyIP EasySoC (1)

EasySoC Platform ­

0 AHB Slave Dummy0 0 AHB Slave Dummy2 D 2 AHB Slave Dummy3 AHB Slave Dummy4 AHB Slave Dummy5 AHB Slave Dummy6 AHB Slave Dummy7 AHB Slave Dummy8 AHB Slave Dummy9 0 1 APB Slave Dummy0 APB Slave Dummy1 y APB Slave Dummy2 APB Slave Dummy3 APB Slave Dummy4 APB Sl Slave Dummy5 APB Slave Dummy6 APB Slave Dummy7

ARM926 Core

AHB2AHB Bridge

0 1

2

AHB Master Dummy1

1 AHB SUB MATRIX

3 4

2

3 2nd APB Bridge

5

4

AHB Master Dummy2

2 6

5

7 8 9

6 7

AHB Master Dummy3

3

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LED 7-Segment EasyIP EasySoC (2)

EasySoc Platform EasySoC E S C FPGA ARM926 C AHB b Core bus . FPGA AHB , AHB2AHB Bridge ARM926 Core AHB bus FPGA AHB bus . FPGA APB bus FPGA AHB bus . APB . AHB/APB bus IP Dummy . y

Dummy IP IP .

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LED 7-Segment EasyIP EasySoC (3)

EasySoC Platform ­ 7segment LED IP

0 AHB Slave Dummy0 0 AHB Slave Dummy2 D 2 AHB Slave Dummy3 AHB Slave Dummy4 AHB Slave Dummy5 AHB Slave Dummy6 AHB Slave Dummy7 AHB Slave Dummy8 AHB Slave Dummy9 0 1 APB Slave Dummy0 7-SEG / LED APB Slave Dummy2 APB Slave Dummy3 APB Slave Dummy4 APB Sl Slave Dummy5 APB Slave Dummy6 APB Slave Dummy7

ARM926 Core

AHB2AHB Bridge

0 1

2

AHB Master Dummy1

1 AHB SUB MATRIX

3 4

2

3 2nd APB Bridge

5

4

AHB Master Dummy2

2 6

5

7 8 9

6 7

AHB Master Dummy3

3

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LED 7-Segment EasyIP EasySoC (4)

EasySoC Platform 7segment LED . . APB APB Slave Dummy1 LED 7seg . EasySoC AHB APB IP Dummy , IP . , FPGA .

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EasySoC Peripheral Memory Map

EasySoC platform memory map . p 7-seg LED APB Dummy slave1 . 0x2000_0000. 0 4 . , AMBA . 1. LED Address : 0x2000_0000 2. 7-Segment Address : 0x2000_0004

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IP

1. LED IP - LED control Register '1' (HIGH), '0' (LOW) LED ON/OFF - 32bit LSB[7:0] 8bit

0x2000_0000

[7] LED7

[6] LED6

[5] LED5

[4] LED4

[3] LED3

[2] LED2

[1] LED1

[0] LED0

2. 7-Segment IP - 7-Segment control register number => number decoder => decoder 7-Segment Device > eco er 7 Segmen ev ce => 7-Segment display (Counter 90msec 7-Segment ON )

0x2000_0004

[31:28] 8 g 7-Seg

[27:24] 7 g 7-Seg

[23:20] 6 g 7-Seg

[19:16] 5 g 7-Seg

[15:12] 4 g 7-Seg

[11:8] 3 g 7-Seg

[7:4] 2 g 7-Seg

[3:0] 1 g 7-Seg

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FPGA APB

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FPGA AMBA

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LED 7-Segment Control IP AMBA

· : EasySoC

1. 1 (1) EasySoC development board (2) Expansion parallel cable ByteBlaster II (Parallel Port) : FPGA download (3) H-JTAG 2. 2 Design language - Verilog HDL 3. () (1) QuartusII 7.1 SP1 web edition (2) ARM ADS 1.2 (3) H-JTAG : H-JTAG server (4) Active Perl for windows : Modelsim simulation (5) ModelSim

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Design file

1. folder name : APB_7-SEG_LED_start_source_code 2. 2 Project Open (1) File > Open Project... (2) start_source_code st2soc.qpf click

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Design file

3. Design file (1) Project Navigator Files Tab click (2) Device Design Files click => Add/Remove Files in Project... click

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Design file

(3) click (4) LED, 7-Segment IP apb_segled_top.v , apb_segled_sm.v , seven_seg.v .

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Design file

(5) OK click

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Design file

(6) APB design file .

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Project Hierarchy

1. ARM926 core I/F design (1) Top file : design_top.vhd ( : \rtl\topfile ) 2. AMBA bus ( : \rtl\amba ) (1) ahb_matrix_m4s10r_rec.vqm : AHB matrix (.vqm : Verilog Quartus Mapping file) ( ) (2) ahb2ahb_sync_rec.vqm : AHB2AHB _ y _ q (3) ahb2apb_p8_rec.vqm : AHB APB bridge (4) ahb_dummy_master_rec.vhd : AHB dummy master (5) ahb_dummy_slave_rec.vhd : AHB dummy slave ahb dummy slave rec vhd (6) apb_dummy_slave_rec.vhd : APB dummy slave 3. APB design file ( : \rtl\segment_led\AMBA ) (1) apb_segled_top : AMBA Slave Port (2) apb_segled_sm.vqm : APB State machine g g _ 4. 7-Segment/LED FPGA IP ( : \rtl\segment_led\FPGA ) (1) top_segled,vhd, segled_ctrl.vqm, bin2seg.vqm : 7-SEGMENT IP

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AMBA IP

1. apb_seg_led_rec.v : module net - 651~657 line : APB Dummy Slave '1' - 664~673 line : sig apb s1 in sig apb s1 out APB Slave 1 sig_apb_s1_in sig_apb_s1_out .

7segment, LED

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FPGA in/out port

1. 82 line : 7-Segment, LED out port

2. 132~134 line : 7-Segment, LED out port

3. 217~219 line : 7-Segment, LED net g

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FPGA pin assign

1. Logic I/O port FPGA I/0 pin 1) Project st2soc.qsf 2) 179~196 line .: 7 Segment pin assign : 7-Segment 3) 198~205 line : LED pin assign

.

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IP (1)

apb_segled_sm.v .

0x2000_0000

0x2000_0004

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IP (2)

seven_seg.v apb_segled_sm.v IP .

7segment

7segment

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Project compile/image file download

1. Start Compilation Icon click ( )

Compile compile .

2. Image file download(.pof) (1) Programmer Icon click ( )

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Project compile/image file download

(3) Add File click (4) Project .pof file click

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Project compile/image file download

(5) Program/Configure, Verify, Blank-Check check box check Start click (6) Reset Power (Power off on )

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ARM software

ARM926 Core

AHB2AHB Bridge AHB SUB MATRIX 2nd APB Bridge 7-SEG / LED 0x2000_0000 0x2000_0004

0x2000_0000 0x2000_0004 LED 7segment IP . , ARM926 Core LED IP . IP . 1. 0x2000_0000 0x2000_0004 test c test.c . 2. ARM Core CPU 7-segment LED .

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ADS (1)

APB 7segment LED ARM 7segment LED . File-New New

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ADS (2)

ARM Executable Image

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ADS (3)

, ARM9 . Add files Project ­ add files .

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ADS (4)

initmn.s test.c .

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ADS (5)

. initmn.s : ARM CPU , . test.c t t : . main .

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ADS (6)

.

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ADS (1)

Debug settings . Target .

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ADS (2)

ARM Assembler FPU, Byte .

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ADS (3)

ATPCS .

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ADS (4)

.

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ADS (5)

ARM C Compiler .

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ADS (6)

ARM Linker . .

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ADS (7)

Linker ,

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ADS (8)

.

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ADS (9)

map . ADS .

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ARM software (1)

1. 2.

test.c . C , , .

3.

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ARM software (2)

. i 0 9 LED 7 0~9 7segment t .

i=i+1 i = i % 10 LED 3 segment 2 segment 1 segment segment

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ARM software (3)

. #define LED8_OUTPUT_REG . LED8_OUTPUT_REG *(volatile unsigned int *) 0x20000000 . volatile , . LED8 OUTPUT REG 0x2000 0000 unsigned LED8_OUTPUT_REG 0x2000_0000 int . , LED8_OUTPUT_REG = 1 0x2000_0000 1 .

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ARM software (4)

arm_main define LED8_OUTPUT_REG, 0x2000_0000 . 0x2000 0004 FND OUTPUT REG 0x2000_0004 FND_OUTPUT_REG .

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ARM software (5)

Make

Debug

, Make . ARM AXF . D b AXD ARM926 Debug . .

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H-JTAG AXD LED, 7-Segment

1. H-JTAG Server 2. Settings > Target setting ARM926EJ-S . 3. 3 Control > Detect target 4. AXD Debugger

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H-JTAG AXD LED, 7-Segment

Register Memory Go Step over Breakpoint

Debug .

Run to cursor

Register view, Memory view, Go, step over, run to cursor, breakpoint. Register view : Register file . Memory view : memory . Go : . Go break point . Breakpoint . step over : . run to cursor : . Breakpoint : breakpoint / .

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H-JTAG AXD LED, 7-Segment

4. Options > Configure Interface... click Target connection "HALT" "" click Kernel Run AXD debugger .

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H-JTAG AXD LED, 7-Segment

5. Processor View > Memory 6. Memory mouse click => click => size > 32bit

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H-JTAG AXD LED, 7-Segment

7. register PLL control register address : 0x12003030, Status control register address : 0x1200302C 0x1200302C, 8. Register address mp 7-SEGMENT control register address : 0x20000000 LED control register address : 0x20000004 value : 0x0103162B value : 0x00000020

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LED 1 . 7segment 0 9 . . LED 7segment .

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Chapter 3. ARM 3 Keypad

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Keypad

Memory map

Keypad

IP Software

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Keypad IP

: 7segment IP keypad . 1) keypad . 2) 7segment IP keypad IP 3) ARM firmware keypad 7segment LED

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FPGA APB

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FPGA AMBA

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EasySoC Peripheral Memory Map

7-seg LED APB Dummy slave1 . 0x2000_0000. , 7segment IP keypad . IP . 1. 7-Segment Address : 0x2000_0000 2. LED Address : 0x2000_0004 3. Keypad Address : 0x2000_0008

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IP

1. Key IP - 7-segment/LED IP . - keypad . - 32bit1bit - .

0x2000_0008

[31] ...

... ...

... ...

... ...

... ...

... ...

[1] 0

[0] Keypad[0]

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FPGA in/out port

1. 84 line : keypad port

2. 138 line : keypad input port

2. 138 line : 7seg IP keypad input port

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apb_segled_top.v file

1. - segled_top keypad input

Keypad

2. - segled sm keypad input segled_sm

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FPGA pin assign

1. Logic I/O port FPGA I/0 pin 1) Project st2soc.qsf 2) 179~196 line .: 7 Segment pin assign : 7-Segment 3) 198~205 line : LED pin assign

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Keypad (1)

1. - keypad input

2. - reset , key_reg 0 - key_reg 0

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Keypad (2)

3. AMBA Read/Write - ARM CPU IP Read/Write - keypad 0008 Read . yp

ARM CPU Write 0008

Read ,

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FPGA pin assign

1. Logic I/O port FPGA I/0 pin 1) Project st2soc.qsf 2) PIN AC21 EasySoC PIN_AC21 . input_key1 1 . 3) , FPGA .

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ARM software

1. - keypad

2. 2 - , 7segment 0 .

0 9

Keypad 0 7segment LED

127

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Microsoft PowerPoint - Ex_02_LED_7seg_keypad.ppt [ ]

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