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A LOW SERIES RESISTANCE, HIGH DENSITY, TRENCH CAPACITOR FOR HIGHHIGH-FREQUENCY APPLICATIONS

Gordon Grivna, Sudhama Shastri, Yujing Wu, & Will Cai

Sept, 2008

www.onsemi.com

Presentation Outline

1. Introduction / purpose 2. High frequency trench capacitors a) MIS trench capacitors b) High frequency "wrap-around" PIP cap. 3. High frequency PIP capacitor characterization a) Electrical characterization and modeling b) Reliability evaluation 4. Potential enhancements / applications 5. Summary 6. Acknowledgments

1. Introduction/Purpose

A modular, high speed, VLSI MOS-compatible decoupling trench capacitor with tunable frequency response has been modeled and electrically characterized. The flexible capacitor design enables low Dt, drop-in capability across a number of technologies and has been qualified for both CMOS and BiCMOS applications.

2. High frequency trench capacitors a) MIS trench capacitors

"Typical" MIS trench bypass capacitors suffer from large series resistance and consequent poor frequency response.

MIS Trench Capacitors Structure of "typical" MIS type bypass trench capacitor with implanted bottom plate

SINGLE DIODE TRENCH CAPACITOR

40KA

POLYSILICON RESISTOR

AlSi

BOTTOM PLATE TOP PLATE TOP PLATE

BOTTOM PLATE

N+

P+

N Epi

P+

P+ Well

HIGH RESISTANCE LOWER PLATE CONNECT P+ POLY TOP ELECTRODE 400A NITRIDE DIELECTRIC

.005 Ohm-cm Boron Substrate

MIS Trench Capacitors Structure of high density RF MIS trench capacitor with laterally diffused bottom plate

(Extracted from F. Roozeboom et. al. -International Microelectronics and Packaging Society, 2001 )

MIS Trench Capacitors

Diffused bottom plate trench capacitors lose their effectiveness as the capacitance per unit area increases, since the bottom plate resistance can become prohibitively large. As trench depth and capacitance per unit area increase further, low resistance access to the bottom plate becomes critical for high speed applications.

MIS Trench Capacitors

Trench Capacitor Device Suitable for Decoupling Applications in High-Frequency Operation

Extracted from International Patent Publication Number WO 2007/054870 A1, May 2007

Bottom plate backside contact

Top plate frontside contact

2. High frequency trench capacitors

a) MIS trench capacitors b) High frequency "wrap-around" PIP capacitor

"Wrap-Around" PIP Capacitor

X-section view of "wrap-around" PIP capacitor for on-chip bypass and tuning applications

NN+ I

P+ Substrate

Trench Bottom Contact Bottom plate contact trench PIP capacitor "finger"

Substrate contact or isolation trench

"Wrap-Around" PIP Capacitor

Diffusion model of trench bottom plate

The use of a highlydoped bottom liner poly electrode and the consequent outdiffusion makes this capacitor function even in the presence of highly-doped buried layers which may otherwise "break" the connection of the bottom electrode.

N+ EPI

P+ Substrate

"Wrap-Around" PIP Capacitor

X-section view of "wrap-around" PIP cap

contact trench/bottom plate contact top plate contact

top plate dielectric layer bottom plate

contact trench

capacitor trench

"Wrap-Around" PIP Capacitor

X-section drawing of "wrap-around" PIP capacitor in lightly doped substrate

N-

Reduced resistance to bottom plate

P- Substrate

Substrate contact or isolation trench

Bottom plate contact trench

PIP capacitor "finger"

"Wrap-Around" PIP Capacitor

X-section SEM of "wrap-around" PIP capacitor in lightly doped substrate

"Wrap-Around" PIP Capacitor

The addition of a separate bottom plate enables "dropin" capability irrespective of the substrate doping type, EPI layers, thermal budget, or substrate dielectric layers.

Top Plate

Bottom plate

Capacitor Dielectric Previous Silicon top structure

3. High frequency PIP capacitor characterization a) Electrical characterization and modeling b) Reliability evaluation

Electrical Characterization

Leakage comparison of MIS cap (no liner) on bare silicon substrate to PIP cap with bottom polysilicon liner

Current Vs Voltage

1.0E-06 1.0E-07 1.0E-08

Current (Amps)

1.0E-09 1.0E-10 1.0E-11 1.0E-12 1.0E-13 0 2 4 6 8 10 12 14 16 18 20

wfr 1, wfr 5, wfr 2, wfr 4, wfr 3, wfr 6,

no liner no liner 500A 500A 1700A 1700A

Voltage, Volt

Electrical Characterization

Poly lined trench caps have improved linearity compared to standard MIS trench caps.

Capacitance Vs Applied Voltage

11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 0 1 2 3 4 5

Voltage, volt

Capacitance, fF/um2

wfr 1, no liner wfr 5, no liner wfr 2, 500A wfr 4, 500A wfr 3, 1700A wfr 6, 1700A

6 7 8 9 10

Electrical Characterization

High linearity, good acrosswafer uniformity (±1.25%)

Electrical Characterization Low leakage, excellent linearity over temperature

Device Modeling

Layout nf=5, np=2 Cross-section nf (fingers) =3, np (modules in parallel) =2

Device Modeling

Very High Frequency Capacitor Layout nf=2, np=20

Capacitor Trench Substrate Contact Trench Isolation Trench

Device Modeling

Reduced Frequency Capacitor for audio-band filter chip

nf=16, np=1

Device Modeling

Distributed R-C model for nf=2, NV=6. Metal inductance is optionally added.

Device Modeling

Ceff=Im(Yij)/(2f), is the effective capacitance extracted from Yparameters; it includes the effect of series resistance NV~8 is sufficient for the model, that is, eight vertical sections are enough for ensuring accuracy

Device Modeling

A given target capacitance is obtained by a combination of fingers and parallel sections. The lower nf is, the better is the frequency response.

Model-Extraction

Pseudo-2D treatment is valid for the widths under consideration

Model Extraction

Low-frequency data obtained from LCR meter and highfrequency data obtained from Network Analyzer A low-frequency fit is first obtained: only 1-2 parameters are tweaked; the rest are geometry-based

Zero bias measurements for various nf and np values with maximum error of only 0.6%

Trench "length" data showing low frequency error of less than 1.1%

Model Extraction

nf=4, np=10 nf=40, np=1

RF parameter extraction requires S-parameter data from 2-port GSG measurements. Device asymmetry can be predicted using lumped element model. Correctly modeling substrate resistance is very important.

3. High frequency PIP capacitor characterization a) Electrical characterization and modeling b) Reliability evaluation

Reliability Evaluation

TEM Construction Analysis

Reliability Evaluation

TEM Evaluation of Capacitor Dielectric

Trench Sidewall

Trench Bottom

Trench Bottom "Corner"

Reliability Evaluation

Lognormal Distributions of Intrinsic TDDB Failures

Capacitor data With Individual Lognormal MLE's Lognormal Probability Plot

.98 .95 .9 .8 4.5MV.per.cm 4.75MV.per.cm 5MV.per.cm 5 16

Fraction Failing

.7 .6 .5 .4 .3 .2 .1 .05 .02 .01 .005 2 5 10 20 50 100 200 500

Hours

Wed Sep 29 17:26:41 2004

Reliability Evaluation

Maximum Likelihood Fit Extrapolation to 10 V @ 150 °C

Capacitor data with Lognormal Linear Model MLE Lognormal Probability Plot

.9999 .999 .995 .98 .95 .9 .8 .6 .4 .2 .1 .05 .01 .002 .0005 .00005 .000003 10^00 10^01 10^02 10^03 10^04 10^05 10^06 10^07 10^08 10^09 10^10 4.5MV.per.cm 4.75MV.per.cm 5MV.per.cm 2 MV.per.cm

Fraction Failing

Hours

Wed Sep 29 18:23:35 2004

Reliability Evaluation

Lifetime Estimates 10 V @ 150 °C

·Quantile Estimates ·From Capacitor data at 2 MV.per.cm ·Lognormal MLE and Pointwise Approximate 90% Confidence Intervals · p · 0.001 · 0.005 · 0.010 · 0.050 · 0.100 · 0.200 · 0.300 · 0.400 · 0.500 · 0.600 · 0.700 · 0.800 · 0.900 · 0.990 Quanhat 193509360 265309753 309187546 469668005 586927866 768766377 933922386 1102876638 1288325603 1504957855 1777217127 2159021141 2827916269 5368207358 Std.Err. 121049290 165510803 192684448 292159050 364961308 478075427 581039386 686586047 802673961 938577225 1109797762 1350632142 1774365391 3399989142 90% Lower 69157870 95085143 110928051 168820772 211052126 276413038 335643103 396108502 462337302 539528708 636294633 771571247 1007511006 1894045950

7,895 years

90% Upper 5.415e+008 7.403e+008 8.618e+008 1.307e+009 1.632e+009 2.138e+009 2.599e+009 3.071e+009 3.590e+009 4.198e+009 4.964e+009 6.041e+009 7.937e+009 1.521e+010

Reliability Evaluation

Lognormal Distributions Extrinsic Failure Mode Evident

Capacitor data With Individual Lognormal MLE's Lognormal Probability Plot

.98 .95 .9 .8 4.5MV.per.cm 4.75MV.per.cm 5MV.per.cm 5 16

Fraction Failing

.7 .6 .5 .4 .3 .2 .1 .05 .02 .01 .005

Extrinsic Failures

0.5

1.0

2.0

5.0

10.0

20.0

50.0

100.0

200.0

500.0

Hours

Wed Sep 29 16:42:35 2004

Reliability Evaluation

Capacitor dielectric thinning on top surface after poly etchback found as source for extrinsic failures

Nitride~230A

Nitride on trench sidewall

Top nitride after polysilicon etchback

4. Potential enhancements and applications

Enhancements

Multi-use trench process: isolation, oxide termination, substrate contact, bottom plate contact

Enhancements

Oxide lined trench with substrate contact opening

Enhancements

Optical X-section view of oxide lined trenches with substrate contact

Enhancements

Oxide isolated substrate contacts

SEM showing deep polysilicon contact

SEM highlighting dopant outdiffusion

Enhancements

Oxide isolated substrate contacts

Boron doped poly fill

Phosphorous doped poly fill

Enhancements

Insitu doped trench (post 1100C 45min anneal)

Boron doped

Phos doped

Enhancements

Extreme trench depth for very high capacitance on chip

Enhancements

Potential for silicide bottom plate for further resistance reduction.

N-

P- Substrate

Substrate contact or isolation trench

Bottom plate PIP capacitor contact trench "finger"

5. Summary

A high-performance trench capacitor has been integrated into RF BiCMOS and other technologies. A distributed trench-capacitor model has been developed and implemented in SPICE.

Summary

Models have been successfully used in several high-frequency designs. Capacitor has been successfully added to multiple substrates and process integrations. Several potential enhancements have been demonstrated.

6. Acknowledgments: The authors would like to thank: The ON Semiconductor analytical and reliability labs for their assistance and numerous analysis reports. The entire ON Semiconductor technology development team and COM1 wafer fab.

Information

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