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STARC STIL(SSTAG)

IEEE Std 1450.6-2005

STIL

Revision 1.00 2010/9/30

Copyright STARC 2010

Copyright STARC 2010

STIL IEEE Std 1450.6-2005

STIL1450.6

IEEE Specification1 1-515 DescriptionSTIL ApplicationSTILSTIL EnvironmentSTILSTIL 1 2 3 1 2 3

2010/9/30 Revision 1.00)

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IEEE Std 1450.6-2005 Specification Extensions to IEEE Std 1450-1999 and IEEE Std 1450.1-2005 1 2 3 4 5 6 7 27 27 27 28 28 29 32 STIL name spaces and name resolution Optional statements of IEEE Std 1450-1999 Restricting the usage of SignalGroup and variable names Additional reserved words STIL statement-extensions to IEEE Std 1450-1999,Clause 8 Extensions to IEEE Std 1450-1999, 17.1 and 23.1 Extensions associated with the LockStep construct of Clause 13 of IEEE Std 1450.12005

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Design hierarchy-cores 1 2 3 36 36 37 CoreType block and CoreInstance statement CoreType block syntax descriptions CoreType block code example

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Cell expression(cellref_expr) 38 Environment block-extensions to IEEE Std 1450.1-2005, Clause 17 1 2 3 4 5 39 39 43 43 44 General Definition of FileReference keywords Example of Environment block FileReference syntax Extension to NameMaps Extension to the inheritance of environment statements

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CTLMode block 1 2 3 4 45 45 47 53 General CTLMode syntax CTLMode block-syntax descriptions CTLMode block syntax example

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10 CTLMode-Internal block 1 2 3 4 56 56 60 76 General Internal syntax Internal block syntax descriptions Internal block syntax example

11 CTLMode-ScanInternal block 1 2 3 4 79 79 81 81 General ScanInternal syntax ScanInternal block syntax descriptions ScanInternal block syntax example

12 CTLMode-CoreInternal block 1 2 3 4 83 83 84 84 General CoreInternal syntax CoreInternal block syntax descriptions CoreInternal block syntax examples

13 CTLMode-Relation block 1 2 3 4 85 85 85 87 General Relation syntax Relation block syntax descriptions Relation block syntax example

14 CTLMode-ScanRelation block 1 2 3 89 89 89 General ScanRelation syntax ScanRelation block syntax descriptions

Copyright STARC 2010

STIL IEEE Std 1450.6-2005

STIL1450.6

IEEE Specification1 1-515 DescriptionSTIL ApplicationSTILSTIL EnvironmentSTILSTIL 1 2 3 Transition Launch/Capture (1) Transition Launch(*)/Capture * LaunchRelease Page 5-12 Application 1 2 3

2010/9/30 Revision 1.00)

IEEE Std 1450.6-2005 Specification 15 CTLMode-External block 1 2 3 4 89 90 90 93 General External syntax External block syntax descriptions External block syntax example

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16 CTLMode-PatternInformation block

Launch/Caputre1450.6Internal UserKeywords ClockRelations RELATION_NAME Pattern Launch/CaptureVector ClockRelations RELATION_NAME Launch/Capture UserKeywords ClockRelations RELATION_NAME Vector MacroDefs ProceduresLoopShiftVector Launch/Capture STIL1450.0Rev4.00 UserKeywords ClockRelations UserKeywords ClockRelations (RELATION_NAME 1450.6 IsConnected InTestAccess (STIL 1450.0Rev5.00 Transition release/capture )

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PatternInformation syntax

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STIL() STIL Transition() "LoC" (*1) "LoS"(*2) * 1 LoCLaunch On Capture/ Launch Off Capture ( Broadside) * 2 LoSLaunch On Shift/ Launch Off Shift ( Skewed-Load )

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Application

STIL() PatternInformationPattern PatternBurst PurposeUser USER_DEFINED STIL 1450.0Rev4.00 UserKeywordsTestType SolutionUser TestType (STIL 1450.0Rev5.00 )

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PatternInformation block syntax PatternInformation block syntax example

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IEEE1450.6 (User-defined name) CTLModeDomainReferences FocusCoreInstance CORE_INSTANCE_NAME Internal ElectricalProperty ELECTORICAL_PROPERTY_IDIsConnected IsDisabledByLOGICSIGNAME 1450.6 EnvironmentCTLMode CTLMODE_NAME CTLModeFamily NAMEUser USER-DEFINED VenderNAMEIsConnected IsGatedByLOGICSIGNAME ExternalConnectTo SymbolicSYMBOLIC_NAME

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Description Named Block CTLModeDomainReferences CORE_INSTANCE_NAME FocusCoreInstance CORE_INSTANCE_NAME IsConnectedIsDisabledByLOGICSIGNAME CTLModeInternalElectricalProperty ELECTORICAL_PROPERTY_IDSignals STIL

STILIEEE1450.0IEEE1450.1 1450.21450.3 STIL

Rev 1.00

2010/9/30

No No No1 No2 No3 TransitionLaunch/Capture

Copyright STARC 2010

STIL

STIL1450.6-2005 STIL

2010 STIL 2010STIL /OKI

Copyright STARC 2010

STIL

No

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IEEE Specification Page100

Clause 16 : CTLMode-PatternInformation block

Application STILSTIL

STIL()STIL Transition() "LoC"(*1) "LoS"(*2) * 1 LoCLaunch On Capture/ Launch Off Capture ( Broadside) * 2 LoSLaunch On Shift/ Launch Off Shift ( Skewed-Load )

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Solution

STIL()PatternInformationPattern PatternBurstPurpose User USER_DEFINED

STIL1.0 { Design 2005; CTLMode 2005; } Environment (ENV_NAME) { (CTLMode CTLMODE_NAME { (PatternInformation { (<Pattern PatternBurst> (pat_or_burst_name) { (Purpose ( User TestType < FC | DC | FCDC | AC >) // ( User ScanLaunch < Shift | Capture | Mix | Any >) // Scan ( User Load < Normal | DeCompression >)// ( User Unload < Normal | Compression >) ; )// })*//End Pattern or PatternBurst })//End PatternInformation })*//End CTLMode }//End Environment

(1) (2) (3) (4)

STIL1450.0Rev4.00UserKeywords TestType SolutionUser TestType(STIL 1450.0Rev5.00)

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Solution()

<> (1)TestType FC DCDC FCDCDC ACAC (2)ScanLaunchScanTypeDynamic Shift LoS- CaptureLoC Mix Any (3)Load Normal STILFF DeCompression STILFF (4)Unload Normal STILFF Compression STILFF

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1 STIL 1.0 { Design 2005 CTL 2005; } PatternBurst BURST1 { PatList { TR1; } } PatternExec EXEC1 { PatternBurst BURST1; Pattern TR1{ }

Environment ENV1 { CTLMode MODE1 { PatternInformation { Pattern TR1 { Purpose User TestType FC User ScanLaunch Shift User Load DeCompression User Unload Compression ; }//End Pattern }//End PatternInformation }//End CTLMode }//End Environment

Pattern TR1 LOS Transition

2 STIL 1.0 { Design 2005 CTL 2005; } PatternBurst TR1 { PatList { PAT1; PAT2; } } PatternExec EXEC1 { PatternBurst TR1; Pattern PAT1{ } Pattern PAT2{ }

Environment ENV1 { CTLMode MODE1 { PatternInformation { PatternBurst TR1 { Purpose User TestType FC User ScanLaunch Capture ; }//End PatternBurst }//End PatternInformation }//End CTLMode }//End Environment Copyright STARC 2010

PatternBurst TR1 Transition LOC

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STARC SSTAG TransitionLaunch/Capture

IEEE Specification Page100

Clause 21: STIL Pattern Data

Application STILSTIL

TransitionLaunch(*)/Capture * LaunchRelease

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Solution Launch/Caputre1450.6 InternalUserKeywords ClockRelations RELATION_NAME PatternLaunch/CaptureVector ClockRelations RELATION_NAMELaunch/Capture UserKeywords ClockRelations RELATION_NAMEVector MacroDefsProceduresLoopShiftVector

DECIMAL_INTEGER TestAccess< Macro | Procedure > STIL 1.0 { Macro Procedure NAME Design 2005 CTL 2005; VectorLaunchCapture Macro Procedure } Vector UserKeywords ClockRelations; Environment ( ENV_NAME ) { PLL CTLMode ( CTLMODE_NAME ) { OffsetLaunchClockVector Internal { CaptureClockVector (ClockRelations RELATION_NAME { (sigref_expr //1 Vector IsConnected In { Launch, Capture (TestAccess ( User VectorCountToLaunch DECIMAL_INTEGER (StartDelay time_exor) ) ( User VectorCountToCaptue DECIMAL_INTEGER (StartDelay time_exor) ) 0 < Macro | Procedure > NAME;)* ( < LaunchClock | CaptureClock ( offset DECIMAL_INTEGER) > SIGNAME { //1 <LeadingEdge | TrailingEdge>; StateAfterEvent <ExpectLow | ExpectHigh > ; ) } )* // end LaunchClock }* // end IsConnected sigref_exprSignal expressions define an ordered list of signals; they are either a single token, or an expression })* // end sigref_expr enclosed in single quotes. Signal expression operators are plus (+), minus (-), ellipsis (..), and })* // end ClockRelations parentheses. These operators are not extendable. Expressions are evaluated left-to-right, with } // end Internal parentheses used to override this order. Signals referenced in signal expressions may occur only once in the sub-expressions generated during evaluation of the expression. } // end CTLMode } // end Environment

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PatternBurst DOMAIN_NAME { ParallelPatList SyncStart { PATTERN_NAME1; PATTERN_NAME2; } } Pattern PATTERN_NAME1 { V{ } ClockRelations (RELATION_NAME)+ } Pattern PATTERN_NAME2 { V{ } ClockRelations (RELATION_NAME)+ } //ClockRelationsVector

Launch/CaptureSTIL1450.0Rev4.00UserKeywords ClockRelations ClockRelations (RELATION_NAME1450.6 IsConnected InTestAccess(STIL1450.0Rev5.00 Transitionrelease/capture)

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1 STIL 1.0 { Design 2005 CTL 2005; } UserKeywords "ClockRelations"; Procedures { "load_unload"{ W "TS"; C{ ;} Shift { V{ si=#; so=#;;} } } } Pattern PAT1 { W "Default"; Macro "test_setup";//MacroDefs // Call "load_unload" { si= ; so=; } V{ } // CLK3Launch //CLK3Capture ClockRelations "TEST1"; V{ } V{ } }

Environment { CTLMode CTLMODE1 {//CTLMODE_NAME Internal { ClockRelations "TEST1" { Launch "CLK3" Capture IsConnected In { LaunchClock "CLK3" { LeadingEdge; StateAfterEvent ExpectHigh; } // end LaunchClock } // end IsConnected IsConnected In { CaptureClock "CLK3" { TraillingEdge; StateAfterEvent ExpectLow; } // end CaptureClock } // end IsConnected } // end sigref_expr } // end ClockRelations } // end Internal } // end CTLMode } // end Environment

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2 STIL 1.0 { Design 2005 CTL 2005; } UserKeywords "ClockRelations"; Procedures { "load_unload"{ W "TS"; C{ ;} Shift { V{ _si=#; _so=#;;} } } } Pattern PAT1 { W "Default"; Macro "test_setup";//MacroDefs // Call "load_unload" {_si= ; _so=; } V{ } // CLK3CLK1Launch ClockRelations "TEST1" "TEST2"; // CLK3Capture V{ } // V{ } //2 CLK2Capture } Environment { CTLMode "CTLMODE1" { //CTLMODE_NAME Internal { ClockRelations "TEST1" { Launch "CLK3" IsConnected In { Capture LaunchClock "CLK3" { LeadingEdge; StateAfterEvent ExpectHigh ; } // end LaunchClock

CaptureClock "CLK3" { TraillingEdge; StateAfterEvent ExpectLow ; } // end CaptureClock } // end IsConnected } // end sigref_expr } // end ClockRelations ClockRelations TEST2 { ` "CLK1"+"CLK2" ' IsConnected In { LaunchClock "CLK1" { LeadingEdge; StateAfterEvent ExpectHigh ; } // end LaunchClock CaptureClock Offset 2 "CLK2" { TraillingEdge; StateAfterEvent ExpectLow ; } // end CaptureClock } // end IsConnected } // end sigref_expr } // end ClockRelations } // end Internal } // end CTLMode } // end Environment

Launch Capture

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STIL 1.0 { Design 2005 CTL 2005; } UserKeywords "ClockRelations"; Procedures { LOC "load_unload"{ W "TS"; Launch Capture C{ ;} Shift { V{ _si=#; _so=#;;} } } } Pattern PAT1 { W "Default"; Macro "test_setup";//MacroDefs // Call "load_unload" {_si= ; _so=; } V{ _se=0 CLK3=P } // CLK3Launch ClockRelations "TEST1" ; V{ _se=0; CLK3=P; } // CLK3Capture } Environment { CTLMode "CTLMODE1" { //CTLMODE_NAME Internal { ClockRelations "TEST1" { "CLK3" IsConnected In { LaunchClock "CLK3" { LeadingEdge; StateAfterEvent ExpectHigh ; } // end LaunchClock CaptureClock Offset 1 "CLK3" { TraillingEdge; StateAfterEvent ExpectLow ; } // end CaptureClock } // end IsConnected } // end sigref_expr } // end ClockRelations } // end Internal } // end CTLMode } // end Environment

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STIL 1.0 { Design 2005 CTL 2005; } UserKeywords "ClockRelations"; LOS Procedures { "load_unload"{ Launch Capture W "TS"; C{ ;} Shift { V{ _si=#; _so=#;;} } } } Pattern PAT1 { W "Default"; Macro "test_setup";//MacroDefs // Call "load_unload" {_si= ; _so=; } V{ _se=0; CLK3=0; } V{ _se=1; CLK3=P; } // CLK3Launch ClockRelations "TEST1" ; V{ _se=0; CLK3=P;

} // CLK3Capture

} Environment { CTLMode "CTLMODE1" { //CTLMODE_NAME Internal { ClockRelations "TEST1" { "CLK3" IsConnected In { LaunchClock "CLK3" { LeadingEdge; StateAfterEvent ExpectHigh ; } // end LaunchClock CaptureClock Offset 1 "CLK3" { TraillingEdge; StateAfterEvent ExpectLow ; } // end CaptureClock } // end IsConnected } // end sigref_expr } // end ClockRelations } // end Internal } // end CTLMode } // end Environment

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5 STIL 1.0 { Design 2005 launch CTL 2005; } load_unload UserKeywords "ClockRelations"; PLLCLK1 Timing { WaveformTable "Default" { Period 10ns; Start Delay Proc1 } PLLCLK2 1.25ns WaveformTable "TS_Launch" { Period 2.5ns; Waveforms{ PatternBurst "TRNS" "PLLCLK1" 01{ 0ns D; 1.25ns D/U; 2.5ns D; } PatList "Sync_Pat" }} WaveformTable "TS_Capture" { ParallelPatList SyncStart { Period 5ns; "Launch_Pat"; // CaptureClock Waveforms{ "Capture_Pat"; // CaptureClock "PLLCLK2" 01{ 0ns D; 2.5ns D/U; 5.0ns D; } } } }} PatternExec { } PatternBurst "TRNS" ; Procedures { } "load_unload" { //PLLCLK2 Pattern "Sync_Pat" { W "TS_Launch"; W "Default"; C{ `"ALLPIN"-"PLLCLK2"'=;} Macro "test_setup";//MacroDefs Shift { V{ _si=#; _so=#; "PLLCLK1"=1;} } //Macro test_setup ClockRelations "TEST1"; //ShiftVector V{ "refclk" =P, //(1)PLLCLK15 V{ "refclk" =P, // Launch : } V{ "refclk" =P, "Proc1" { //PLLCLK2 } W "TS_Capture"; Pattern "Launch_Pat" { V{ "PLLCLK2"=#,}//1 Launch/Capture Clock W "Default"; V{ "PLLCLK2"=#;}//2 //TS_LaunchTS_Capture V{ "PLLCLK2"=#;}//3 ClockRelations // V{ "PLLCLK2"=#;}//4 //launchCapture V{ "PLLCLK2"=#;}//5 //2PatternLaunch_PatCapture_Pat) V{ "PLLCLK2"=#;}//6 Call "load_unload" { si= ; so=;} V{ "PLLCLK2"=#;}//7 } ClockRelations "TEST1"; //(2)10ns7 //PLLCLK2Capture Pattern "Capture_Pat" { // W "Default"; } Call "Proc1" {"PLLCLK2"=1111111;} } }

capture

Environment { CTLMode "CTLMODE1" { Internal { ClockRelations "TEST1" { `"PLLCLK1"+"PLLCLK2"' { IsConnected In { TestAccess User VectorCountToLaunch 5 Procedure "load_unload"; //(1) LaunchClock "PLLCLK1" { LeadingEdge; StateAfterEvent ExpectHigh; }//End LaunchClock TestAccess User VectorCountToCapture 7 StartDelay '1.25ns' Procedure "Proc1"; //(2) CaptureClock "PLLCLK2" { TraillingEdge; StateAfterEvent ExpectLow; }//End CaptureClock }// End IsConnected }//End sigref_expr }//End ClockRelations }//End Internal }//End CTLMode }//End Environment

) PLLCLK1PLLCLK2Pseudo

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6 STIL1.0 { Design2005; CTL 2005; launch capture } UserKeywords "ClockRelations"; Load_unload Timing { PLLCLK1 WaveformTable "Default" { Period 10ns; } WaveformTable "TS_Launch_Capture" { Period 2.5ns; Waveforms{ "PLLCLK1" 01{ 0ns D; 1.25ns D/U; 2.5ns D; } Pattern "Sync_Pat" { }} W Default } Macro "test_setup"; //MacroDefs Procedures { //Macro test_setup; V{ "refclk" =P, "load_unload"{ V{ "refclk" =P, W TS_Launch_Capture; : C{ `ALLPIN'=;} Shift { V{ _si=#; _so=#; PLLCLK1=1;} } V{ "refclk" =P, ClockRelations "TEST1"; //(1),(2)5 } //PLLCLK1 Pattern "Pat1" { //Launch W Default ; //Capture // // } //LaunchCapture } Call "load_unload"{ "s"i= ; "so"=;} PatternBurst "TRNS" { } PatList { Sync_Pat; Pat1; } } Launch/Capture Clock PatternExec { ClockRelations PatternBurst "TRNS" ; }

Environment { CTLMode "CTLMODE1" { Internal { ClockRelations "TEST1" { "PLLCLK1" { IsConnected In { TestAccess User VectorCountToLaunch 5 Procedure "load_unload"; LaunchClock "PLLCLK1" { LeadingEdge; StateAfterEvent ExpectHigh; }//End LaunchClock TestAccess User VectorCountToCapture 5 Procedure "Proc1"; CaptureClock "PLLCLK1" { TraillingEdge; StateAfterEvent ExpectLow; }//End CaptureClock }// End IsConnected }//End sigref_expr }//End ClockRelations }//End Internal }//End CTLMode }//End Environment

//(1)

//(2)

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IEEE Specification Page27

5. Extensions to IEEE Std 1450-1999 and IEEE Std 1450.1-2005

DescriptionSTIL

IEEE1450.6(User-defined name) CTLModeDomainReferencesFocusCoreInstance CORE_INSTANCE_NAMEInternalElectricalProperty ELECTORICAL_PROPERTY_IDIsConnectedIsDisabledByLOGICSIGNAME

1450.6 EnvironmentCTLModeCTLMODE_NAME CTLModeFamilyNAMEUser USER-DEFINED VenderNAMEIsConnectedIsGatedByLOGICSIGNAME ExternalConnectToSymbolicSYMBOLIC_NAME

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Solution

Named Block CTLModeDomainReferencesCORE_INSTANCE_NAMEFocus CoreInstanceCORE_INSTANCE_NAME IsConnectedIsDisabledByLOGICSIGNAME CTLModeInternalElectricalProperty ELECTORICAL_PROPERTY_IDSignals

STIL

STILIEEE1450.0IEEE1450.11450.21450.3 STIL

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Information

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STILUsageGuide1450.6Rev1.00JP.xls