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Microcontrollers and the PIC

ECE Senior Design 20 Sept. 2011

Popular Microcontrollers

· · · · · · · · PIC ­ Microchip (8-32bit) AVR ­ Atmel (8bit) ARM ­ ARM Limited (32 bit) 8051 ­ Intel then Everyone (8-bit) 68HCSxx ­ Motorola / freescale MSP430 ­ TI (low power 16-bit) PSoC ­ Cypress (M8C, 8051,ARM) Nios / MicroBlaze ­ Altera / Xilinx

Microcontroller Application Requirements

· Microcontroller and Support Circuitry

· Power Supply · Application Software · User Input/Output and Device Interfaces

Features found in Microcontrollers

· · · · · · · · · · · · · · Central Processor Reset Control (Power-on, Brown out, Watchdog) Internal Oscillators and PLLs Program Memory (Factory Mask, OTP, EPROM, Flash) RAM Memory EEPROM Memory (User Configuration) GPIO Pins Timers Interrupts (Internal, External) Parallel Bus Interfaces Serial Interfaces (UART, I2C, SPI) Analog input and output (A to D, D to A, PWM, Comp, Cap Sense) Power Management In-Circuit Programming and Debug (self reprogramming)

Harvard vs. Von Neumann

Harvard Architecture

Harvard architecture

· Separate busses for program memory and data memory · Improved operating bandwidth · Allows for different bus widths · Used in many microcontrollers

Program Memory

14-bit Bus

CPU

8-bit Bus

Data Memory

Von Neumann Architecture

Von Neumann architecture

· Program and data stored in same memory · Used in many microprocessors

8-bit Bus

CPU

Program & Data Memory

RISC vs. CISC

RISC ­ Reduced Instruction Set Computer

· Emphasis on Software · Most instructions execute in a single clock cycle · Larger code sizes

CISC ­ Complex Instruction Set Computer

· Emphasis on Hardware · Instructions require multiple clock cycles · Smaller code size

What the does PIC stand for anyway?

PIC ­ "Peripheral Interface Controller"

The original PIC was designed to be a Peripheral Interface Controller for 6502 microcontroller from Rockwell late 70's.

Why did we choose Microchip PIC Family of Microcontrollers?

· Free development software MPLAB IDE (Includes a Simulator) · Low cost development hardware

· Devices are easy to obtain through distributors and can be sampled

· A wide range of devices are available with varying feature sets · Microchip is in continuous development of new PIC devices · Has a large Internet based development community · Wide acceptance in industry over 1.8 Billion units shipped

Enhanced Midrange PIC Busses (PIC12F1822)

15-bit Program Address bus:

15 Program Address Program Memory

capable of addressing 32k of program memory (PIC12F1822 has 2k of program memory)

14 Instruction CPU 8 Register Address Data Memory and Special Function Registers

14-bit Instruction bus:

contains the opcode and the operands

8-bit Register Address:

PIC12F683 128 Bytes of SRAM 256 Bytes EEPROM

8 Data

8-bit Data bus:

read and write registers

Datasheet Feature Page 12F1822

· Datasheet PIC12F1822

· Processor Structure of the PIC12F1822 · Device Pins for the PIC12F1822

Microcontroller Block Diagram

I/0 Pins

· Up to 6 GPIO Pins on PIC12F1822 (1 input only)

· The Pin Direction is Set with the TRISA Register

· Reading and Writing to the Port is handled in the PORTA LATA Registers

RA0 AN0 DACOUT CPS0 C1IN+ P1B TX SDO ICSPDAT RA1 AN1 VREF CPS1 C1IN0SRI RX SCL ICSPCLK RA2 AN2 CPS2 C1OUT T0CLKI CCP1 INT IOC WPU RA3 T1G nSS IOC nMCLR VPP RA4 AN3 CPS3 C1IN1T1OSO P1B CK SDO IOC RA5 SRNQ T1CLKI CCP1 RX IOC WPU CLKIN

Generic Port Structure

TRISIA Register

LATA Register

PORTA Register

Lighting an LED

Program Memory Map and Stack

·

·

Reset Vector - 0000h

Interrupt Vector - 0004h

·

·

Program Memory - 2048

Stack Depth - 16

Data Memory

The "W" Register (working register)

movf addwf reg1, w reg2, w ; Move a file registers contents into the W register ; Place result in W register

Program Address 13 Program Counter Program Memory

14 Instruction Instruction Register File Registers Data Bus 8

Direct Addr. 7

Instruction Decode and Control ALU 8 W Register

The Status Register

Program Address 13 Program Counter Program Memory 14 Instruction Instruction Register File Registers Data Bus 8

Direct Addr. 7

Instruction Decode and Control

Status Register result 3

ALU 8 W Register

The Status bits

· Arithmetic Status of the ALU · Reset Status WDT and PD · Bank Select bit for Data Memory and SFR

Pipelining of Instructions

· Most instructions Execute in a single Processor Cycle · A Processor Cycle is 4 Clock Cycles · Using a 4MHz oscillator each processor cycle is 1MHz · This results in a 1us execution time

Non-Sequential Address Read

· Exception to the one processor cycle per instruction is for Branching operations

· The Pipeline will be broken on a non-sequential address read · Branching instructions require two processor cycles to execute

Instruction Pipelining

Pre-Fetched Instruction

Executing Instruction

movlw 0x05

Instruction Cycles

Example Program

1 2 3 4 MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2

T0 Fetch

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Instruction Pipelining

Pre-Fetched Instruction

Executing Instruction

movwf REG1

movlw 0x05

Instruction Cycles

Example Program

1 2 3 4 MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2

T0 Fetch

T1 Execute Fetch

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Instruction Pipelining

Pre-Fetched Instruction

Executing Instruction

call SUB1

movwf REG1

Instruction Cycles

Example Program

1 2 3 4 MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2

T0 Fetch

T1 Execute Fetch

T2

Time to execute normal instruction

Execute Fetch

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Instruction Pipelining

Pre-Fetched Instruction

Executing Instruction

addwf REG2

call SUB1

Instruction Cycles

Example Program

1 2 3 4 MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2

T0 Fetch

T1 Execute Fetch

T2

T3

Execute Fetch Execute Fetch

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Instruction Pipelining

Pre-Fetched Instruction

Executing Instruction

movf PORTB,w

call SUB1

Instruction Cycles

Example Program

1 2 3 4 MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2

T0 Fetch

T1 Execute Fetch

T2

T3

T4

Execute Fetch Execute Fetch Flush

Time to execute call instruction includes pipeline flush

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch

Instruction Pipelining

Pre-Fetched Instruction

Executing Instruction

return

movf PORTB,w

Instruction Cycles

Example Program

1 2 3 4 MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2

T0 Fetch

T1 Execute Fetch

T2

T3

T4

T5

Execute Fetch Execute Fetch Flush

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch

Execute Fetch

Instruction Pipelining

Pre-Fetched Instruction

Executing Instruction

movf PORTC,w

return

Instruction Cycles

Example Program

1 2 3 4 MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2

T0 Fetch

T1 Execute Fetch

T2

T3

T4

T5

T6

Execute Fetch Execute Fetch Flush

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch

Execute Fetch Execute Fetch

Instruction Pipelining

Pre-Fetched Instruction

Executing Instruction

addwf REG2

return

Instruction Cycles

Example Program

1 2 3 4 MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2

T0 Fetch

T1 Execute Fetch

T2

T3

T4

T5

T6

T7

Execute Fetch Execute Fetch Flush Fetch

51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return

Fetch

Execute Fetch Execute Fetch Flush

Information

Microcontrollers and the PIC

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