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Static Timing Analysis Formal Verification Synopsys PrimeTime Formality TclTool Command Language Tcl

PrimeTime Formality Tcl

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1.1 1.2 PrimeTime 2.1 PrimeTime 2.2 PrimeTime 2.3 2.4 PrimeTime Tcl pt_shell 3.1 Tcl 3.2 3.3 3.4 PrimeTime 3.4.1 3.4.2 PrimeTime 3.4.3 collection 3.5 3.6 4.1 4.1.1 Stamp Model 4.1.2 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.7 5.1 5.2 5.3 5.4 path timing report 5.5 5.6 Formality

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6.1 6.2 6.3 6.4 7.1 7.2

7.3 7.4 7.5 7.6 7.7 8.1 8.2 8.3

Formality Formality Formality ....................................(27) fm_shell 7.2.1 Reference Design Implementation Design 7.2.2 container Reference Design Implementation Design Debug ....................................(32) 8.3.1 8.3.2 8.3.3 Debug 8.3.4

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VLSI ULSI IC EDA Synopsys Aart de Geus IC IC IC IP IC

§1.1

Dynamic Timing SimulationStatic Timing Ana -lysis (critical pat -hs) IC

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Time-to-market

§1.2

IC Synopsys Formality Verp -lex Conformal LEC

Synopsys PrimeTime Formality PrimeTime Tcl PrimeTime Formality Debug

PrimeTime

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PrimeTime

PrimeTime Synopsys ASICPrimeTime Synopsys EDA PrimeTime PrimeTime

§2.1

PrimeTime

PrimeTime ² (setup and hold checks) ² ² (clock-gating checks) ² recovery and removal checks ² unclocked registers ² unconstrained timing endpoints ² master-slave clock separation ² multiple clocked registers ² combinational feedback loops ² PrimeTime 1PrimeTime 2PrimeTime SOCsystem-on-chip

PrimeTime

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PrimeTime

§2.2

PrimeTime

PrimeTime 1 ² ² ² ² ² 2 (timing assertions/constraints) (uncertainty)(latency) 3(timing exceptions) ² multicycle paths ² false paths ² (path segmentation) arcs 4 constra -int reports path timing reports PrimeTime

PrimeTime

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§2.3

AMD 2910 2-2

Figure2-2 AMD 2910

§2.4

PrimeTime

PrimeTime GUIGraphical User Interf -ace Tcl pt_shell PrimeTime pt_shell quitexit ^d GUI pt_shell pt_ shell

Tcl pt_shell

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Tcl pt_shell

Tcl Tool Command Language PrimeTime Tcl Tcl PrimeTime Tcl pt_shell synopsys EDA Tcl 2-1 Design Compiler Tcl PrimeTime Design Compiler

§3.1

Tcl

Tcl 1set set clock_period 10

2$ echo $clock_period

3unset 4printvar echo $

PrimeTime set sh_enable_page_mode true PrimeTime .synopsys_pt.setup sh_enable_page_mode

Tcl pt_shell

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§3.2

PrimtTime ([]) 1 [ 2 [ 3] ] 3 2

§3.3

Tcl 1 2 set mydelay 10 echo "The value of mydelay is $mydelay" The value of mydelay is 10 echo {The value of mydelay is $mydelay} The value of mydelay is $mydelay expr

§3.4 §3.4.1

PrimeTime

IC "(object)" DesignCellPortPinNetClock

Tcl pt_shell

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Design Synopsys design Cell Synopsys cell instance design Port inputoutput design I/O Pin cell inputoutput I/O Referencecell instance Net ports pins pins pins Clock port pin VHDL Figure3-1

§3.4.2

PrimeTime

PrimeTime collection get_objtype objtype "help get_*" Design Compiler find collection memory query_objects collection set data_ports [get_ports D[*] ] query_objects $data_ports all_objtype collection all_clocksall_inputsall_outputsall_instancesall_registers

Tcl pt_shell

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all_connected all_connected pin port net CLOCK query_objects [all_connected [get_nets CLOCK]]

§3.4.3

collection

1foreach_in_collection collection foreach_in_collection variable collection { body } Y_OUTPUT foreach_in_collection outpin [get_ports Y_OUTPUT[*]] { ? set maxcap [get_attribute $outpin wire_capacitance_max] ? set pinnname [get_attribute $outpin full_name] ? echo "Max capacitance of port $pinname is $maxcap" ? } get_ports collectionoutpinmaxcap pinname collection echo foreach_in_collection collection Tcl foreach 2 collection add_to_collection collection object remove_from_collection collection object object collection 3collection

Tcl pt_shell

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collection filter_collection collection collection collection -filter filter ==,!=,>,<,>=,<=,=~ ND2,ND21,ND3,ND4p cells query [get_cells * -hier -filter "ref_name =~ ND*"] PrimeTime query query_objects

§3.5

(arritubes) PrimeTime Design Compiler (net ) list_arritubes get_arritube report_arritube define_user_arritube set_user_arritube remove_user_arritube AM2910 get_attribute [get_designs AM2910] voltage_max

§3.6

Unix help man clock

Tcl pt_shell

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help *clock help -verbose

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² ² ² (wire load model??) ² (??timing assertions) ²

§4.1 §4.1.1

Stamp Model

Stamp model DSP(digital signal processing) RAM Stamp model pin-to-pin arcs(??)pin Stamp model 1.mod pin-to-pin arc 2.data .mod arc AM2910 Y 2-2 Stamp model compile_stamp_model -model_file Y.mod -data_file Y.data -output Y Y.mod Y.data .db Y_lib.db Y.db Y_lib.db core Y.db Y_lib.db core Y.db Y_lib.db (link

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_path)

§4.1.2

?? HDL stamp model pt_shell Stamp mo -del AM2910 STACK source -echo stack.qtm.pt report_qtm_model; save_qtm_model -output STACK -format db stack.qtm.pt pt_shell source [1] save_qtm_model .db PrimeTime .db STACK_lib.db STACK .db §4.1

§4.2

PrimeTime search_path link_path set set search_path "." set link_path "* pt_lib.db STACK_lib.db Y_lib.db" AMD 2910 PrimeTime search _path "."

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link_path "*" PrimeTime pt_lib.dbSTACK_lib.dbY_lib.db

§4.3

PrimeTime

PrimeTime Synopsys .db Verilog EDIF Electronic Design Interchange Format VHDL

read_db read_verilog

read_edif read_vhdl

Synopsys AM2910.db read_db AM2910.db

§4.4

PrimeTime link_path CONTROLREGCNTSTACKUPCY link_path pt_lib.db STACK_lib.dbY_lib.db

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link_design AM2910 1 Memory PrimeTime PrimeTime search_path 2 link_design PrimeTime PrimeTime 3 link_create_black_boxes true PrimeTime reference black box link_create_black_boxes false list_design report_cell memory warning write_script .pt

§4.5

set_operating_conditions -library pt_lib -min BCCOM -max WCCOM set_wire_load_mode top set_wire_load_model -library pt_lib -name 05x05 -min set_wire_load_model -library pt_lib -name 20x20 -max PrimeTime setup timing report hold timing reports

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set_min_library list_libraries "report_lib ".

§4.6 §4.6.1

create_clock -period 30 [get_ports CLOCK] set clock [get_clock CLOCK] set_clock_uncertainty 0.5 $clock set_clock_latency -min 3.5 $clock set_clock_latency -max 5.5 $clock set_clock_transition -min 0.25 $clock set_clock_transition -max 0.3 $clock back-annotated??() uncertaintytransition set_propagated_clock clock_object_list §4.6.2 (clock-gating checks)

set_clock_gating_check -setup 0.5 -hold 0.1 $clock set_min_pulse_width 2.0 $clock back-annotated PrimeTime SDF(standard delay format) §4.6.3

report_design report_reference

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stamp

§4.7

check_timing errors warnings check_timing error warning "check_timing -help" AM2910 check_timing warnings

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AM2910 §5.1

set_input_delay 0.0 [all_inputs] -clock $clock set_output_delay 2.0 [get_port INTERRUPT_DRIVER_ENABLE] -clock $clock set_output_delay 1.25 [get_port MAPPING_ROM_ENABLE] -clock $clock set_output_delay 0.5 [get_port OVERFLOW] -clock $clock set_output_delay 1.0 [get_port PIPELINE_ENABLE] -clock $clock set_output_delay 1.0 [get_port Y_OUTPUT] -clock $clock set_driving_cell -lib_cell IV -library pt_lib [all_inputs] set_capacitance 0.5 [all_outputs] clock set clock [get_clock CLOCK] check_timing AM2910 check_timing warnings

§5.2

write_script

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1Design Compiler dcsh .dcsh 2Design Compiler dctcl .tcl 3PrimeTime .pt write_script -format dctc1 -output AM2910.tc1 write_script -format dcsh -output AM2910.dcsh write_script -format ptsh -output AM2910.pt PrimeTime Design Compiler Design compiler PrimeTime

Clocks Timing Exceptions Delays Net and Port Design Environment Design Rules

nameswaveformslatencyuncertainty false paths multicycle paths path groups minimun and maximum delays input and output delays timing checks all delay annotations capacitanceresistancefanout wire load model operation condition drive driving celltransition minimum and maximum capacitancefanout transition

5-1 source -echo

§5.3

report_constraint constraint report timing violations constrains violations

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constraint report ² min and max delay ² min clock pulse width ² min period ² ??recovery and removal on registers ² clock-gating setup and hold ² min and max capacitance ² min and max transition ² min and max fanout -verbose report -all_violators report

§5.4

path timing report

report_timing timing report report path group -delay min report_timing -help

§5.5

??(timing exceptions)

Timing exceptions (false paths)(multic -ycle paths) arcs?? timing exceptions PrimeTime

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1 updatePrimeTime timing exceptions report_exceptions 2-ignored exceptions PrimeTime exceptions AM2910 timing exceptions set_false_path -from U3/OUTPUT_reg[*]/CP -to U2/OUTPUT_reg[*]/D set_multicycle_path -setup 2 -from INSTRUCTION[*] -to U2/OUTPUT_reg[*] set_multicycle_path -hold 1 -from INSTRUCTION[*] -to U2/OUTPUT_reg[*] update_timing report_exceptions -ignored exceptions timing exceptions

§5.6

timing exceptions constraint report timing report report_constraint -all_violators report_timing exceptions viloators slack PrimeTime AM2910 pt_shell [2]

Formality

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Formality

Formal Verification Synopsys Formality

§6.1

Formality

test bench Formality RTL Formality ² ² ² RTL-to-RTLRTL-to-gategate-to-gate ² ² VHDLVerilogSynopsys .db EDIF ²

Formality

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² Design Compiler ² PrimeTime GUI fm_shell

§6.2

Formality

EDA Formality Formality Formaliyt "" ASIC Formality

Formality

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Figure6-1 ASIC

§6.3

Formality

Formality 6-2 1 2

Formality

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Formality 3 Formality 4

Figure6-2

Formality

§6.4

Formality

Formality

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container

Ref Impl Design en

No

Debug

"" fm_shell GUI

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Formality §7.1 fm_shell

PrimeTime Formality Tcl help man -help UNIX fm_shell ls cat sh cat

§7.2 §7.2.1

Reference Design Implementation Design

Synopsys Reference Desi -gn Implementation DesignReference Design Implementation Design dbs netlists lib libdbsnetlists set search_path ". ./lib ./dbs ./netlists" §7.2.2 container

container Formality "" container Reference Design Implementation Design container container

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Figure7-1 container

§7.3

Formality gtech.db./lib cba_core.db read_db cba_core.db report_libraries -short report_libraries report_li -s

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§7.4

Reference Design

1 container container create_container ref "ref" container 2 Formality ² Synopsys .db ² Verilog ² VHDl ² EDIF Reference synth.db mR4000.db Implemen -tation clk_insert1.v verilog synth.db container read_db synth.db GUI Formality container cba_core gtech WORK Reference Design mR4000 3 Reference Design set_reference_design ref:/WORK/mR4000 (full designID) container // Formality ref Reference Design 4 Reference Design Formality

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link $ref

§7.5

Implementation Design

Reference Design 1 impl container clk_insert1.v read_verilog -c impl -netlist clk_insert1.v -netlist RTL Formality 2 Implementation Design set_implementation_design impl:/WORK/mR4000 3 link $impl 4 test_se 0 current_design §impl set_constant test_se 0 Implementa -tion Design Reference Design test_se 0

§7.6

Debug GUI fm_shell .fss save_session -replace -full fm_shell_session exit GUI restore_session fm_shell_session.fss

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§7.7

verify Formality ref impl verification failed 3 Failing compare points Formality debug

Debug

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Debug

Refe -rence Desing Implementation Design fm_shell GUI De -bug

§8.1

report_failing_points Instruction_reg[10] Instruction_reg[16] state_reg[9]

§8.2

6-2 Formality "" "" Implementation Reference Design Formality ""Formality net report diagnose report_error_candidates

Debug

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Formality net cell net 100% CLK 100% debug instruction_reg[10] diagnose $impl/Instruction_reg[10] report_error_candidates

Error candidates: % type Name ----------100.0 net Clk 100.0 net n1023 100.0 net n42

Debug

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Clkn1023n42 net Instrution_reg [10] Clk

§8.3 §8.3.1

81 "Logic Cone"

Figure8-1

§8.3.2

8.1 8.2 fm_shell GUI GUI Report Failing Points Report Edit Show Size fm_

Debug

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shell report_failing_points impl:/WORK/mR4000/Instruction_reg[10] view logic cone Reference Design Implementation Desi -gn

Instruction

_reg[10]

Clk Figure7-3

n1023

n42

8.2

0 <=24 2549

Debug

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5089 90100 Instruction_reg[10] Clk Clkn1023n42 net net 8.2

§8.3.3

Debug

instruction_reg[10] CLK net Isolate Subcone CLK Reference Design Implementation Design Clk Implementation buffer

Figure7-4

Debug

Debug

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§8.3.4

Formality View menu Apply First Pattern debug

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