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TSV Interposer: The Most Cost-Effective Integrator for 3D IC Integration

John H. Lau Electronics & Optoelectronics Research Laboratories Industrial Technology Research Institute (ITRI) Chutung, Hsinchu, Taiwan 310, R.O.C. 886-3591-3390, [email protected]

ASME InterPACK2011-52189 (Lau)

Objectives

To investigate the significant roles of Cu-filled TSV passive interposers for 3D IC integration. Emphasis is placed on the roles they play as:

(1) (2) (3) (4) Substrates Reliability buffers Carriers Thermal management tools

It is shown that the Cu-filled TSV passive interposers are the most cost-effective integrator for 3D IC integration system-inpackage (SiP).

ASME InterPACK2011-52189 (Lau)

Contents

(1) INTRODUCTION (2) 3D IC INTEGRATION (3) 3D IC MEMORY-CHIPS STACKING (4) 3D IC INTEGRATION: ACTIVE INTERPOSERS (5) 3D IC INTEGRATION: PASSIVE INTERPOSERS

A. Passive Interposers as Substrates/Carriers (2.5D IC Integration) B. Cu-Filled TSV Passive Interposers as Reliability Buffers for Moore's Law chips C. Passive Interposers as the Integrators for Moore's Law Chips (3D IC Integration) D. Passive Interposers used as Effective Thermal Management tools and Low-Cost Integrators for Moore's Law chips (3D IC Integration)

(6) SUMMARY AND RECOMMENDATIONS (7) ACKNOWLEDEGEMENTS

ASME InterPACK2011-52189 (Lau)

3D Integration Technologies

3D IC Packaging 3D IC Integration 3D Si Integration

Full swing production for memories.

Mass Production

Commercialization

Die Stacking with wire bonds

Testing and yield challenges give way for package stacking

Maturity

Applied R&D Basic/A pplied R&D

Package on Package Stacking (PoP)

Active applied R&D is undertaken by Research Institutes. System level challenges are key. In the phase of industrialization.

Still in upstream research, technological challenges such as yield & device architecture are key issues.

C2C, C2W, W2W Stacking W2W Stacking

Technology

Lau

4 Lau, Lee, Prem, Yu, 3D MEMS Packaging, McGraw-Hill, 2009

Evolution of TSV 3D integration

The origin of 3D Integration (1980)

3D integration was trigged by the silicon-on-insulator (SOI) technology 30 years ago, when people thought Moore's law could be hitting the wall by the 1990s.

The invention of TSV (1958)

Shockley's invention was not meant for 3D integration

3D Si Integration (was favored in 1980s)

Stacking up wafers with TSVs for electrical feed through. Bumpless!

3D IC Integration (was rejected in 1980s)

Stacking up the chips with TSVs and solder bumps

A boost (1985) by Richard Feynman

Go 3D instead of all on a surface of a chip!

3D IC Integration with microbumps and thin chips (has been favored since 2000s)

Because of the disappointment of 3D Si Integration, and using thin chips and microbumps

Long way to go!

Need Ecosystem, EDA, Technology

No sight in Volume Production in the next 10 years

Memorychips Stacking

Active Interposers (Memory/Logic + CPU/Logic)

Need Ecosystem, EDA, and Business models

Passive Interposers (2.5D & 3D)

Will be used the most in the next 10 years

2.5D IC Integration with Passive Interposer Micro Bump TSV/RDL/IPD Passive Interposer 3D IC Integration with Passive Interposer TSV

Cost issues and The right way to go and compete with Competing Moore's law. Hopefully in production (at technology least for memory-chips stacking) by 2020!

Thin Wafers TSV

560m

[email protected] thick 2Gb Chips (16Gb)

W2W (SiO2-SiO2) bonding

Memory

Micro bump TSV

Micro Bump

TSV

CPU/ Logic

TSV/RDL/IPD Passive Interposer TSV

Bumpless

Cu Cu

ASME InterPACK2011-52189 (Lau)

Micro bump

Xilinx's 4 FPGAs on a Passive TSV Interposer

ASME InterPACK2011-52189 (Lau)

Xilinx's FPGA Wide I/O Interface

ASME InterPACK2011-52189 (Lau)

ITRI Phase-I 3D IC Integration Test Vehicle

Not-to-scale

TSV is optional Micro bumps Thermal TSV:15m

Electrical

Stress sensor

Mechanical

TSV: 10m

100m

TSV:15m

TSV:10m

50m IPD

100m 80m

TSV/RDL/IPD Interposer

Ordinary bumps

RDL RDL

TSV:15m

`

`

1mm 350m

Organic (BT) substrate

I/O:400 ball array, pitch:450m Solder balls

1.2mm

I/O:400 ball array, pitch:1mm

ASME InterPACK2011-52189 (Lau)

PCB PCB

ITRI Phase-I 3D IC Integration SiP 8

ITRI Phase-I 3D IC Integration Test Vehicle

ITRI's Phase-I 3D IC integration SiP

Mechanical Chip 4-chip stacked

Thermal chip

TSV interposer

BT-substrate

ASME InterPACK2011-52189 (Lau)

Semi-Embedded TSV Interposer with Stress Relief Gap

Moore's Law chips

ASME InterPACK2011-52189 (Lau)

10

Cu-filled TSV can be a Stress Relief (Reliability) Buffer for the Cu-low-k Pads of a Moore's law Chip

TCE = 2.5x10-6/oC

Mirco solder joint TSV Moore's law Chip BT-Substrate

Cu-filled TSV interposer

TCE = 8-10x10-6/oC Special

Underfill Ordinary Underfill

250MPa

250 200

(a) Mirco solder joint

PCB

Ordinary solder joint Special Underfill

150 100

125MPa

42MPa

Moore's law Chip BT-Substrate

50 0

Conventional FCBGA with FCBGA with interposer

FCBGA interposer and 3 Category 1 Category 2 Categoryunderfill

(b)

PCB

TCE = 15x10-6/oC

Lau

·Selcanayagam and Lau, et al., IEEE/ECTC08, Also, IEEE Transactions 2009. ·Zhang, Lau, et al., IEEE/ECTC 2009, Also, IEEE Transactions 2010 ·Lau and Zhang, ASME Paper: InterPACK2011-52205

IME TSV Interposers (Carriers)

Evolution of TSV 3D integration

The origin of 3D Integration (1980)

3D integration was trigged by the silicon-on-insulator (SOI) technology 30 years ago, when people thought Moore's law could be hitting the wall by the 1990s.

The invention of TSV (1958)

Shockley's invention was not meant for 3D integration

3D Si Integration (was favored in 1980s)

Stacking up wafers with TSVs for electrical feed through. Bumpless!

3D IC Integration (was rejected in 1980s)

Stacking up the chips with TSVs and solder bumps

A boost (1985) by Richard Feynman

Go 3D instead of all on a surface of a chip!

3D IC Integration with microbumps and thin chips (has been favored since 2000s)

Because of the disappointment of 3D Si Integration, and using thin chips and microbumps

Long way to go!

Need Ecosystem, EDA, Technology

No sight in Volume Production in the next 10 years

Memorychips Stacking

Active Interposers (Memory/Logic + CPU/Logic)

Need Ecosystem, EDA, and Business models

Passive Interposers (2.5D & 3D)

Will be used the most in the next 10 years

2.5D IC Integration with Passive Interposer Micro Bump

Cost issues and The right way to go and compete with Competing Moore's law. Hopefully in production (at technology least for memory-chips stacking) by 2020!

Thin Wafers TSV

560m

[email protected] thick 2Gb Chips (16Gb)

TSV/RDL/IPD Passive Interposer 3D IC Integration with Passive Interposer

TSV

W2W (SiO2-SiO2) bonding

Memory

Micro bump TSV

Micro Bump

TSV

CPU/ Logic

TSV/RDL/IPD Passive Interposer TSV

Bumpless

Cu Cu

Micro bump

ASME InterPACK2011-52189 (Lau)

TSV passive interposer supporting high-power chips (e.g., microprocessor and logic) on its top side and low-power chips (e.g., memory) on its bottom side

TIM Microbumps Heat Spreader + Sink (if needed) Adhesive TSV Interposer with RDL & IPD Stiffener ring Simple organic substrate Microprocessor/ ASIC

PCB

Ordinary solder bumps

Memory

Solder balls

Special underfills are needed between the Cu -filled interposer and all the chips. Ordinary underfills are needed between the interposer and the organic substrate.

ASME InterPACK2011-52189 (Lau)

TSV interposer supporting high-power chips on its top side and low-power chips on its bottom side with a cavity.

TIM Microbumps Adhesive Microprocessor/ ASIC Heat Spreader + Sink (if needed) Stiffener ring

TSV /RDL/IPD interposer with a cavity

Simple organic substrate

PCB

Ordinary solder bumps

Solder balls

Special underfills are needed between the Cu-filled interposer and all the chips. Ordinary underfills are needed between the interposer and the organic substrate.

ASME InterPACK2011-52189 (Lau)

Passive TSV interposer with RDL and IPD supporting highpower chips on its top-side and low-power chips at its bottom-side. The organic substrate is with a cavity

ASME InterPACK2011-52189 (Lau)

Dimensions of the passive TSV interposer with 4 highpower flip chips on its top and 16 low-power flip chips at its bottom (the gist of the 3D IC integration SiP.)

TSV Interposer 10mm TSV Interposer 5mm 5mm 35mm High power chip 35mm

The 4 high power chips are the same and uniformly distributed over the TSV interposer.

10mm 35mm

TSV Interposer High Power Chip 200µm

200µm

Low power chip 35mm

The 16 low power chips are the same and uniformly distributed over the TSV interposer.

Low Power Chip

200µm

60mm Solder bump

850µm 150µm ......... High Power Chip .........

There are 66 bumps on each side. Totally 260 bumps. There are 11 bumps on each side. Totally 40 bumps.

20µm 200µm

400µm 60µm Solder Bump 60µm Solder bump Cu TSV

Low power chip

ASME Paper no. IMECE2010-40975 Lau

.........

.........

TSV Interposer

There are 1600 TSVs in the interposer. So there are 400 TSVs in the quarter model.

Top View

Bottom View

Side View

Thermal Management System of 3D IC Integration Supported by a TSV Interposer

Thermal Interface Material Stiffener Heat Spreader Heat Sink Micro Bumps Adhesive

High-power Chip

Low-power Chip

High-power Chip

Heat Slug PCB Organic Substrate Ordinary Solder Bumps

PCB TSV Interposer with RDL & IPD Solder Balls

Special underful between the TSV interposer and the high- and low-power flip chips. Ordinary underful between the TSV interposer and the organic substrate.

ASME InterPACK2011-52189 (Lau)

Low-Cost TSH (Through-Si Holes) Interposer for 3D IC Integration

Moore's Law chip Through-Si Holes (TSH) Interposer

RDL RDL RDL

Non-metallization holes on the TSH interposer

Solder joints

RDL RDL RDL

Solder bump

Cu/Au Stud, wire, or pillow

Solder bump

Organic Substrate/PCB

1. Underfills are optional between the Moore's law chips and the interpose when they are subjected to thermal loading! However, for shock and vibration loads, and depending on chip size, underfills may be needed! 2. Underfills between the TSH and the organic substrate/PCB are necessary!

ASME InterPACK2011-52189 (Lau)

Embedded 3D IC Integration with Optical Devices

Heat Slug

Serializer or deserializer VCSEL or PD TSV

TIM

Solder Ball

Driver chip or TIA

TIM

Cu Heat Spreader

Heat Slug

Polymer Waveguide

Heat Slug

Mirror

Optical layer support (film)

Mirror

Laminated Substrate/Board

Special Underfills (e.g., Transparent) Buried via (filled or unfilled) for electrical interconnects Special Underfills (e.g., Transparent)

20

ASME InterPACK2011-52189 (Lau)

VCSEL = Vertical Cavity Surface Emitted Laser (transparent); PD = Photo Diode Detector (transparent); TIA = Trans-Impedance Amplifier

3D IC integration SiP consists of a series of TSV/RDL/IPD interposers with embedded fluidic channels to support multiple Moore's law chips without any TSVs

TSV/RDL/IPD Interposer with embedded fluidic channels to support multiple Moore's law chips without any TSVs Substrate

PCB

ASME InterPACK2011-52189 (Lau)

TSV/RDL/IPD interposer with embedded fluidic channels supporting all kinds of chips on its top and bottom sides

TSV/RDL/IPD interposer with embedded fluidic channels to support Moore's law chips with no TSVs

IPD RDL Moore's law chips

TSVs Micro-channels Microbumps Solder bumps

ASME InterPACK2011-52189 (Lau)

Interposer (carrier) with TSVs for electrical feed through and fluidic microchannels for thermal management

TSV

Fluidic inlet Fluidic outlet

TSV

Fluidic channel

Fluidic inlet

Fluidic outlet

ASME InterPACK2011-52189 (Lau)

Fluidic Channel Top-side Bottom-side

Fabricated TSV and embedded fluidic microchannel carrier (interposer). The TSV, sealing ring for TSVs, sealing ring for micochannels. Au20Sn solder bumps and Ti/Cu/Ni/Au UBMs

ASME InterPACK2011-52189 (Lau)

For channel height = 700m, 100 [email protected], 4 [email protected], flow rate = 0.54L/min. Top Left (interposer and LEDs temperature distribution); Top Right (LEDs temperature distribution); Bottom Left (ASICs temperature distribution); Bottom Right (flow path in channel)

Interposer and LEDs temperature distribution

LEDs temperature distribution

ASICs temperature distribution

Flow path in channel

ASME InterPACK2011-52189 (Lau)

3D Integration Roadmap

3D IC integration (TSV interposer with embedded fluidic microchannels)

Volume Production

3D IC integration (TSV interposer with chips on both sides)

2.5D IC integration (TSV interposer with chips on top-side)

Memory/Logic + CPU/Logic with TSV

MEMS on ASIC with TSV CIS with TSV and DSP

Multi-LEDs on chip with TSV

Wide I/Os DRAM

CIS with TSV (2.5D)

2008

2010

2012

2014

2016

2018

ASME InterPACK2011-52189 (Lau)

Memory stacking

2020

Memory/Logic + CPU/Logic

SUMMARY AND RECOMMENDATIONS

The roles played by the Cu-filled TSV passive interposers for 3D IC integration have been investigated in this study. It has been demonstrated that the Cu-filled TSV passive interposers are cost-effective 2.5D IC integration substrates and carriers, as well as 3D IC integrator, thermal management tools, and reliability buffers. Some important results and recommendations are summarized in the following. 1. In the next 10 years, the TSVs will be fabricated the most (by the number of vias) for Cu-filled passive interposers. 2. Passive interposer is the most cost-effective 3D IC integrator. It is not only for substrates, carriers, but also thermal managements. Let the passive interposer be the workhorse of 3D IC integration SiPs! 3. Besides it is the most cost-effective 3D IC integrator, the Cu-filled passive interposer acts like a stress relief (reliability) buffer, which reduces the stress acting on the Cu-low-k pads on Moore's law chips. This advantage becomes more pronounced when the feature size is getting smaller and so does the allowable stress of the chip pads. 4. A few true cost-effective 3D IC integration SiPs with Cu-filled TSV passive interposers have been proposed. 5. 3D Si integration is the right way to go and compete with Moore's law. Hopefully, by 2020 at least the memory chips stacking could be manufactured at lower costs and higher throughputs by using the 3D Si integration technology. The industry should stride to make this happens!

Acknowledgements

The author would like to express thanks to the financial support by Ministry of Economic Affairs (MOEA), Taiwan, R.O.C., and the strong support by the VP and Director of Electronics & Optoelectronics Research Lab, Dr. Ian Chan of ITRI.

Thank you very much for your attention!

Lau 29

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