Read DDR3 SODIMM Spec text version

DDR3 Unbuffered SODIMM Spec Sheet

Features

· DDR3 functionality and operations supported as defined in the component data sheet ·204pin, small-outline dual in-line memory module (SODIMM) · Fast data transfer rates: PC3-8500, PC3-10600 · 1GB(128 Meg x 8), 2GB (256 Meg x 64), 4GB (512Meg x 64) · V DD = V DDQ = 1.5V ±0.075V · V DDSPD = 3.0V to 3.6V · Reset pin for improved system stability · Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals · Single or Dual rank · Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) · Adjustable data-output drive strength · Serial presence-detect (SPD) EEPROM · Gold edge contacts · Pb-free · Fly-by topology · Terminated control, command, and address bus

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Rev 1.1 Nov. 2010

DDR3 Unbuffered SODIMM Spec Sheet

Module Specification

Part Number SP001GBSTU106S01(2) SP001GBSTU133S01(2) SP001GBSTU106T01(2) SP001GBSTU133T01(2) SP001GBSTU106Q01(2) SP001GBSTU133Q01(2) SP002GBSTU106V01(2) SP002GBSTU133V01(2) SP002GBSTU106S01(2) SP002GBSTU133S01(2) SP002GBSTU106T01(2) SP002GBSTU133T01(2) SP004GBSTU106V01(2) SP004GBSTU133V01(2) SP008GBSTU106V21(2) SP008GBSTU133V21(2) Module Density & Configuration 1GB (128Mx64) 128Mx8 1Rank 1GB (128Mx64) 128Mx16 1Rank 1GB (128Mx64) 64Mx16 2Ranks 2GB (256Mx64) 256Mx8 1Rank 2GB (256Mx64) 128Mx8 2Ranks 2GB (256Mx64) 128Mx16 2Ranks 4GB (512Mx64) 256Mx8 2Ranks 4GB x 2 Kit Package 4GB x 2 Kit Package Bandwidth PC3-8500 PC3-10600 PC3-8500 PC3-10600 PC3-8500 PC3-10600 PC3-8500 PC3-10600 PC3-8500 PC3-10600 PC3-8500 PC3-10600 PC3-8500 PC3-10600 PC3-8500 PC3-10600 Data Rate DDR3-1066 DDR3-1333 DDR3-1066 DDR3-1333 DDR3-1066 DDR3-1333 DDR3-1066 DDR3-1333 DDR3-1066 DDR3-1333 DDR3-1066 DDR3-1333 DDR3-1066 DDR3-1333 DDR3-1066 DDR3-1333 Timing (tCL-tRCD-tRP) 7-7-7 9-9-9 7-7-7 9-9-9 7-7-7 9-9-9 7-7-7 9-9-9 7-7-7 9-9-9 7-7-7 9-9-9 7-7-7 9-9-9 7-7-7 9-9-9

Note: This document supports all STU Series DDR3 204Pin SODIMM products. Some item was being EOL in this list, Please contact with our sales Dep.

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Rev 1.1 Nov. 2010

DDR3 Unbuffered SODIMM Spec Sheet

Pin Assignments

204-Pin DDR3 SODIMM Front

Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 Symbol VREFDQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 Pin 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 Symbol DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# Pin 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 Symbol VDD A10 BA0 VDD WE# CAS# VDD A13 S1# VDD NC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS Pin 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 ­ ­ Symbol DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT ­ ­ Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23

204-Pin DDR3 SODIMM Back

Symbol Pin 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 Symbol VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CKE1 VDD NC NC/A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# Pin 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 Symbol VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREFCA SS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS Pin 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 ­ ­ Symbol DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT ­ ­

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DDR3 Unbuffered SODIMM Spec Sheet

Pin Description

Symbol Type Description Address inputs: Provide the row address for ACTIVE commands and the column address and auto precharge bit for READ/WRITE commands to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed. The address inputs also provide the opcode during mode register command set. A0­A13 (128Mx8) A0­A14 (256Mx8). Bank address inputs: BA0, BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0, BA1 define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.

A0­A14

Input

BA0­BA2 CK0, CK0#, CK1, CK1#

Input Input

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates CKE0, CKE1 Input clocking circuitry on the DDR3 SDRAM. Data input mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. DM is sampled on both DM0­DM7 Input edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS7pins. On-die termination: ODT (registered HIGH) enables termination resistance internal to the ODT0 DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS# Input ODT1 and DM. The ODT input will be ignored if disabled via the LOAD MODE command. RAS#, CAS#, Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being Input WE# entered. Reset: RESET# is an active LOW CMOS input referenced to V SS . The RESET# input receiver Input RESET# is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 ×V DD and DC LOW 0.2 (LVCMOS) ×V . DD Chip select: S# enables (registered LOW) and disables (registered HIGH) the command S0#, S1# Input decoder. Presence-detect address inputs: These pins are used to configure the SPD EEPROM SA[2:0] Input address range. Serial clock for presence-detect: SCL is used to synchronize the presence-detect data SCL Input transfer to and from the module. DQ0­DQ63 I/O Data input/output: Bidirectional data bus. DQS0­DQS7 Data strobe: Output with read data, input with write data for source synchronous operation. I/O DQS0#­DQS7# Edge-aligned with read data, center-aligned with write data. Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data SDA I/O into and out of the SPD EEPROM on the module. Power supply: 1.5V ±0.075V. The component V DD and V DDQ are connected to the module V DD Supply V DD . V DDSPD Supply Temperature sensor/SPD EEPROM power supply: +3.0V to +3.6V. V REFCA Supply Reference voltage: Control, command, and address (V DD /2). V REFDQ Supply Reference voltage: DQ, DM (V DD /2). V SS Supply Ground. V TT Supply Termination voltage: Used for control, command, and address (V DD /2). NC ­ No connect: These pins are not connected on the module. NU ­ Not used: These pins are not used in specific module configuration/operations.

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Rev 1.1 Nov. 2010

DDR3 Unbuffered SODIMM Spec Sheet

Simplified Mechanical Drawing(x8 1Rank)

Note: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note: 2. The dimensional diagram is for reference only.

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Rev 1.1 Nov. 2010

DDR3 Unbuffered SODIMM Spec Sheet

Simplified Mechanical Drawing(x16 1Rank)

Note: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note: 2. The dimensional diagram is for reference only.

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Rev 1.1 Nov. 2010

DDR3 Unbuffered SODIMM Spec Sheet

Simplified Mechanical Drawing(x8 2Ranks)

Note 1: All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note 2: The dimensional diagram is for reference only.

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Rev 1.1 Nov. 2010

DDR3 Unbuffered SODIMM Spec Sheet

Simplified Mechanical Drawing(x16 2Ranks)

Note 1: All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. Note 2: The dimensional diagram is for reference only.

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Rev 1.1 Nov. 2010

Information

DDR3 SODIMM Spec

8 pages

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