Read Microsoft Word - Non-conductive Epoxy Filled vias in PCB white paper.doc text version

Non-Conductive Epoxy Filled Vias in PCB's Provides New Product Offerings

David Hoover Sr. Field Applications Engineer Multilayer Technology, Inc. (MULTEK) Abstract


Non-conductive filled-via technology has existed for quite some time in the PCB manufacturing industry. In the past, it has been used mainly to support smaller finepitch enabling technologies (HDI). This paper will discuss past HDI approaches and how the equipment and the process has been highly refined. The filled-via technology can be utilized for some very demanding finepitch technologies and has also found to be suitable to support surface mounted gold to gold contact devices.


In the past, epoxy-filled vias have predominately been used for HDI via-in-pad interconnect strategies. By utilizing the via-in-pad locations as potential solderball or SMT land locations, designers could gain additional rout channels on the outerlayers where normally fine-pitch component density would not allow. (See Illustration 1 below) These fine pitch packages can provide higher functionality along with a higher I/O count. Many of these devices with small component footprints are available in production. It's not uncommon to see pitches down below 1.0 mm (.040") for BGAs and down to .4 mm (.0157") for CSP devices. These components become a large challenge for the designer. Here are a couple of techniques typically done to help provide for additional rout channels out of these devices. You can: 1. 2. 3. Increase the layer count. (until you have solved for all the I/O contained on the device) (Note: This may increase the PCB thickness beyond the mechanical or manufacturable limitations) Use alternative interconnect strategies. (i.e., blind, buried, micro, or sequential lamination vias)

Use a combination of through and/or filled vias. (which keeps the stack-up and manufacturing process more of a standard conventional method.)

Although I'm sure that the designer would pursue option 1 initially, they may find that another option may be required. Option 2 can gain some real estate and provide via-in-pad approaches may not be the best option for yields, lead-times, and costs. For the scope of this paper, we will concentrate strictly on option 3.

Illustration 1

Added Rout Channels on Outerlayer (underneath device)


Non-Conductive Filled Vias are rendered using standard design rules for typical PCB geometries. Many of these are available from your component supplier. By using commonly found design rules and non-conductive filled vias, you can free up more real estate on the PCB surfaces. What's necessary for the fabricator to build this technology is a separate drill file consisting of only the vias to be filled. Keep in mind that there is a cost adder associated with this technology and it's always best to deploy required via fill technologies only when required (i.e., finepitch component areas). This way it also helps keep the cost impact down at a minimum. Extra Cost Considerations · Hole filling - (materials) · Planarization ­ (Mechanical Equipment & Process Time) · Copper Capping (Additional Drilling and Copper Plating) When designing in the particular non-conductive and dense filled vias, you could slightly change the hole size to produce this at CAD file output. On the blueprint it's best to call out that particular hole size to be non-conductive via filled. This way there is a clear concise understanding which holes require what process along with an adequate tool for all inspectional locations.


1) Provides a flat coplanar surface. (For component attachment) 2) More traces on PCB escaping devices through rout channels. (Results in less lyrs / potential lower costs) 3) Increased component density. (Due to absence of periphery vias) 4) Potential EMI / SI benefits. 5) Thermal dissipation. (Lower Inductance due to no dog bone pads with traces.)

(Either at lead connections or under devices ­ heat pipes)

6) No via (Soldermask) plugging required at the component locations. (Conductive Filled Vias seal off the possibility of solutions wicking up from the bottom side. This also provides a flatter soldermask / pad surface which will yield greater feature resolution during stencil paste printing for assembly)


The process is rendered by drilling, copper plating, and filling the vias using standard PCB fabrication equipment. Once the non-conductive filled vias are cured and planarized, the balance of the PTH's are processed which yields a flat copper plated cap over the non-conductive filled vias. The non-conductive filling polymer consists of a composition of epoxy polymers and fillers that produces a filled via plug that closely matches the CTE of a FR-4 multilayer (<35 ppm). (See Process Flow Chart on Next Page)

Hole Plugging ­ Overview of the Process

VIP Process flow

NC drilling

Through hole plating


PHP selective hole plugging

Back-up board Solder mask


Copper plating on surface

To Solder Mask process

Copper plating on surface


These filled holes sometimes have minor dimples that are in the pads surfaces caused when the epoxy plugs are cured. (See Illustration 2 and 3) By driving out the curing solvents during the baking/curing process, a small dimple can be formed. This dimple is relatively small and should not create any issues during assembly. Additionally, sometimes a minor air bubble may be found in the PTH. (See Illustration 4) These too have been evaluated and should not create any issues to the assembled PCA.

1.70 1.20 0.70 0.20 -0.30 -0.80 -1.30 -1.80 49 43 AE 37 31 25 N 19 13 7 A 2 AU BJ 1.20-1.70 0.70-1.20 0.20-0.70 -0.30-0.20 -0.80--0.30 -1.30--0.80 -1.80--1.30

Typical Dimple = 25 um (<1 mil)

Illustration 2 and 3

Small Bubble can sometime be present

Illustration 4

The via-filling technology has provided additional benefits for internal via holes (IVH) of the HDI PCBs. By having the IVH via core holes epoxy pre-filled before the next lamination task, the prepreg results can be more predictable due to the inner laminar bonds consisting of flat layers to be laminated. Internal open vias would no longer be a concern regarding the capillary action of the removal of free resin. (See Illustration 5 and 6 below)

Illustration 5

Illustration 6

The equipment used to produce these epoxy-filled vias structures has evolved to the point that they can produce very consistent, acceptable repeatable results. By utilizing a series of tightly controlled mechanical abrasive sanders or ceramic hones, the epoxy/copper surfaces can be planarized to produce very flat planar surfaces. These flat surfaces allow for both a good surface to solder (attach) components and devices to surface via-in-pad locations on the PCBs. It has additionally been found to produce acceptable results for surface mating gold-to-gold socketed technology connections.


· · Aspect Ratios from 1:1 to 15:1. (Up to 6:1 in Production) R & D Quantities Only Minimum Through Hole Size of 10 mils. (Micro Vias also can be filled. See Illustration 7,8,& 9)

Filled Blind Vias Lyrs 1-2 and 1-3

Illustration 7, 8, & 9

Future Applications

Higher density devices have driven this technology to new product / technology challenge levels. One of which is socketed surface mating technologies. (i.e., Connectors, LGAs, and BGAs) Some of the new surface requirements for higher I/O devices have exceeded standard PCB parameters. The higher I/O devices have additionally driven the PCB technology to higher layer counts and thicker PCBs, which has in turn impacted PCB manufacturing yields. By using non-conductive epoxy-filled via technology, challenges associated with high aspect ratio designs have been alleviated, and yields optimized. (See Illustration 10)

Illustration 10

Reliability Tests

The filled vias have been subjected to PCB Thermal Shock Tests parameters and have been found to survive 6 X at 288'C. (Thermal Shock Tests)

IST Results ­ (Reliability Tests)

PTH performance all 6 heads

120 115 110 105 100 95 90 85 80 75 70 change in mohms 60 55 50 45 40 35 30 25 20 15 10 5 0 -5 -10 -15 1 13 25 37 49 61 73 85 97 109 121 133 145 157 169 181 193 205 217 229 241 253 265 277 289 301 313 325 # of Cycles

change in mohms 120 115 110 105 100 95 90 85 80 75 70

PTH performance all 6 heads


741-1-1 741-1-2 741-1-3 741-1-4 741-1-5 741-1-6

65 60 55 50 45 40 35 30 25 20 15 10 5 0 -5 -10 -15 1 10 19 28 37 46 55 64 73 82 91 100 109 118 127 136 145 154 163 172 181 190 199 208 217 226 235 244 253 # of Cycles

741-1-1 741-1-2 741-1-3 741-1-4 741-1-5 741-1-6

IST Coupons Without Filled Vias

IST Coupons With Filled Vias

This IST testing suggests that that the Filling of the Vias with Non Conductive Epoxy produces results that meet (or exceed) the results of standard PTH technology


This new process provides a cost-effective way for the PCB designer to potentially reduce PCB fabrication costs and regain additional real estate typically lost by conventional dog bone traces between component pads and vias. By using via-in-pad technology, the designer can regain more rout channels to adequately rout challenging fine pitch devices. One of the methods to achieve via-in-pad technology is non-conductive via fill. Another upcoming usage for this technology is surface mounted socketed BGAs, LGAs, and Surface Mounted Connectors. The current Reliability Tests are promising and suggest that PCBs using this technology will be equivalent (if not better than) standard through hole PCB Technology.

Future Activities

· · · · ·

(My Wish list)

Increased Demand for VIP Technology due to High Speed Requirements (Low Lead inductance) Increased Demand for VIP Technology due to increased Routability (Finer Pitch Components drives the Density Up requiring more Metal Fanout Design Channels) Thermal Dissipation Possibilities (Copper Plating Thickness, Connection to Planes, MLF Devices) NC Dispensing (Precise Application of the Inks / Media) Full PTH Sealing for Assembly Reliability (Sealing of the Via in Pads stops the solder Volume from wicking away from the Solder Joints)


Special Thanks to the Multek Germany and China Teams in all their efforts in developing and optimizing these upcoming promising technologies.


1. 2. 3. 4. IPC, "IPC-2315 Design Guide for High Density Innerconnects (HDI) and Micro Vias", Released IPC Document IPC, "IPC-2226 Design Standard for High Density Innerconnect (HDI) Printed Boards", Released IPC Document D.H. Hoover, "Conductive Filled Vias for Via-in-Pad Technology", Data Circuit Systems Inc., 3/02 San Jose R.A. Wessel, "Polymer Thick Film Via Plug for PCBs and Packaging Applications", Proceedings to Technical Conference, IPC Expo, 3/98 Long Beach


Microsoft Word - Non-conductive Epoxy Filled vias in PCB white paper.doc

6 pages

Find more like this

Report File (DMCA)

Our content is added by our users. We aim to remove reported files within 1 working day. Please use this link to notify us:

Report this file as copyright or inappropriate


You might also be interested in

Microsoft Word - RFID_AIChE_E&Mpdfatc.doc
Microsoft Word - Non-conductive Epoxy Filled vias in PCB white paper.doc