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Realizing a Power Efficient, Easy to Program Manycore: The Tile Processor

Anant Agarwal Tilera, MIT

Multicore is Everywhere

Laptop Automobiles

Cellphones Datacenters/Clouds

Telepresence

TVs

Desktop

Network Network Switches Switches

2

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Parallel Computing No Longer Province of Rocket Scientists

#Cores n Cores

1000 cores

32

64 cores

Sun IBM Cell

Larrabee 8-24 cores

4

Intel

Quad core

The computing world is ready for radical change

2 1 2005

3

Dual core Time 2006 2007 2014

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Tilera Announced the TILE-Gx100 in Oct `09

100 general-purpose cores Runs SMP Linux Standard programming 1.25GHz ­ 1.5GHz Full 64-bit processors 32 MBytes total cache 546 Gbps memory BW 200 Tbps iMesh BW 80-120 Gbps packet I/O 80 Gbps PCIe I/O Wire-speed packet engine

Flexible Flexible I/O I/O

Memory Controller Memory Controller

Memory Controller Memory Controller

MiCA MiCA

Misc Misc I/O I/O

Network Network I/O I/O mPIPE mPIPE

3 PCIe 3 PCIe

Interfaces Interfaces Eight Eight 10Gb 10Gb -or-or32 1Gb 32 1Gb -or-orTwo 40Gb Two 40Gb

­ ­ ­

120Mpps 40 Gbps crypto 20 Gbps compress

MiCA engines:

Memory Controller Memory Controller Memory Controller Memory Controller

MiCA MiCA

4

© 2009 Copyright Tilera Corporation. All Rights Reserved.

But first, let's rewind to 1996

5

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Research Vision to Commercial Product

The opportunity 1B Transistors in 2007 A blank slate The future? TileGx100 100 cores

MiCA MiCA

UART x2, USB x2, UART x2, JTAG, USB x2, I2C, SPI JTAG, I2C, SPI

Memory Controller Memory Controller Memory Controller Memory Controller

(DDR3) (DDR3)

4x GbE SGMII (DDR3)

(DDR3)

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

SerDes SerDes SerDes SerDes

2018

mPIPE mPIPE

PCIe 2.0 PCIe 8-lane 2.0 8-lane

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

PCIe 2.0 PCIe 8-lane 2.0 8-lane PCIe 2.0 PCIe 4-lane 2.0 4-lane

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

1996

MIT Raw 16 cores

Flexible Flexible I/O I/O

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

MiCA MiCAMemory Controller

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

Memory Controller Memory Controller Memory Controller

(DDR3) (DDR3)

(DDR3) (DDR3)

10 GbE 10 GbE XAUI XAUI

2010

CPU

Mem

Tile Processor 64 cores

1997

2002

6 © 2009 Copyright Tilera Corporation. All Rights Reserved.

2007

SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes

100B transistors

SerDes SerDes

Interlaken Interlaken

Interlaken Interlaken

The Opportunity

1996...

20MIPS cpu in 1987

Few thousand gates

7 © 2009 Copyright Tilera Corporation. All Rights Reserved.

The Opportunity

The billion transistor chip of 2007

8 © 2009 Copyright Tilera Corporation. All Rights Reserved.

How to Fritter Away Opportunity

Caches Does not scale Burns a lot of power Control

100 ported RegFil and RR

More resolution buffers, control

9

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Key Multicore Challenges: The 3 P's

Performance challenge

­ How to scale from 1 to 1000 cores -- the number of cores is the new MegaHertz

Power efficiency challenge

­ Performance per watt is the new metric ­ power efficiency trumps instruction-set (ISA) compatibility

Programming challenge

­ How to distinguish between a processor and a paper weight

10

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Our Early Raw Proposal Got parallelism?

CPU Mem

11

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Take Inspiration from ASICs

mem mem

mem

mem mem

ASICs have high performance and low power · Custom-routed, short wires · Lots of ALUs, registers, memories ­ huge on-chip parallelism

But how to build a programmable chip?

12 © 2009 Copyright Tilera Corporation. All Rights Reserved.

Replace Long Wires with Routed Interconnect

Ctrl

[IEEE Computer '97]

13

© 2009 Copyright Tilera Corporation. All Rights Reserved.

16-Way ALU Clump

Distributed ALUs

ALU

ALU

ALU ALU ALU ALU

ALU

ALU

RF

ALU ALU

ALU

ALU

14

© 2009 Copyright Tilera Corporation. All Rights Reserved.

ALU

Bypass Net

ALU

ALU

ALU

Distributed ALUs, Routed Bypass Network

ALU

R

ALU

Scalar Operand Network (SON) [TPDS 2005]

15 © 2009 Copyright Tilera Corporation. All Rights Reserved.

ALU

ALU

ALU

ALU

From a Large Centralized Cache...

16

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...to a Distributed Shared Cache

$

R

ALU ALU ALU

ALU

ALU

ALU

17

[ISCA 1999]

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Distributed Everything + Routed Interconnect Tiled Multicore

$

R

ALU ALU ALU

ALU

Each tile is a processor, so programmable

18 © 2009 Copyright Tilera Corporation. All Rights Reserved.

ALU

ALU

On-Chip Interconnect Routes Messages

payload

$

R

ALU ALU ALU

ALU

For distributed cache access, off-chip misses, I/O, user-level messages

19 © 2009 Copyright Tilera Corporation. All Rights Reserved.

ALU

ALU

header

Tiled Multicore Captures ASIC Benefits and is Programmable

Scales to large numbers of cores Modular ­ design and verify 1 tile Power efficient

­ Short wires plus locality opts ­

CV2f

­ Chandrakasan effect, more cores at 2 lower freq and voltage ­

CV f

Processor Core

S Core + Switch = Tile

20

Current Bus Architecture

© 2009 Copyright Tilera Corporation. All Rights Reserved.

"Raw" Die Photo

...2002

16 tiles, 425MHz, 18 Watts (vpenta) IBM 0.18 micron process

21 © 2009 Copyright Tilera Corporation. All Rights Reserved.

[ISCA 2004]

Research Vision to Commercial Product

The opportunity 1B Transistors in 2007 A blank slate The future? TILE-Gx100 100 cores

MiCA MiCA

UART x2, USB x2, UART x2, JTAG, USB x2, I2C, SPI JTAG, I2C, SPI

Memory Controller Memory Controller Memory Controller Memory Controller

(DDR3) (DDR3)

4x GbE SGMII (DDR3)

(DDR3)

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

mPIPE mPIPE

SerDes SerDes SerDes SerDes

1996

MIT Raw 16 cores

Flexible Flexible I/O I/O

Interlaken Interlaken

2018

PCIe 2.0 PCIe 8-lane 2.0 8-lane

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

PCIe 2.0 PCIe 8-lane 2.0 8-lane PCIe 2.0 PCIe 4-lane 2.0 4-lane

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

MiCA MiCAMemory Controller

10 GbE 10 GbE XAUI XAUI 4x GbE

SGMII

Memory Controller Memory Controller Memory Controller

(DDR3) (DDR3)

(DDR3) (DDR3)

10 GbE 10 GbE XAUI XAUI

2010

CPU

Mem

Tile Processor 64 cores

1997

2002

22 © 2009 Copyright Tilera Corporation. All Rights Reserved.

2007

SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes

100B transistors

SerDes SerDes

Interlaken Interlaken

Why Do We Care?

Markets Demanding More Performance at Lower Power

Cloud

Demands higher performance density and low power

Cloud server rack Cloud server rack

Wireless infrastructure market

Demands higher throughput, more services and low power

GGSN GGSN Base Station Base Station

Networking market

Demands higher performance, better security and services

Security Appliances Security Appliances Switches Switches

Digital multimedia market

Newer algorithms (e.g., H.264) for higher compression demand more performance

Video Conferencing Video Conferencing

Cable & Broadcast Cable & Broadcast

23

© 2009 Copyright Tilera Corporation. All Rights Reserved.

The Tile Processor is a System-on-a-Chip

Performance

# of cores On-chip cache (MB) Cache coherency Operations (16/32-bit BOPS) On chip bandwidth (Terabit/s) Clock speed (MHz)

TILEPro64

64

SerDes SerDes

DDR2 Controller 0 DDR2 Controller 0

DDR2 Controller 1 DDR2 Controller 1

Yes w/ DDC 221/166 38 700, 866

PCIe 0 PCIe 0

XAUI 0 XAUI 0

Flexible Flexible I/O I/O UART UART JTAG JTAG SPI, I2C SPI, I2C SerDes SerDes

GbE 0 GbE 0 GbE 1 GbE 1

Power

Typical power -5 device (W) Typical power -7 device (W) Typical power -9 device (W) N/A 17-21 27-34

DDR2 Controller 3 DDR2 Controller 3 DDR2 Controller 2 DDR2 Controller 2 PCIe 1 PCIe 1 XAUI 1 XAUI 1 SerDes SerDes

I/O and Memory

Ethernet bandwidth PCIe interfaces Flexible I/O pins DDR2 bandwidth (peak Gbps) 2 XAUI, 2GbE 2 x 4-lanes 64 200

TILEPro64 Block Diagram

TILEPro36 also available

24

Tilera development systems

© 2009 Copyright Tilera Corporation. All Rights Reserved.

SerDes SerDes

5.6

Remember the 3 P's?

Performance challenge

­ How to scale from 1 to 1000 cores -- the number of cores is the new MegaHertz

Power efficiency challenge

­ Performance per watt is the new metric ­ power efficiency trumps instruction-set (ISA) compatibility

Programming challenge

­ How to distinguish between a processor and a toaster

25

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Key Innovations

Core

1. General purpose cores ­ Standard OS and programming

Cache + MMU

Terabit Switch

2. iMeshTM Network ­ How to scale and be energy efficient

5. Multicore Development Environment ­ How to program OS1/APP1

3. Multicore Dynamic Distributed Cache ­ How to achieve cache coherence and run standard software

Core

Core

Cache + MMU

Cache + MMU

OS2/APP2 OS1/APP3 4. Multicore HardwallTM ­ How to virtualize multicore

26

Terabit Switch

Terabit Switch

© 2009 Copyright Tilera Corporation. All Rights Reserved.

1 - Full-Featured General Cores Enable Throughput Oriented Computing and Standard Languages

Processor

­ ­ ­ ­ ­ ­ ­ Each core is a complete computer 3-way VLIW CPU Designed for low power ­ 200mW per core SIMD instructions: 32, 16, and 8-bit ops Instructions for video (e.g., SAD) and networking Protection and interrupts Single core performance roughly the same as a modern MIPS or ARM core L1 cache: 8KB I, 8KB D, 1 cycle latency L2 cache: 64KB unified, 7 cycle latency 32-bit virtual address space per process 64-bit physical address space Instruction and data TLBs Cache integrated 2D DMA engine

Core

Register File

Three Execution Pipelines

Memory

­ ­ ­ ­ ­ ­

Cache

16K L1-I 8K L1-D I-TLB D-TLB 64K L2 2D DMA

Switch in each tile Runs SMP Linux Runs off-the-shelf open-source C/C++ programs

Terabit Switch

27

© 2009 Copyright Tilera Corporation. All Rights Reserved.

2- iMesh On-Chip Network

Distributed resources

­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ 2D Mesh peer-to-peer tile networks 5 independent networks Each with 32-bit channels, full duplex Tile-to-memory, tile-to-tile, and tile-to-IO data transfer Packet switched, wormhole routed, point-to-point Near-neighbour flow control, dimension-ordered routing

Core

SWITCH

MDN TDN UDN IDN VDN STN

Performance and energy efficiency

ASIC-like one cycle hop latency 2 Tbps bisection bandwidth 32 Tbps interconnect bandwidth Low power One static, four dynamic IDN ­ System and I/O MDN ­ Cache misses, DMA, other memory TDN, VDN ­ Tile to tile memory access and coherence UDN, STN ­ User-level streaming and scalar transfer

Core

Core

Core

Cache + MMU

Cache + MMU

Cache + MMU

Cache + MMU

Terabit Switch

Terabit Switch

Terabit Switch

Terabit Switch

Core

Core

Core

Core

Cache + MMU

Cache + MMU

Cache + MMU

Cache + MMU

6 independent networks

Core Cache + MMU

Terabit Switch

Terabit Switch

Terabit Switch

Terabit Switch

Core

Core

Core

Cache + MMU

Cache + MMU

Cache + MMU

Terabit Switch

Terabit Switch

Terabit Switch

Terabit Switch

Core

Core

Core

Core

Cache + MMU

Cache + MMU

Cache + MMU

Cache + MMU

Terabit Switch

Terabit Switch

Terabit Switch

Terabit Switch

Achieves scalability and power efficiency

28 © 2009 Copyright Tilera Corporation. All Rights Reserved.

Meshes are Power Efficient

[Konstantakopoulos '07]

More than 80% power savings over buses

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3 ­ Coherent On-Chip Cache System Enables Standard Programming

Distributed cache

­ Each tile has local L1 and L2 cache ­ Aggregate of L2 serves as a globally shared L3

DDR2 Controller 0 DDR2 Controller 0 DDR2 Controller 1 DDR2 Controller 1 SerDes SerDes SerDes SerDes SerDes SerDes

Dynamic Distributed Cache (DDCTM)

­ Hardware based cache coherence ­ Hardware tracks sharers, invalidates stale copies ­ One or multiple coherency domains ­ Dedicated network to manage coherency

tile b

PCIe 0 PCIe 0 XAUI 0 XAUI 0

Flexible Flexible I/O I/O UART UART JTAG JTAG SPI, I2C SPI, I2C

SerDes SerDes

Completely Coherent System

DDR2 Controller 3 DDR2 Controller 3

GbE 0 GbE 0 GbE 1 GbE 1

PCIe 1 PCIe 1

XAUI 1 XAUI 1

tile a

tile h

DDR2 Controller 2 DDR2 Controller 2

Coherent direct-to-cache I/O

­ Header/packet delivered directly to tile caches ­ Cache coherent delivery ­ Significant DRAM bandwidth and latency reduction

30 © 2009 Copyright Tilera Corporation. All Rights Reserved.

4 ­ Multicore HardwallTM Technology for Virtualization and Protection in Cloud Environments

The virtualization and protection challenge Multicores need to run multiple OS's and applications in cloud environments OS's must be protected from each other I/O and other shared resources must be virtualized Multicore Hardwall technology Protects applications and OS by prohibiting unwanted interactions Configurable to include one or many tiles in a protected area Supported by Tilera hypervisor running on all the tiles

OS1/APP1

OS2/APP2 OS1/APP3

31

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Configurable Fine Grain Protection

Full Stack Linux with Hypervisor

TLB Access 1 0 2 3 DMA Engine 1 0 2 3 "User" Network 1 0 2 3 I/O Network 1 0 2 3

Key: Key: 0 ­ User Code 0 ­ User Code 1 ­ OS 1 ­ OS 2 ­ Hypervisor or PAL 2 ­ Hypervisor or PAL 3 ­ Hypervisor Debugger 3 ­ Hypervisor Debugger

32 © 2009 Copyright Tilera Corporation. All Rights Reserved.

5 ­ Standard Tools and Software Stack

Multicore Development Environment Standards-based tools Standard programming

SMP Linux 2.6.26 ANSI C/C++ pthreads

Standard application stack Application layer

Open source apps Standard C/C++ libs

Applications

Linux libraries Applications libraries

Operating System layer Integrated tools

SGI compiler Standard gdb gprof Eclipse IDE 64-way SMP Linux Zero Overhead Linux Bare metal environment

Operating System

Linux kernel and kernel drivers

Hypervisor

Virtualization and high speed I/O drivers

Hypervisor layer Innovative tools

Multicore debug Multicore profile Virtualizes hardware I/O devices drivers Load balancer

TILE hardware

Tile Tile Tile Tile ...

33

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Multiple Software Environments to Meet Diverse Needs of Embedded and Cloud Systems

Standard SMP Linux

­ Standard Linux environment with processes and threads ­ Ideal for applications and control plane code requiring operating system services ­ Open source applications work out of the box

Standard SMP Linux with Zero Overhead Linux (ZOL)

­ Zero Linux overhead (Eliminates OS interrupts, timer ticks, etc..) ­ Transparent to programmer - no software change required ­ For high performance data-plane applications not requiring OS services

Bare metal environment

­ Full control of the hardware on up to 64 tiles ­ No operating system or hypervisor layers ­ For embedded applications requiring fine grain control of memory, and IO

Hybrid environment

­ Using 2 or all three of the above models ­ Each environment can be run on one or more Tiles ­ Ideal for customers aggregating data plane and control plane code on one chip

34

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Parallel Programming using Standard Models

64-way SMP Linux

­ Single system image across all tiles

DPI Load Balancer DPI DPI

Standard pthreads API

­ ­ ­ pthread_create() Shared memory model by default Synchronize using mutexes and locks

Packet stream

Histogram

Deep packet inspection

Standard Linux processes

­ ­ ­ ­ fork(), exec() Separate address space Share memory: mmap(), mspaces Communicate: Pipes / local sockets

DDR2 Memory Controller 00 DDR2 Memory Controller DDR2 Memory Controller 11 DDR2 Memory Controller

DPI

PCIe 00 PCIe MAC MAC PHY PHY Serdes Serdes UART, HPI UART, HPI JTAG, I2C, JTAG, I2C, SPI SPI Flexible IO Flexible IO

HST DPI LB DPI

XAUI XAUI MAC MAC PHY 00 PHY Serdes Serdes GbE 00 GbE GbE 11 GbE Flexible IO Flexible IO

Gentle slope programming optimizations using Linux extensions

­ ­ Control memory location and distribution Control thread scheduling and location

New models and further optimizations using TMC library (Tile Multicore Components)

PCIe 11 PCIe MAC MAC PHY PHY Serdes Serdes DDR2 Memory Controller 33 DDR2 Memory Controller

XAUI XAUI MAC MAC PHY 11 PHY Serdes Serdes DDR2 Memory Controller 22 DDR2 Memory Controller

35

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Scaling Up: TileGx100 Announced in Oct `09

100 general-purpose cores Runs SMP Linux Standard programming 1.25GHz ­ 1.5GHz Full 64-bit processors 32 MBytes total cache 546 Gbps memory BW 200 Tbps iMesh BW 80-120 Gbps packet I/O 80 Gbps PCIe I/O Wire-speed packet engine

Flexible Flexible I/O I/O

Memory Controller Memory Controller

Memory Controller Memory Controller

MiCA MiCA

Misc Misc I/O I/O

Network Network I/O I/O mPIPE mPIPE

3 PCIe 3 PCIe

Interfaces Interfaces Eight Eight 10Gb 10Gb -or-or32 1Gb 32 1Gb -or-orTwo 40Gb Two 40Gb

­ ­ ­

120Mpps 40 Gbps crypto 20 Gbps compress

MiCA engines:

Memory Controller Memory Controller Memory Controller Memory Controller

MiCA MiCA

36

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Scaling Down: TILEGx16 also Announced

16 Processor Cores 1.0 &1.25 GHz speeds Full 64-bit processors 5.2 MBytes total cache 200 Gbps memory BW 20 Tbps iMesh BW 24 Gbps total packet I/O

­ ­ 2 ports 10GbE (XAUI) 12 ports 1GbE (SGMII)

TM

MiCA MiCA

UART x2, UART x2, USB x2, USB x2, JTAG, JTAG, 2C, II2C,SPI SPI SerDes SerDes

Memory Controller (DDR3) Memory Controller (DDR3)

mPIPE mPIPE

PCIe 2.0 PCIe 2.0 4-lane 4-lane

10 GbE 10 GbE XAUI XAUI 4x GbE SGMII 10 GbE 10 GbE XAUI XAUI 4x GbE SGMII

SerDes SerDes

PCIe 2.0 PCIe 2.0 4-lane 4-lane

SerDes SerDes

SerDes SerDes

4x GbE SGMII

32 Gbps PCIe I/O Wire-speed packet engine

­ ­ ­ 30Mpps 10 Gbps crypto 5 Gbps compress & 5 Gbps decompress

SerDes SerDes

PCIe 2.0 PCIe 2.0 4-lane 4-lane

Flexible Flexible I/O I/O

Memory Controller (DDR3) Memory Controller (DDR3)

SerDes SerDes

MiCA engine:

Midrange 36 core part also announced

37

© 2009 Copyright Tilera Corporation. All Rights Reserved.

Vision for the Future

Corollary of Moore's Law: The number of cores will double every 18 months

p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m s s s s s s s s s s s s s s s s s s s s s

The `core' is the logic gate of the 21st century

38 © 2009 Copyright Tilera Corporation. All Rights Reserved.

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