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EMC DESIGN GUIDELINES

CONTENTS 1. 2. 3. 4. 5. 6. 7. 8. 9. Power supply considerations Signal line considerations PCB considerations Component considerations EMC specific components Inductors Common mode chokes Transformers Isolated DC-DC converters

The EC (European Community) regulations regarding electromagnetic compatibility (EMC) affect many aspects of circuit and system design. However, there are many considerations that can be applied generally to reduce both the emissions from and susceptibility to, electromagnetic interference (EMI). As a manufacturer of electronic components, C&D Technologies is committed to minimising emissions from its own components and to helping its customers achieve EMC compliance by correct component choice and design. To this end C&D Technologies have compiled the following list of general design considerations. figure 3).

I Isolate individual systems where possible

(especially analogue and digital systems) on both power supply and signal lines (see figure 4).

2. SIGNAL LINE CONSIDERATIONS I Use low pass filters on signal lines to

reduce bandwidth to signal minimum.

I Keep feed and return loops close on wide

bandwidth signal lines.

I Terminate lines carrying HF or RF signals

correctly (this minimises reflection, ringing and overshoot, see figure 5).

10. Conclusion 1 1. Pre-compliance testing conducted line emissions of DC supplied circuits 12. Pre-compliance 13. Standard test method 14. Shielding 15. DC target circuit under test 16. Circuit conditions 17. Resolution bandwidth and spectra obtained 18. Spectra detection method 19. Using the emissions spectra information 20. Relevant standards 21. Abbreviations

1. POWER SUPPLY CONSIDERATIONS I Eliminate loops in supply lines

(see figure 1).

I Terminate lines carrying signals external to

a board at the board edge, avoid lead terminations within the board and loose leads crossing the board.

I Decouple supply lines at local boundaries

(use RCL filters with low Q, see figure 2).

I Avoid cabling or tracking which is close to

the quarter wavelength of the signal frequency, this can produce resonance within the signal conductor.

I Place high speed sections close to the

power line input, slowest section furthest away (reduces power plane transients, see Figure 1: Eliminate Loops in Supply Lines

I Track all signals on the board, avoid 'flying

leads' across the board.

I Minimise rise and fall times on signal and

clock edges (sharp edges produce wide hf spectra), slew rate limiting also reduces crosstalk (see figure 6).

3. PCB CONSIDERATIONS I Avoid slit apertures in PCB layout, particularly in ground planes or near current paths.

I Areas of high impedance give rise to high

EMI, use wide tracks for power lines on the trace side.

I Make signal tracks stripline and include a

Figure 3: Place High Speed Circuits Close to PSU Figure 2: Decouple Supply Lines at Local Boundaries

Figure 4: Isolate Individual Systems

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EMC DESIGN GUIDELINES

Figure 5: Terminate Signal lines Correctly

I A guard ring around trace layers reduces

emission out of the board, only connect to ground at single point and make no other use of the guard ring (i.e. do not use to carry ground return from a circuit).

I Do not leave any floating conductor areas,

these act as EMI radiators, if possible connect to ground plane (often these sections are placed for thermal dissipation, hence polarity should be unimportant but check component data sheet, see figure 13).

I Avoid overlapping power planes, keep

separate over common ground (reduces system noise and power coupling, see figure 10).

Reflection Coefficient = Z = l ZO - ZT l Z l ZO + Z T l

I Power plane conductivity should be high,

therefore avoid localised concentrations of via and through hole pads (surface mount is the preferred assembly technology)

4. COMPONENT CONSIDERATIONS I Locate biasing and pull up/down

components close to driver/bias points.

ground plane and power plane whenever possible.

I Keep HF and RF tracks as short as

possible, lay out the HF tracks first (see figure 7).

I Track mitring (bevelling the edges at

corners) reduces field concentration (see figure 11).

I Minimise output drive from clock circuits. I Use common mode chokes between current

carrying and signal lines to increase coupling and cancel stray fields (see figure 14).

I Avoid track stubs, these cause reflection

and harmonics (see figure 8).

I If possible make tracking run orthogonally

between adjacent layers (see figure 12).

I Decouple close to chip supply lines,

reduces component noise and power line transients (see figure 15).

I On sensitive components and terminations

use surrounding guard ring and ground fill where possible (see figure 9). Figure 6: Use Slow Rise & Fall Times

I Do not loop tracks, even between layers,

this forms a receiving or radiating antennae.

I Use low impedance capacitors for

decoupling and bypassing (ceramic multilayer types are preferred due to high resonant frequency and stability).

I Use discrete components for filters where

possible (surface mount is preferable due to lower parasitics and aerial effects of terminations on through hole parts).

I Ensure filtering of cables and over voltage

protection at the terminations (this is especially true of cabling that is external to Figure 10: Avoid Overlapping Power Planes

Figure 11: Mitre Track Corners

Figure 7: Keep HF Tracks Short

Figure 8: Avoid Track Stubs

Figure 12: Orthogonal Tracking on Seperate Layers Figure 9: Use Guard Ring & Ground Fill

EMC DESIGN GUIDELINES

the system, if possible all external cabling should be isolated at the equipment boundary). within an existing circuit. The range of components C&D Technologies produce which can be used for specific EMC problems include transformer isolators, standard inductors and common mode chokes. return lines (i.e. induced EMI) while allowing differential mode signals and DC to pass. Suitable choice of inductance will also help in maintaining a match to the characteristic line impedance and acts as a filter to bandwidth limit the termination. Any of C&D Technologies' transformers with a 1:1 ratio can be employed as a common mode signal choke. C&D Technologies also have a portfolio of customer specific chokes and can design a common mode choke for a customer's circuit application.

I Minimise capacitive loading on digital

output by minimising fan-out, especially on CMOS ICs (this reduces current loading and surge per IC).

6. INDUCTORS

The range of inductors available from C&D Technologies are targeted mainly at the power market, and are useful for reducing EMI on power lines and for filtering high current signals. In switched mode power supply (SMPS) circuits inductors for both the energy storage and line filtering are available (see figure 16). It is recommended that a toroidal or sheilded inductor be used if EMC problems are suspected of being emitted from this circuit function. Toroidal inductors maintain the magnetic field within the core shape and hence have virtually zero radiated field. The susceptibility of a toroid is also negligible due to the shape, since an applied magnetic field would generate an equal and opposite current component in the wire (self cancelling). At power sections of various circuit functions, an inductor between the local supply and the main feed provides good filtering of the supply and reduces noise from localised circuits in the system polluting the main power line (see figure 2). Since the inductor here requires a relatively high DC current during its usual operation, axial inductors which have very a high saturation current are recommended. Selection should be made on the current handling and relative switching speed of the circuit section. Generally low values of inductance are preferred due to the associated low DC resistance. In systems with a reactive load or driver a matched termination may be required using a passive reactive circuit. The frequency response of the load/driver needs to be known, but can be matched by a relatively simple and easily characterised RCL network Another area where inductors can be used with great benefit to the EMI of a circuit is in an amplifier bias network (see figure 17). By using an inductive element in the bias or compensation arms, a filter can be added to the circuit without loading the signal with additional inductance. Careful choice of inductance value is required and placement close to the amplifier is essential. This method is suitable for filtering HF noise, particularly on video and VHF/UHF TV type signals.

I If available, use shielding on fast switching

circuits, mains power supply components and low power circuitry (shielding is expensive and should be a 'last resort' option). In general, keeping the bandwidth of all parts of the system to a minimum and isolating circuits where possible reduces susceptibility and emissions. Considerations which are applicable to reducing noise levels are equally applicable to EMC compliance, EMC compliant circuits should obviously exhibit low noise levels.

8. TRANSFORMERS

The main EMC benefit of using a transformer is in providing an isolation barrier between a signal line and the signal processing circuit (particularly where the signal line exits the board or system). This is true of signals being driven or received, since isolating the line reduces common mode noise and eliminates ground (or signal return) potential differences between systems. Figure 16: Basic SMPS and Filter Configuration

5. EMC SPECIFIC COMPONENTS

As a supplier of isolator components, C&D Technologies provide a range of parts which can offer simple solutions to EMC problems Figure 13: Do Not Leave Floating Conductive Areas

Figure 17: Amplifier Filtering with Inductors

Figure 14: Use Common Mode Choke Between Signal Lines

Figure 15: Decouple Close to IC Supply Lines

7. COMMON MODE CHOKES

Common mode chokes are best employed in signal lines to eliminate common mode noise or EMI on cables or induced in the signal tracks (see figure 14). The choke should be located as near to the driver/receiver circuit as possible, or at the entry point of a signal to a board. The choke works by cancelling interference appearing on both signal and

One particular area where high noise is essential is in thyristor/triac driving circuits, where the transformer is providing an isolation between a mains driven load and a logic based controller (see figure 18). The isolating pulse transformer provides much better noise immunity than an insulated gate bipolar transistor (IGBT) due to inherently lower coupling capacitance (typically tens of pF for a pulse transformer compared to nF for power IGBT devices). The lower coupling capacitance improves the circuits immunity for noise on the mains and from the power switching device.TORS DESIGN . 11.

EMC DESIGN GUIDELINES

Figure 18: Triac/Thyristor Firing Circuit

14. SHIELDING

At all times the DC powered circuit under test (CUT), LISN and all cables connecting any measurement equipment, loads and supply lines should be shielded. The shielding is to prevent possible pick-up on cables and the CUT from external EMC sources (e.g. other equipment close by, radiated emissions from the PSU etc). The shielding is again referenced to mains earth. When measuring small circuits or individual components, the whole part can often be fitted into a metal enclosure for testing. All power and test entry points should be via shielded connectors, preferably high frequency BNC types. The LISN should be shielded and external to the enclosure containing the test circuit (see figure 23).

9. ISOLATED DC-DC CONVERTERS

An isolated DC-DC converter can provide a significant benefit to reducing susceptibility and conducted emission due to isolating both power rail and ground from the system supply (see figure 4). Isolated DC-DC converters are switching devices and as such have a characteristic switching frequency which may need some additional filtering (see figure 21).

therefore only be considered as precompliance tests, the end system would have to be fully compliance tested for full CE certification. However, if the system is to be certified via the Technical Construction File (TCF) route, the individual pre-compliance tests may be used as part of the TCF.1

13. STANDARD TEST METHOD

Having no EN standard relies on the user to implement the closest equivalent test standard to the existing EMC regulations for mains borne emissions. One of the first problems with a DC supply is removing the test PSU noise from the target circuit noise while performing the test (assuming the test PSU is not the same as the final system PSU). The removal of line noise is performed on AC mains connected systems using a line impedance stabilisation network (LISN) on both live and neutral lines and referenced to the mains earth as a ground plane. This has been directly copied for the testing of DC supplied circuits, using any DC PSU with an earth terminal, both the positive and ground (or 0V) lines are filtered with a LISN referenced to the mains earth terminal. Each LISN is constructed in accordance with CISPR 16 for 50/50µH line impedance (see figure 22). There are other reasons for using the mains earth as a reference than just the ability to relate the test to the standard EN specifications, in many systems the mains earth will in fact be the case ground plane. If it is known that the 0V line is the ground plane reference the earth reference can be connected to the 0V line at the supply, with both LISNs still on the DC supply lines (the LISN on the 0V line should still be connected as this gives an indication of likely ground line noise). Circuits supplied with multiple DC lines will require a LISN on each power feed and the noise measured on each of the power lines. Figure 21: Filtering a DC-DC Converter

15. DC TARGET CIRCUIT UNDER TEST

There are innumerable circuit configurations that could be used as a test circuit for an example, however, it was decided instead to use a board level DC-DC converter with a resistive output load. Board level DC-DC converters are a common place item on many PC boards, instrumentation and processing equipment. The advantage of using a DC-DC converter here is that it has a known characteristic switching frequency (see figure 24), hence a stable well behaved noise spectrum can be obtained easily and the vagaries of the actual circuit functionality can be circumvented. The DC-DC converter used was an NMS1212, 12V input, 12V dual output device delivering a total 2W of power with a typical characteristic switching frequency of 35kHz. This device has a number of line spectra below the EC EMC lower limit for conducted emissions (150kHz), but no sub-harmonics below its fundamental switching frequency.

10. CONCLUSION

The above recommendations, if followed, should allow completed systems to achieve CE certification first time. They should give a designer more confidence in their circuits ability to meet the EC directive and offer good advice for low noise circuitry.

11. PRE-COMPLIANCE TESTING CONDUCTED LINE EMISSIONS OF DC SUPPLIED CIRCUITS

Power supply (PSU) designers should be well aware by now of the requirement of their power supply to provide clean DC voltage to the target circuit and not to disturb the ac mains voltage. However, often the PSU designer may have no idea of the noise that can potentially be introduced by the target circuit, likewise the DC circuit designer (digital or analogue) may not be aware of the requirements of the PSU as far as acceptable noise levels are concerned. The aim of this section is to bridge this gap, to provide a method for testing the DC circuit in isolation from its final PSU and enable either additional filtering to be specified, or PSU immunity to conducted noise to be requested. Either way it enables the two designers to work towards a common goal; CE certification of the final product.

16. CIRCUIT CONDITIONS

To ensure that worst case conditions, as far as EMC is concerned, are applied to the CUT it is necessary to have some knowledge of the circuit operation, hence it is usually best specified by the CUT designer. In the case of the NMS DC-DC converter, worst case is at full load (i.e. 2W output) with maximum input voltage (see figure 25), although the input voltage actually had a minimal effect within its allowed tolerance. Other worst case conditions may be difficult to apply (e.g. high temperature, see figure 26) due to the nature of the test environment, however, some gauge of how these may effect the EMC performance should be considered. Where circuit loading conditions and their effect on EMC are not known, tests can be done in-situ on the CUT prior to the precompliance test.

12. PRE-COMPLIANCE

There are no specified EMC limit lines for DC rails, hence there are no specified tests in the EC or CENELEC regulations that can be applied directly. Likewise the PSU and the DC supplied circuit could only be considered as sub-systems at best, possibly even components, consequently on their own they are exempt from the EC directive. The tests conducted can

EMC DESIGN GUIDELINES

17. RESOLUTION BANDWIDTH AND SPECTRA OBTAINED

One of the first problems may be to decide on the resolution required for the pre-compliance tests. To maintain compatibility with the EC directive for mains emissions, a 9kHz resolution bandwidth (RBW) should be used for conducted line measurements. In circuits with only a few line emissions this may be suitable, however, with analogue processing circuits or asynchronous logic there are likely to be some wideband spectra. It is also possible that individual line spectra may change with loading conditions but within a predefined envelope, hence widening the RBW can encompass this envelope. If we consider the NMS again, as a square wave quasi-resonant converter there are two main switching peaks, one at the resonant frequency (35kHz) and another at twice the resonant frequency (reflected full wave rectification, see figure 24). There are also harmonics of these across the whole emissions Figure 22: CISPR16 LISN Circuit spectra (falling significantly at 5MHz, see figure 27). In the frequency range of interest there are therefore 853 individual line spectra if resolved at 9kHz RBW, variation in tolerance of components, input voltage accuracy and loading could change the operating frequency by as much as 20%, hence more than 200 additional lines could be added or subtracted from the spectra. Overall the envelope tends to remain fairly constant, hence simply widening the RBW to 120kHz gives the envelope function and not the individual line spectra (see figure 28). The information is now easier to use and understand and possible variations should be encompassed by this envelope. Widening the RBW should only be done in situations where there is wideband noise or a large number of closely related individual spectra. Most circuits will be able to use a 9kHz RBW. It should also be noted that when using a spectrum analyzer the effective noise floor is raised when the RBW is widened, hence the lower level noise can be swamped out by this effect. It is always worth trying the narrowest RBW first then widening as and when necessary. can be achieved by reducing the video bandwidth of the spectrum analyzer to less than the RBW. Quasi-peak detection is designed to simulate a subjective human type response to a pulse type interference. Quasipeak weights rise and fall times of the signal to produce a given level. A continuous wave signal would be identical with all three detection methods, infrequent pulsed interference would be higher via a quasi-peak detection and lowest using peak detection. It is up to the user to decide on the most appropriate detection method for their circuit. If in doubt use the quasi-peak method. Here the spectra was produced by continuous pulses from the DC-DC converter, peak detection could have been used but average detection was used as this gave a cleaner envelope trace.

19. USING THE EMISSIONS SPECTRA INFORMATION

There are several uses for the spectra obtained; the circuit could be redesigned or the PCB layout changed to reduce the noise, there could be additional filtering added at the PSU input to the DC circuit or the circuit could prove to have so little noise as to require no changes. If considering redesign it is possible to determine which of multiple layouts are the quietest or which components are quietest, does filtering on the sensors or load points Figure 25: Input Voltage Effect on Switching Frequency

18. SPECTRA DETECTION METHOD

There are essentially three methods of measuring conducted line spectra; peak detection, average detection and quasi-peak detection. Peak detection is the instantaneous measurement of the signal, this is essentially best for continuous wave spectra and 'snapshots' of the emissions. Average detection measures the average over a time period, this Figure 23: Test Set-Up

Figure 24: Switching Spectra of NMS1212

Figure 26: Temperature Effect on Switching Frequency

EMC DESIGN GUIDELINES

Figure 27: NMS1212 Spectra with 9kHz RBW CENELEC CISPR CSA DEMKO DIN DTI EC EIA reduce noise? Does noise get to the PSU from the logic, clock or interface circuits? All these should be examinable on the circuit while still in the pre-production or design stages. Filtering may be the lowest cost option of getting the circuit through pre-compliance. If redesign represents a major investment in time and money, simply adding a capacitor and inductor to the input line may only add minimal cost and drop the noise by 20dB at the problem frequency. Alternatively you may even have to specify to the PSU designer that the PSU must give a specified noise rejection, 20dB to noise below 1MHz for example. The standard EMC limit lines can be placed as overlays on the noise emissions to determine what rejection the PSU requires. Often this is not quite as straight forward as it sounds as PSU output capacitors and CUT input capacitors may result in a significantly higher rejection than would be suggested by simply using 50 noise sources (the PSU and CUT are unlikely to have 50 impedance, or even matched impedances). As stated previously, Figure 28: NMS1212 Spectra with 120kHz RBW these tests are only precompliance and further tests with the PSU and circuit in the target system will have to be conducted prior to certifying the completed product. EN EMC EMI ETSI FCC HF IEC ISO ITU JISC NSF RF TCF SAA SCC SFA SEMKO UHF UL UNI VDE VHF Comite European de Normalisation Electrotechnique Comite International Special des Perturbations Radioelectriques Canadian Standards Authority Dansk Standard (Denmark) Deutsches Institut fur Normung (Germany) Department of Trade and Industry (UK) European Community Electronic Industries Association European Standard (Norme European) ElectroMagnetic Compatibility ElectroMagnetic Interference European Telecommunications Standards Institute Federal Communications Commission (US) High Frequency International Electrotechnical Commision International Organisation for Standardisation International Telecommunication Union Japanese Industrial Standards Committee Norges Standardiseringsforbund (Norway) Radio Frequency Technical Construction File Standards Australia Standards Council of Canada Finnish Standards Association Svenska Elektviska Kommissionen (Sweden) Ultra High Frequency Underwriters Laboratory (USA) Ente azionale Italiano di Unificazione (Italy) Verband Deutsche Electrotechniker (Germany) Very High Frequency

20. RELEVANT STANDARDS

The following are some of the relevant EMC standards applicable in various countries that the above design notes are intended to address. FCC 15J/SUB Part B VDE 0871 CISPR 22 EN 60555-2/3 EC Directive 89/336/EEC

21. ABBREVIATIONS

ANSI BSI CE American National Standards Institute British Standards Institute Certificate of EMC Compliance

C&D Technologies (NCL) Limited reserve the right to alter or improve the specification, internal design or manufacturing process at any time, without notice. Please check with your supplier or visit our web site to ensure that you have the current and complete specification for your product before use. © C&D Technologies (NCL) Limited 2001 AN010.1 No part of this publication may be copied, transmitted or stored in a retrieval system or reproduced in any way including, but not limited to, photography, photocopy, magnetic or other recording means, without prior written permission from C&D Technologies (NCL) Limited. Instructions for use are available from www.dc-dc.com

C&D Technologies (NCL) Ltd Tanners Drive, Blakelands North Milton Keynes MK14 5BU, England Tel: +44 (0)1908 615232 Fax:+44 (0)1908 617545 email: [email protected] www: http://www.dc-dc.com

C&D Technologies (NCL), Inc. 5816 Creedmoor Road, Raleigh NC 27612, USA Tel: +1 (919) 571-9405 Fax: +1 (919) 571-9262 email: [email protected]

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