Read mitac%208050.pdf text version

SERVICE MANUAL FOR

8050

BY: Grass.Ren

Repair Technology Research Department /EDVD Feb.2004

8050 N/B Maintenance

Contents

1. Hardware Engineering Specification ............................................................................. 1.1 Introduce ............................................................................................................. 1.2 System Overview .................................................................................................... 1.3 System Hardware Parts .............................................................................................. 2. System View & Disassembly ...................................................................................... 2.1 System View ......................................................................................................... 2.2 System Disassembly ................................................................................................. 3. Definition & Location of Connectors / Switches Setting ...................................................... 4. Definition & Location of Major Component .................................................................... 5. Pin Description of Major Component............................................................................. 5.1 Pentium4 (Willamette/Northwood) processor ..................................................................... 5.2 Sis650 North Bridge ................................................................................................. 5.3 Sis962 South Bridge ................................................................................................. 6. System Block Diagram ............................................................................................... 7. Maintenance Diagnostics ............................................................................................ 7.1 Introduction ......................................................................................................... 7.2 Debug Card ............................................. ............................................................ 7.3 Error code....................................... ....................................................................

3 3 6 9 34 34 37 57 60 62 62 66 75 83 84 84 85 86

1

8050 N/B Maintenance

Contents

8. Trouble Shooting ...................................................................................................... 8.1 No Power ............................................................................................................. 8.2 Battery Can not Be Charged ........................................................................................ 8.3 No Display ....................................... .................................................................... 8.4 External Monitor No Display ........................................................................................ 8.5 Memory Test Error ................................................................................................. 8.6 Keyboard/Touch-pad Test Error ................................................................................... 8.7 USB Port Test error.................................................................................................. 8.8 Hard Disk Drive Test Error.......................................................................................... 8.9 CD-ROM Test Error ................................................................................................ 8.10 Audio Test Failure.................................................................................................. 8.11 LAN Test Error .................................................................................................... 8.12 Modem Test Error............... .................................................................................. 8.13 Mini-PCI Test Error........... ......... ........................................................................... 8.14 Card Bus&Reader Test Error...................................................................................... 8.15 TV Encoder Test Failure ........................................................................................ 8.16 IEEE1394 Test Failure ............................................................................................. 9. Spare Parts List ....................................................................................................... 10. System Exploded View ............................................................................................. 11. Circuit Diagram ..................................................................................................... 12. Reference Material .................................................................................................

89 90 95 97 103 105 107 109 111 113 115 118 120 122 124 126 128 130 141 142 176

2

8050 N/B Maintenance

1. Engineer Hardware Specification

1.1 Introduce

The MiTAC 8050 model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package. It can support Banias 1.5G ~ 1.9GHz/Dothan 2.0GHz and above. This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface (ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system status, such as AC Power indicator, Battery Power indicator, Battery status indicator, HDD,CD-ROM, NUM LOCK, CAP LOCK, SCROLL LOCK, RF on/off Card Reader indicator. It also equipped with LAN, 56K Fax MODEM, 3 USB port, S-Video and audio line in/out , external microphone function. The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC1600/PC2100 DDRSDRAM. The Montara-GME GMCH Host Memory Controller integrates a high performance host interface for Intel Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, Digital Video port (DVOB & DVOC) interface, and Intel Hub interface Technology connecting with Intel 82801DBM ICH4-M. The Intel ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers,

3

8050 N/B Maintenance

and Intel Hub interface technology. The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics2 performance for notebooks. It's architecture introduces the latest achievements in the graphics industry, which enable the use of the progressive new features in upcoming applications, but without compromising performance. ATIs support of support of DirectX® 9 features, highly optimized Open GL® support, and flexible memory configurations allow implementations targeted at the gaming enthusiast, consumer, business and workstation platforms. The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management Interface (ACPI). The VT6307L is a single chip PCI Host Controller for IEEE 1394-1995 Release 1.0 and IEEE 1394a P2000. It implements the Link and PHY layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0 and 1394a P2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance data transfer via a 32-bit bus master PCEI host bus interface. The VT6307L supports 100, 200 and 400 Mbit/sec transmission via an integrated 2-port PHY. The VT6307L services two types of data packets: asynchronous and isochronous(real time). The 1394 link core performs arbitration requesting, packet generation and checking, and bus cycle master operations. It also has root node capability and performs retry operations. The RICOH R5C592 CardBus/Media Reader controller functions as a single slot PCI to Cardbus bridge and also PCI interface smart card and MS/SD/MMC flash card reader. The R5C592 provide one Cardbus slot and all reader interface may operate simultaneously.

4

8050 N/B Maintenance

The CH7011A is a display controller device which accepts a digital graphics input signal, and encodes and transmits data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable voltage data port which supports five different data format including RGB and YcrCb. The TV-Out processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text display. Eight graphics resolutions are supported up to 1024 X 768 with full vertical and horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Support is provided for Macrovision and RGB bypass mode which enable driving a VGA CRT with the input data. The W83L950D is a high performance microcontroller on-chip supporting functions optimized for embedded control.These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system configurations, so that compact, high performance systems can be implemented easily. A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME, Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power shutdown. Following chapters will have more detail description for each individual sub-systems and functions.

5

8050 N/B Maintenance

1.2 System Overview(1)

CPU Chip Set L2 Cache System BIOS Memory Intel Mobile Pentium-M Processor 1.5G ~ 1.9GHz/Dothan 2.0GHz and above -Thermal spec 35W TDP Intel 855GME+ICH4 1MB on-die for Pentium-M/ 2MB for Dothan 512KB Flash EPROM - include System BIOS, VGA BIOS - Plug&Play capability -ACPI 0MB DDR266/333 SDRAM memory on board - 200pin DDR266/333 SDRAM SO-DIMM Memory Module - Expandable to 1,024MB - 1.25-inch height memory module supported Video Controller Optical drive FDD HDD Display 1.SMA 2.Reserve external VGA for Ati M10/M11 Combo / DVD-RW, DVD-RAM (12.7mm) External USB I/F Option 2.5" 30GB / 40GB / 60GB / 80GB HDD(9.5mm) 4200rpm or 5400rpm - Ultra DMA 100 15.4" Wide WXGA+ TFT -Resolution: 1280x800 - 1 CCFT Typical 185cd/m2 -16.77 Million Colors with dithering

6

8050 N/B Maintenance

1.2 System Overview(2)

Continue to previous page

Keyboard US/UK/Japanese keyboard layout(Use the Orignal KBD that other model used) - 19mm key pitch / 3mm stroke - Hot key spec: Fn+F1 : WirelessLAN ON/OFF, Fn+F3/E4 : Volume down/up, Fn+F5 : LCD/CRT output change Fn+F6/F7: Brightness up/down, Fn+F11: Display ON/OFF, Fn+F12: Standby Pointing Device TouchPad (No scroll button) TypeII x 1 -PCMCIA Standard Rev.2.1 , CardBus support , w/o ZV port Audio System Built-in Sound system - SCMS support - AC97 I/F - 16-bit Sampling and Playback - 16-bit stereo - Full duplex supported - 3D sound supported - AC-3 support - Built-in 2W Woofer - Built-in stereo speaker, Built-in microphone - Sound Volume control by Hot-Key (Fn + F3 : Volume down, Fn + F4 : Volume up) Card Reader I/O Port Support Mulit Card Reader USB(2.0) x 3 IEEE1394 port x 1(4pins) Mic-in(mono) x 1 Headphone-out(stereo)/SPDIFx 1

8

8050 N/B Maintenance

1.2 System Overview(3)

Continue to previous page

Line-in x 1 TV-out (PAL/NTSC) x 1 (Macrovision supported) RJ-45 LAN Jack x 1 (with cap) RJ-11Modem Jack x 1 (with cap) Mini-PCI connetor (for WirelessLAN Card) VGA port x 1 DC-in x 1 Communication Battery Power Supply Safety Lock Dimension Weight OS Accessories Windows Logo 56Kbps(V.90) Fax Modem(MDC) and 100Base-TX LAN Wireless LAN (IEEE802.11b, g,a/g) Li-ion Battery 2200mAh(6-cell) - Battery Life: (TBD) -RTC bckup battery(Lithium) Standard -Power-ON charge available 60W Universal AC Adapter(100-240V) Security Lock hole W353.8 x D250 x H25~32mm (P)3.0kg Windows XP Home Service Pack 1 TBD Support PC2001 Specification - need to get the Logo for WindowsXP Home, WHQL Certified EMI / Safety / Regulation EMI:CE/FCC/UL/TUV, BSMI/CCC(TBD) Wireless:CE/FCC,WiFi, PTT:CE/FCC, USB:USB2.0 Logo, Energy Star, Harmonic Noise regulations

8

8050 N/B Maintenance

1.3 System Hardware Parts

1.3.1 Intel Banias processors in Micro-FCPGA package.

Intel Banias Processors with 478 pins Micro-FCPGA package. The first Intel mobile processor with the Intel NetBurst micro-architecture which features include hyper-pipelined technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock. Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and frequency between two performance modes.

1.3.2 Clock Generator

System frequency synthesizer: ICS950810 Programmable output frequency, divider ratios, output rise/fall time,

9

8050 N/B Maintenance

output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions. Programmable watchdog safe frequency. Support I2C Index read/write and block read/write operations. Use external 14.318MHz crystal.

1.3.3 Montara-GME GMCH IGUI 3D Graphic DDR/SDR Chipset

Montara-GME GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and Intel®' I/O Hub architecture INTEL 82801DBM ICH4-M. Montara-GME GMCH Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die termination to support Intel Banias processors. Montara-GME GMCH provides a 12-deep InOrder-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Banias series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated GUI, Montara-GME GMCH also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature Intel®' I/O Hub architecture is incorporated to connect Montara-GME GMCH and INTEL 82801DBM ICH4-Mtogether. Intel®' I/O Hub architecture is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to transfer data w/ 533 MB/s bandwidth

10

8050 N/B Maintenance

from/to Multi-threaded I/O Link layer to/from Montara-GME GMCH, and the Multi-threaded I/O Link Encoder/Decoder in Montara-GME GMCH to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from INTEL 82801DBM ICH4-M. An Unified Memory Controller supporting DDR266 DRAM is incorporated, delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GME GMCH adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.

Features Processor/Host Bus Support

Intel® Banias processor Support host bus Dynamic Bus Inversion (DBI) 2X Address, 4X data Supports system bus at 400MT/s (100 MHz) Supports 64-bit host bus addressing 8-deep In-Order-Queue

11

8050 N/B Maintenance

AGTL+ bus driver technology with integrated GTL termination resistors and low voltage operation (1.05V) Supports Enhanced Intel® Speed Step TM Technology (EIST) and Geyserville III Support for DPWR# signal to Banias processor for PSB power management

Memory System

Directly supports one DDR channel, 64-bts wide (72-b with ECC). Supports 200-MHz and 266-MHz DDR devices with max of 2 Double-Sided SO-DIMMs(4 rows populated) with unbuffered PC1600/PC2100 DDR(with ECC). Supports 128-Mb, 256-Mb and 512-Mbit technologies providing maximum capacity of 1-GB with only x 16 devices. All supported devices have 4 banks. Supports up to 16 simultaneous open pages. Supports page sizes of 2KB, 4KB, 8KB, and 16KB. Page size is individually selected for every row. UMA support only.

System Interrupt

12

8050 N/B Maintenance

Supports 8259 and Processor System Bus interrupt delivery mechanism Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface MSI sent to the CPU through the system Bus From IOxAPIC in ICH4-M Provides redirection for upstream interrupts to the System Bus Video Stream Decoder Improved HW Motion Compensation for MPEG2 All format decoder (18 ATSC formats) supported Dynamic Bob and Weave support for Video Streams Software DVD at 60 fields/second and 30 frames/second full screen Support for 720x480 pixel resolution DVD quality encoding at low CPU utilization Video Overlay Single high quality scalable overlay and second Sprite to support second overlay Multiple overlay functionality provided via Arithmetic Stretch Blt Direct YUV from Overlay to TV-out

13

8050 N/B Maintenance

Independent Gamma Correction Independent Brightness / Contrast / Saturation Independent Tint / Hue support Destination Color keying Source Chroma keying Maximum source resolution of 1920x1080 pixels Maximum overlay clock of 133 MHz/200 MHz provides a pixel resolution up to [email protected] 60Hz or [email protected] 85 Hz

Display

Analog Display Support 350 MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog monitor up to 1800x1350 @ 85 Hz accompanying I2C and DDC channels provided through multiplexed interface hot plug and display support Dual independent pipe with single display support Simultaneous: Same images and native display timings on each display device DVO (DVOB) support Digital video out port DVOB with 165-MHz dot clock on 12-bit interface

14

8050 N/B Maintenance

Variety of DVO devices channel Compliant with DVI Specification 1.0, thereby providing support for a flat panel up to 2048x1536 pixel resolution, or digital CRT up to 1920x1080 pixel resolution

1.3.4 I/O Controller Hub : INTEL 82801DBM

The INTEL 82801DBM ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers, the Audio Controller with AC 97 Interface, the IDE Master/Slave controllers, and Intel®' I/O Hub architecture. The PCI to LPC Bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O and legacy power management functionalities are integrated as well. The integrated Universal Serial Bus Host Controllers features Dual Independent UHCI Compliant Host controllers with six USB ports delivering 480 Mb/s bandwidth and rich connectivity. Besides, Legacy USB devices as well as over current detection are also implemented. The Integrated AC97 v2.3 compliance Audio Controller that features a 7-channels of audio speaker out and HSP v.90 modem support. Additionally, the AC97 interface supports 4 separate SDATAIN pins that is capable of supporting multiple audio codecs with one separate modem codec. The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode transfers up to 16 Mbytes/sec and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that sustain the high data transfer rate in the multitasking environment.

15

8050 N/B Maintenance

INTEL 82801DBM ICH4-M supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates the legacy system I/O like: two 82C37 compatible DMA controllers, Channels 0-3 are hardwired to 8 bit, three 8254 compatible programmable 16-bit counters channels 5-7, hardwired keyboard controller and PS2 mouse interface(not use in MiTAC 8050 model), Real Time clock with 512Bytes CMOS SRAM and two 82C59 compatible Interrupt controllers. Besides, the I/O APIC managing up to 14 interrupts with both Serial and FSB interrupt delivery modes is supported. The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2 compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for specific application. In addition, the INTEL 82801DBM ICH4-M supports Deeper Sleep power state for Intel Mobile processor. A high bandwidth and mature Intel®' I/O Hub architecture is incorporated to connect Montara and Intel 82801DBM ICH4-M Hub interface together. Intel®' I/O Hub architecture is developed.

1.3.5 Introducing MOBILITY M10 (Option)

The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics performance for notebooks. Its architecture introduces the latest achievements in the graphics industry, which enable the use of the progressive new features in upcoming applications, but without compromising performance. ATI's support of DirectX® 9 features, highly optimized OpenGL® support, and flexible memory configurations allow implementations targeted at the gaming enthusiast, consumer, business and workstation platforms.

16

8050 N/B Maintenance

SMARTSHADERTM 2.0 -- Advanced Shader Technology Provides complete hardware-accelerated support for the new DirectX® 9 programmable shader model, enabling more complex and realistic texture and lighting effects than ever before. Significant improvement over first-generation shaders introduced in DirectX® 8, with a much more powerful and intuitive instruction set. Offers full support for this feature in OpenGL® applications. MOOTHVISIONTM 2.0 -- Flexible Anti-Aliasing and Anisotropic Filtering 2x/4x/6x full-scene anti-aliasing modes Adaptive algorithm with programmable sample patterns 2x/4x/8x/16x anisotropic filtering modes Adaptive algorithm with bi-linear (performance) and tri-linear (quality) options High Performance Memory Support Incorporates support for DDR SDRAM/SGRAM. Features key items from ATI's third generation HYPER ZTM III technology that conserves memory bandwidth for improved performance in demanding applications. Dual Display Support

17

8050 N/B Maintenance

Leading-edge technology, fully optimized with HYDRA VISIONTM, flexibly supports multiple combinations of notebook LCD, traditional CRT monitors, flat panel displays and TV. Features Dual Channel DVI support. 230MHz LVDS transmitter supports LCD panels up to QXGA (2048x1536) resolution. Integrated 165MHz TMDS transmitter supports external flat panels up to UXGA (1600x1200) resolution. High performance DAC speeds of 400MHz. Features in Detail VIDEO Acceleration M10 allows the integration of industry leading digital video features, including advanced de-interlacing algorithms for unprecedented video quality and integrated digital TV decode capability. Includes programmable,independent gamma control for the video overlay. New FULLSTREAMTM technology removes blocky artifacts from streaming and Internet video and provides sharper image quality. Integrated general purpose xDCT engine (capable of performing both forward and inverse discrete cosine transform) and motion compensation (MC) support for the acceleration of MPEG encoding and decoding as well as DV (digital video) encoding and decoding.

18

8050 N/B Maintenance

1.3.6 TV CH7011

The CH7011 is a Display controller device which accepts a digital graphics input signal, and encodes and transmits data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable voltage data port which supports five different data formats including RGB and YCrCb.The TV-Out processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text display. Eight graphics resolutions are supported up to 1024 by 768 with full vertical and horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Support is provided for MacrovisionTM and RGB bypass mode which enables driving a VGA CRT with the input data.

Features

TV output supporting up to 1024x768 graphics resolutions Macro visionTM 7.X copy protection support Programmable digital interface supports RGB and YCrCb True scale rendering engine supports under scan in all TV output resolutions Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering Support for all NTSC and PAL formats

19

8050 N/B Maintenance

Provides CVBS, S-Video and SCART (RGB) outputs TV connection detect Programmable power management 10-bit video DAC outputs Fully programmable through serial port Complete Windows and DOS driver support Low voltage interface support to graphics device

1.3.7 AC'97 AUDIO SYSTEM: Advance Logic, Inc, ALC655

The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC multimedia systems,including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter technology to meet performance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of stereo outputs with 5-Bitvolume controls, a mono output, and multiple stereo and mono inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The digital interface circuitry of the ALC655 CODEC operates from a 3.3V power supply for use in notebook and PC applications. The ALC655 integrates 50mW/20ohm headset audio amplifiers at Front-Out and Surr-Out, built-in 14.318M 24.576MHz PLL and PCBEEP generator, those can save BOM costs. The ALC655

20

8050 N/B Maintenance

also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer electronic products, such as AC3 decoder/speaker and mini disk devices. ALC655 supports host/soft audio from Intel ICHx chipsets as well as audio controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows series drivers (Win XP/ME/2000/98/NT), EAX/Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities (supporting Karaoke, 26-kind of environment sound emulation,10-band equalizer), HRTF 3D positional audio and SensauraTM 3D (optional) provide an excellent entertainment package and game experience for PC users. Besides, ALC655 includes Realtek's impedance sensing techniques that makes device load on outputs and inputs can be detected. Meets performance requirements for audio on PC99/2001 systems Meets Microsoft WHQL/WLP 2.0 audio requirements 16-bit Stereo full-duplex CODEC with 48KHz sampling rate Compliant with AC'97 2.3 specifications Front-Out, Surround-Out, MIC-In and LINE In Jack Sensing 14.318MHz- 24.576MHz PLL to save crystal 12.288MHz BITCLK input can be consumed Integrated PCBEEP generator to save buzzer Interrupt capability

21

8050 N/B Maintenance

Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX High quality differential CD input Two analog line-level mono input: PCBEEP,PHONE-IN Two software selectable MIC inputs A dedicated Front-MIC input for front panel applications (software selectable) Boost preamplifier for MIC input shared with Center and LFE output Both Front-out and Surround-Out built-in LINE Input shared with surround output; MIC 50mW/20 amplifier

1.3.8 MDC:PCTEL MODEM DAUGHTER CARD PCT2303W (ASKEY V1456VQL-P1)

The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. Theof PC-TEL's well proven PCT2303W chipset and the HSP56TM MR software modem driver allows systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining higher system performance.

22

8050 N/B Maintenance

PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with the Pentium class processors, HSP becomes part of the host computer's system software. It requires less power to operate and less physical space than standard modem solutions. PC-TEL's HSP modem is an easily integrated, cost-effective communications solution that is flexible enough to carry you into the future. The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a programmable line interface to meet international telephone line requirements. The PCT2303W chip set is available in two 16-pin small outline packages (AC'97 interface on PCT303A and phone-line interface on PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to 4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve compliance with international regulatory requirements. The PCT2303W complies with AC'97 Interface specification Rev. 2.1. The chip set is fully programmable to meet world-wide telephone line interface requirements including those described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer threshold. The PCT2303W chip set has been designed to meet stringent world-wide requirements for out-of-band energy, billing-tone immunity, lightning surges, and safety requirements.

Features

Virtual com port with a DTE throughout up to 460.8Kbps. G3 Fax compatible

23

8050 N/B Maintenance

Auto dial and auto answer Ring detection

Codec/DAA Features

AC97 2.1 compliant 86dB dynamic range TX/RX paths 2-4-wire hybrid Integrated ring detector High voltage isolation of 4000V Support for "Caller ID" Compliant with FCC Part68, CTR21, Net4 and JATE Low power standby Low profile SOIC package 16 pins 10x3x1.55mm Low power consumption 10mA @ 3.3V operation

24

8050 N/B Maintenance

1mA @ 3.3V power down Integrated modem codec

Standard Features

Data ITU-T V.90 (56Kbps), V.34 (4.8Kbps TO 33.6 Kbps), V.32 bis (4.8Kbps to 14.4Kbps), V.22 bis (1.2 bps

to 2.4 Kbps), V.21 and Bell 103 and 212A(300 to 1200 bps) modulation protocol.

Data Compression ITU-T V.42bis MNP Class 5 Error Correction ITU-T V.42 LAPM MNP 2-4 Fax ITU-T V. 17, V.29, V.27ter, V.21, Channel 2, Group 3, EIA Class I

25

8050 N/B Maintenance

1.3.9 IEEE1394 VT6307L (Option)

1.3.9.1 Overview

The VT6307 IEEE 1394 OHCI Host Controller provides high performance serial connectivity. It implements the Link and Phy layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0 and 1394a-2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance data transfer via a 32-bit bus master PCI host bus interface. The VT6307 supports 100, 200 and 400 M bit/sec transmission via an integrated 2-port PHY. The VT6307 services two types of data packets: asynchronous and isochronous (real time). The 1394 link core performs arbitration requesting, packet generation and checking, and bus cycle master operations. It also has root node capability and performs retry operations. The VT6307 is ready to provide industry-standard IEEE 1394 peripheral connections for desktop and mobile PC platforms. Support for the VT6307 is built into Microsoft Windows 98, Windows ME, Windows 2000, and Windows XP.

1.3.9.2. Features

32 bit CRC generator and checker for receive and transmit data On-chip isochronous and asynchronous receive and transmit FIFOs for packets (2K for general receive plus 2K for isochronous transmit plus 2K for asynchronous transmit) 8 isochronous transmit contexts 4 isochronous receive contexts

26

8050 N/B Maintenance

3-deep physical post-write queue 2-deep physical response queue Dual buffer mode enhancements Skip Processing enhancements Block Read Request handling Ack_tardy processing

1.3.10 System Flash Memory (BIOS)

Firmware Hub for Intel® 810, 810E, 815, 815E,815EP, 820, 840, 850 Chipsets Flexible Erase Capability Uniform 4 K Byte Sectors Uniform 16 K Byte overlay blocks for SST49LF002A Uniform 64 K Byte overlay blocks for SST49LF004ATop boot block protection 16 K Byte for SST49LF002A

27

8050 N/B Maintenance

64 K Byte for SST49LF004A Chip-Erase for PP Mode Single 3.0-3.6V Read and Write Operations Superior Reliability Firmware Hub Hardware Interface Mode 5-signal communication interface supporting byte Read and Write 33 MHz clock frequency operation WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block Block Locking Register for all blocks Standard SDP Command Set Data# Polling and Toggle Bit for End-of-Write detection 5 GPI pins for system design flexibility 4 ID pins for multi-chip selection

28

8050 N/B Maintenance

1.3.11 Memory System

1.3.11.1 64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMM

JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM) Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components 64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); (64Meg x 64 [HD]) VDD= VDDQ= +2.5V ±0.2V VDDSPD = +2.2V to +5.5V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data--i.e.,source-synchronous data capture Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)

29

512MB

8050 N/B Maintenance

Four internal device banks for concurrent operation Selectable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD, MT8VDDT6464HD) maximum average periodic refresh interval Serial Presence Detect (SPD) with EEPROM Fast data transfer rates PC2100 or PC1600 Selectable READ CAS latency for maximum compatibility Gold-plated edge contacts

1.3.12 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHY Ceiver ,The ICS1893 is a low-power, physical-layer device (PHY)

General

The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications

30

8050 N/B Maintenance

and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management Interface (ACPI), PCI power management for modern operating systems that are capable of Operating System Directed Power Management (OSPM) to achieve the most efficient power management possible.The RTL8100C(L) does not support CardBus mode as the RTL8139C does. In addition to the ACPI feature, the RTL8100C(L) also supports remote wake-up (including AMD Magic Packet, LinkChg, and Microsoft® wakeupframe) in both ACPI and APM environments. The RTL8100C(L) is capable of performing an internal reset through the application of auxiliary power. When auxiliary power is applied and the main power remains off, the RTL8100C(L) is ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides 4 different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8100C(L) LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality. The RTL8100C(L) also supports Analog Auto-Power-down, that is, the analog part of the RTL8100C(L) can be shut down temporarily according to user requirements or when the RTL8100C(L) is in a power down state with the wakeup function disabled.In addition, when the analog part is shut down and the Isolate B pin is low (i.e. the main power is off), then both the analog and digital parts stop functioning and the power consumption of the RTL8100C(L) will be negligible. The RTL8100C(L) also supports an auxiliary power auto-detect function, and will auto-configure related bits of their own PCI power management registers in PCI configuration space. 128 pin QFP/LQFP Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip 10 Mb/s and 100 Mb/s operation Supports 10 Mb/s and 100 Mb/s N-way Auto-negotiation operation

31

8050 N/B Maintenance

PCI local bus single-chip Fast Ethernet controller Compliant to PCI Revision 2.2Supports PCI clock 16.75MHz-40MHz Supports PCI target fast back-to-back transaction Provides PCI bus master data transfers and PCI Memory space or I/O space mapped data transfers of RTL8100C(L)'s operational registers Supports PCI VPD (Vital Product Data) Supports ACPI, PCI power management Supports 25MHz crystal or 25MHz OSC as the internal Clock source. The frequency deviation of either crystal or OSC must be within 50 PPM. Compliant to PC99/PC2001 standard Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft® wakeup frame) Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse) Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains off

32

8050 N/B Maintenance

Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI configuration space. Includes a programmable, PCI burst size and early Tx/Rx threshold. Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate timer-interrupt Contains two large (2Kbyte) independent receive and transmit FIFOs Advanced power saving mode when LAN function or wakeup function is not used Uses 93C46 (64*16-bit EEPROM) to store resource configuration, ID parameter, and VPD data. Supports LED pins for various network activity indications Supports loopback capability Half/Full duplex capability Supports Full Duplex Flow Control (IEEE 802.3x)

33

8050 N/B Maintenance

2. System View and Disassembly

2.1 System View

2.1.1 Front View

1394 Jack Line Out Connector Line In Connector MIC In Connector SD Card Slot Top Cover Latch

2.1.2 Left-side View

VGA Port S-Video Port USB Ports *1 Ventilation Openings RJ-11 Connector RJ-45 Connector PCMCIA Card Socket

34

8050 N/B Maintenance

2.1.3 Right-side View

CD-ROM/DVD-ROM Drive Kensington Lock

2.1.4 Rear View

Kensington Lock Power Connector USB Port*2

35

8050 N/B Maintenance

2.1.5 Bottom View

Hard Disk Drive DDR SDRAM Card Wireless Card CPU Battery Park Stereo Speaker Set

2.1.6 Top-open View

LCD Screen Power Button Stereo Speaker Set Keyboard Device LED Indicators Touch Pad Hard Disk Drive Indicator Battery Power Charging Indicator Power Indicator

36

8050 N/B Maintenance

2.2 System Disassembly

The section discusses at length each major component for disassembly/reassembly and show corresponding illustrations.Use the chart below to determine the disassembly sequence for removing components from the notebook. NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power. 2.2.1 Battery Pack 2.2.2 Keyboard Modular Components 2.2.3 CPU 2.2.4 HDD Module 2.2.5 DVD-ROM Drive 2.2.6 Wireless Card NOTEBOOK 2.2.7 Modem Card 2.2.8 DDR-SDRAM 2.2.9 LCD Assembly LCD Assembly Components 2.2.10 LCD Panel 2.2.11 Inverter Board 2.2.12 System Board Base Unit Components 2.2.13 Touch Pad

37

8050 N/B Maintenance

2.2.1 Battery Pack

Disassembly 1. Carefully put the notebook upside down. 2. Slide the two release lever outwards to the "unlock" ( compartment ( ). (Figure 2-1) ) position ( ), while take the battery pack out of the

Figure 2-1 Remove the battery pack

Reassembly 1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a clicking sound. 2. Slide the release lever to the "lock" ( ) position.

38

8050 N/B Maintenance

2.2.2 Keyboard

Disassembly 1. Remove the battery pack. (Refer to section 2.2.1 Disassembly) 2. Open the top cover. 3. Loosen the four latches locking the keyboard. (Figure 2-2) 4. Slightly lift up the keyboard and disconnect the cable from the mother board, then separate the keyboard. (Figure 2-3)

Figure 2-2 Loosen the four latches

Figure 2-3 Disconnect the cable

Reassembly 1. Reconnect the keyboard cable and fit the keyboard back into place with four latches. 2. Replace the battery pack. (Refer to section 2.2.1 reassembly)

39

8050 N/B Maintenance

2.2.3 CPU

Disassembly 1. Remove the battery pack. (Refer to section 2.2.1 Disassembly) 2. Remove three screws fastening the heatsink cover. (Figure 2-4) 3. Remove three spring screws that secure the heatsink upon the CPU and disconnect the fan's power cord from system board. (Figure 2-5)

Figure 2-4 Remove three screws

Figure 2-5 Free the heatsink

40

8050 N/B Maintenance

4. To remove the existing CPU, Loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU. (Figure 2-6)

Figure 2-6 Remove the CPU

Reassembly 1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into the holes. Tighten the screw by a flat screwdriver to locking the CPU. 2. Connect the fan's power cord to the system board, fit the heatsink upon the CPU and secure with three spring screws. 3. Replace the CPU cover and secure with three screws. 4. Replace the battery pack. (Refer to section 2.2.1 reassembly)

41

8050 N/B Maintenance

2.2.4 HDD Module

Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly) 2. Remove two screws fastening the HDD compartment cover. (Figure 2-7) 3. Remove the one screw and slide the HDD module out of the compartment. (Figure 2-8)

Figure 2-7 Remove the HDD compartment cover

Figure 2-8 Remove HDD module

42

8050 N/B Maintenance

4. Remove four screws to separate the hard disk drive from the bracket, remove four screws. (Figure 2-9)

Figure 2-9 Remove hard disk drive

Reassembly 1. Attach the bracket to hard disk drive and secure with four screws. 2. Slide the HDD module into the compartment and secure with one screw. 3. Place the HDD compartment cover and secure with two screws. 4. Replace the battery pack. (Refer to section 2.2.1 reassembly)

43

8050 N/B Maintenance

2.2.5 CD/DVD-ROM Drive

Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly) 2. Remove one screw fastening the CD/DVD-ROM drive. (Figure 2-10) 3. Push firmly to release the tray. Then gently pull out the CD/DVD-ROM drive by holding the tray that pops out. (Figure 2-11)

Figure 2-10 Remove one screw

Figure 2-11 Remove the CD/DVDROM drive

Reassembly 1. Push the CD/DVD-ROM drive into the compartment and secure with one screw. 2. Replace the battery pack. (Refer to section 2.2.1 reassembly)

44

8050 N/B Maintenance

2.2.6 Wireless Card

Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to sections 2.2.1 Disassembly) 2. Remove the two screws fastening the Mini PCI compartment cover. (Figure 2-12) 3. Disconnect the wireless card's antennae first ( ). Then pull the retaining clips outwards ( ) and remove the wireless card ( ). (Figure 2-13)

Figure 2-12 Remove two screws

Figure 2-13 Remove the Wireless card

Reassembly 1. To install the wireless card, match the wireless card 's notched part with the socket's projected part and firmly insert it into the socket. Then push down until the retaining clips lock the wireless card into position. Then sure that the antennae fully populated. 2. Tighten the screws to secure the wireless card compartment cover to the housing. 3. Replace the battery pack. (Refer to section 2.2.1 reassembly)

45

8050 N/B Maintenance

2.2.7 Modem Card

Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly) 2. Remove two screws fastening modem card's compartment cover. (Refer to steps 1-2 of section 2.2.6 Disassembly) 3. Remove two screws fastening the modem card. (Figure 2-14) 4. Lift up the modem card and disconnect the cord. (Figure 2-15)

Figure 2-14 Remove two screws

Figure 2-15 Disconnect the cord

Reassembly 1. Reconnect the cord and fit the modem card. 2. Fasten the modem card by two screws. 3. Replace the modem card's compartment cover by two screws. (Refer to step 2 of section 2.2.6 reassembly). 4. Replace the battery pack. (Refer to section 2.2.1 reassembly)

46

8050 N/B Maintenance

2.2.8 DDR-SDRAM

Disassembly 1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly) 2. Remove two screws fastening the DDR compartment cover to access the SO-DIMM socket. (Figure 2-16)

Figure 2-16 Remove the cover

Figure 2-17 Remove the SO-DIMM

3. Pull the retaining clips outwards ( ) and remove the SO-DIMM ( ). (Figure 2-17)

Reassembly 1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR into position. 2. Replace two screws to fasten the DDR compartment cover. 3. Replace the battery pack. (See section 2.2.1 reassembly)

47

8050 N/B Maintenance

2.2.9 LCD ASSY

Disassembly 1. Remove the battery pack, keyboard,CPU, hard disk drive, CD/DVD-drive and wireless card. (See sections 2.2.1,2.2.2, 2.2.3, 2.2.4, 2.2.5 and 2.2.6 Disassembly) 2. Remove the nineteen screws on the bottom of notebook. (Figure 2-18) 3. Remove the four screws that secure the hinge cover. (Figure 2-19)

Figure 2-18 Remove nineteen screws

Figure 2-19 Remove four screws

48

8050 N/B Maintenance

4. Remove the two screws and disconnect the touch pad's cable, then free the top cover.(Figure 2-20) 5. Remove the two hinge covers. (Figure 2-21)

Figure 2-20 Free the Top cover

Figure 2-21 Remove the hinge covers

49

8050 N/B Maintenance

6. Disconnect the two cables and remove the four screws. (Figure 2-22) 7. Remove the eight screws. (Figure 2-23)

Figure 2-22 Remove the four screws and Disconnect the two cables

Figure 2-23 Remove the eight screws

50

8050 N/B Maintenance

8. Carefully pull the antenna wires out. Now you can lift up the LCD ASSY from base unit. (Figure 2-24)

Figure 2-24 Free the LCD ASSY

Reassembly 1. Attach the LCD assembly to the base unit and secure with four screws. 2. Rip the antenna wires back into Min-PCI compartment. 3. Reconnect the two cables to the system board. Screw the hinge covers by two screws. 4. Replace the shield and secure with eight screws. 5. Replace the top cover and secure with two screws. And reconnect the touch pad's cable. 6. Upside down the notebook. secure the housing by nineteen screws and secure two screws in the rear. 7. Replace the Wireless card, CD/DVD-ROM, hard disk drive, CPU, keyboard and battery pack. (Refer to sections 2.2.6, 2.2.5, 2.2.4, 2.2.3, 2.2.2 and 2.2.1 reassembly)

51

8050 N/B Maintenance

2.2.10 LCD Panel

Disassembly 1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive and LCD assembly. (Refer to section 2.2.1, 2.2.2, 2.2.4, 2.2.5 and 2.2.9 Disassembly) 2. Remove the two rubber pads and two screws on the corners of the panel. (Figure 2-25) 3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process until the cover is completely separated from the housing. 4. Remove the twelve screws and disconnect the cable. (Figure 2-26)

Figure 2-25 Remove LCD cover

Figure 2-26 Remove twelve screws and disconnect the cable

52

8050 N/B Maintenance

5. Remove the six screws that secure the LCD bracket. (Figure 2-27) 6. Disconnect the cable to free the LCD panel. (Figure 2-28)

Figure 2-27 Remove the six screws

Figure 2-28 Free the LCD panel

Reassembly 1. Replace the cable to the LCD. 2. Attach the LCD panel's bracket back to LCD panel and secure with six screws. 3. Replace the LCD panel into LCD housing.and reconnect two cables to inverter board and secure with two screws. 4. Fasten the LCD panel by ten screws. 5. Fit the LCD cover and secure with two screws and rubber pads. 6. Replace the LCD assembly, CD/DVD-ROM drive, hard disk drive, keyboard, battery pack. (See sections 2.2.9, 2.2.5, 2.2.4, 2.2.2, and 2.2.1 reassembly)

53

8050 N/B Maintenance

2.2.11 Inverter Board

Disassembly 1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive and LCD assembly. (Refer to section 2.2.1, 2.2.2, 2.2.4, 2.2.5 and 2.2.9 Disassembly) 2. Remove the LCD cover and LCD panel. (Refer to the steps 1-4 of section 2.2.10 Disassembly ) 3. Remove the one screw fastening the inverter board and disconnect the cable, Then free the inverter board. (Figure 2-29)

Figure 2-29 Free the inverter board

Reassembly 1. Reconnect the cable. Fit the inverter board back into place and secure with one screw. 2. Replace the LCD Panel and LCD cover. (Refer to section 2.2.10 reassembly) 3. Replace the LCD assembly. (Refer to section 2.2.9 reassembly) 4. Replace the CD/DVD-ROM drive, hard disk drive, keyboard and battery pack. (Refer to sections 2.2.5, 2.2.4, 2.2.2 and 2.2.1 reassembly)

54

8050 N/B Maintenance

2.2.12 System Board

Disassembly 1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive, Wireless card and LCD assembly. (Refer to sections 2.2.1, 2.2.2, 2.2.4, 2.2.5, 2.2.6 and 2.2.9 Disassembly) 2. Remove the four screws that secure the system board and disconnect the two speaker's cables. Then lift it up from the housing. (Figure 2-30) 3. Disconnect the one speaker's cables from the system board and remove the two screws, Then separate the bracket and free the system board. (Figure 2-31)

Figure 2-30 Remove four screws and disconnect the two cables

Figure 2-31 Free the system board

Reassembly 1. Fit the bracket and secure with two screws . 2. Turn over the system board. Reconnect the speaker's cords. 3. Replace the system board back into the housing and secure with four screws, then reconnect the cable. 4. Replace the LCD assembly, CD/DVD-ROM, HDD, keyboard and battery pack. (Refer to previous section reassembly)

55

8050 N/B Maintenance

2.2.13 Touch Pad

Disassembly 1. Remove the battery pack, keyboard, hard disk drive and CD/DVD-drive. (See sections 2.2.1,2.2.2 , 2.2.4 and 2.2.5 Disassembly) 2. Remove the top cover. (See steps 1-5 in section 2.2.9 Disassembly) 3. Remove the two screws and free the touch pad. (Figure 2-32).

Figure 2-32 Remove the two screws

Reassembly 1. Replace the touch pad and secure the two screws. 2. Replace the top cover. (Refer to the section in 2.2.9 reassembly) 3. Replace the battery pack, keyboard, hard disk drive and CD/DVD-drive. (See sections 2.2.1,2.2.2 , 2.2.4 and 2.2.5 Disassembly).

56

8050 N/B Maintenance

3. Definition & Location of Connectors / Switches

3.1 Mother Board - A

J3 J2 J1 SW2

J1 : Inverter Board Connector J2 : LCD panel connector J3 : Internal Left Speaker Connector J4 : Touch-pad Module Connector J5 : Internal Key-board Connector J6 : PCMCIA Card Connector J7 : Internal Right Speaker Connector

J6

SW4

J5

SW2 : Power Button

J7 SW5 J4

SW4 : Left Button Switch of Touch-pad SW5 : Right Button Switch of Touch-pad

57

8050 N/B Maintenance

3. Definition & Location of Connectors / Switches

3.2 Mother Board - B

J706 J702 J704 J709

PJ701 : AC Adaptor Connector J701&J706 : USB Port Connector J702 : CRT Connector

J701

J713

J703 : Battery Connector

PJ701

J704 : External VGA Connector J705 : Internal Subwoofer Speaker

J707

J707: FAN Connector J708 : CD-ROM IDE Connector J709: Lan & Phone Lan Connector

J711 J712

J710 : RTC Battery Connector J711&J712 : DDR SO-DIMM Module Socket J713 : Mini-PCI Connector

J703 J710 J705 J708 J714

J714 : Hard Disk Driver Connector -----To next page-----

58

8050 N/B Maintenance

3. Definition & Location of Connectors / Switches

3.2 Mother Board - B

-----Continue From Previous Page----J715 J717

J715&J717: Modem Daughter Board Connector J716 : SD&MS Card Socket J718 : IEEE 1394 Connector J719 : External Micro Phone Jack J720 : Line Out HP/OPT Jack

J718

J721 : External Line-in Jack

J720 J721 J719

J716

59

8050 N/B Maintenance

4. Definition & Location of Major Components

4.1 Mother Board - A

PU2 : +3VS/+5VS Voltage Generator PU3 : CPU Core Voltage Generator PU14: +1.8V/+1.35V Voltage Generator

PU2

PU15 : +2.5VS/+1.25V Voltage Generator U2 : TV Encoder Controller U15: SYS BIOS Controller U16: WINBOND KBC Controller

PU3

U15 U524

U524: TPA02012 Audio Amplifier

PU15 U2 U16 PU14

60

8050 N/B Maintenance

4. Definition & Location of Major Components

4.2 Mother Board - B

U706 : Thermal Sensor/Fan Controller U713 : Intel BANIAS CPU

U719

U714 : Intel 855GM/GME North Bridge U715 : Intel ICH4-M South Bridge

U727 U713 U706

U724

U719 : LAN-RTL8100CL Controller U724 : IEEE1394 Controller U725 : SUBWOOFER AMP Controller U726 : Audio CODEC(ALC655)

U714

U727 : CB710 Card Bus Reader Controller

U725 U726

U715

61

8050 N/B Maintenance

5. Pin Descriptions of Major Components

5.1 Intel Banias Pentium M Processor(1)

Signal Name A[31:3]# Type I/O Description A[31:3]# (Address) define a 2 32 -byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel Pentium M processor system bus. A[31:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. Signals Associated Strobe REQ[4:0]#, A[16:3]# ADSTB[0]# A[31:17]# ADSTB[1]# The differential pair BCLK (Bus Clock) determines the system bus frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs. BNR# (Block Next Request) is used to assert a bus stall by any bus agent that is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Intel Pentium M processor system bus agents. This includes debug or performance monitoring tools.

Signal Name BPRI#

Type I

Description

BR0#

A20M#

I

COMPP3:0]

D[63:0]#

ADS#

I/O

ADSTB[1:0]#

I/O

BCLK[1:0]

I

BNR#

I/O

BPM[2:0]# BPM[3]

O I/O

DBR#

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of both processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. I/O BR0# is used by the processor to request the bus. The arbitration is done between the Intel Pentium M processor (Symmetric Agent) and the MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM chipset. Analog COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Refer to the platform design guides for more implementation details. I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups Data Group DSTBN#/DSTBP# DINV# D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3 Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. O DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect. DBR# is not a processor signal.

62

8050 N/B Maintenance

5.1 Intel Banias Pentium M Processor(2)

Signal Name DBSY# Type I/O Description DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both processor system bus agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both processor system bus agents. DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment To Data Bus Bus Signal Data Bus Signals DINV[3]# D[63:48]# DINV[2]# D[47:32]# DINV[1]# D[31:16]# DINV[0]# D[15:0]# DPSLP# when asserted on the platform causes the processor to transition from the Sleep state to the Deep Sleep state. In order to return to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and also connects to the MCH-M component of the Intel 855PM or Intel 855GM chipset. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both processor system bus agents. Data strobe used to latch in D[63:0]#. Signals Associated Strobe D[15:0]#, DINV[0]# DSTBN[0]# D[31:16]#, DINV[1]# DSTBN[1]# D[47:32]#, DINV[2]# DSTBN[2]# D[63:48]#, DINV[3]# DSTBN[3]# Data strobe used to latch in D[63:0]#. Signals Associated Strobe D[15:0]#, DINV[0]# DSTBP[0]# D[31:16]#, DINV[1]# DSTBP[1]# D[47:32]#, DINV[2]# DSTBP[2]# D[63:48]#, DINV[3]# DSTBP[3]#

Signal Name DPWR#

Type I

Description DPWR# is a control signal from the Intel 855PM and Intel 855GM chipsets used to reduce power on the Intel Pentium M data bus input buffers. FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 80387 coprocessor, and is included for compatibility with systems using MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP . GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. REQ[4:0]# (Request Command) must connect the appropriate pins of both processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#.

FERR#/PBE#

O

DEFER#

I

DINV[3:0]#

I/O

GTLREF

I

DPSLP#

I

HIT# HITM#

I/O I/O

IERR#

O

DRDY#

I/O

IGNNE#

I

DSTBN[3:0]#

I/O

DSTBP[3:0]#

I/O

REQ[4:0]#

I/O

63

8050 N/B Maintenance

5.1 Intel Banias Pentium M Processor(3)

Signal Name INIT# Type I Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power on Reset vector configured during power on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST) LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured using BIOS programming of the APIC register space and used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. Probe Ready signal used by debug tools to determine processor debug readiness. Probe Request signal used by debug tools to request debug operation of the processor. PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal may require voltage translation on the motherboard. Processor Power Status Indicator signal. This signal is asserted when the processor is in a lower state (Deep Sleep and Deeper Sleep).

Signal Name PWRGOOD

Type I

Description PWRGOOD (Power Good) is a processor input. The processor requires this signal as a clean indication that the clocks and power supplies are stable and within their specifications. `Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout the boundary scan operation. ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects. These are not processor signals. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both system bus agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both processor system bus agents. These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. Please refer to the platform design guides for more details. SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state.

LINT[1:0]

I

ITP_CLK[1:0]

I

RESET#

I

LOCK#

I/O

RS[2:0]#

I

RSVD

-

PRDY# PREQ# PROCHOT#

O I O

SLP#

I

PSI#

O

64

8050 N/B Maintenance

5.1 Intel Banias Pentium M Processor(4)

Signal Name SMI# Type I Description

Signal Name VCC VCCA[3:0] VCCP VCCQ[1:0] Type I I I I Description Processor core power supply. VCCA provides isolated power for the internal processor core PLL's. Processor I/O Power Supply. Quiet power supply for on die COMP circuitry. These pins should be connected to VCCP on the motherboard. However, these connections should enable addition of decoupling on the VCCQ lines if necessary. VCCSENSE is an isolated low impedance connection to processor core power (VCC ). It can be used to sense or measure power near the silicon with little noise. VID[5:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (Vcc). Unlike some previous generations of processors, these are CMOS signals that are driven by the Intel Pentium M processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise.

STPCLK#

TCK TDI TDO TEST1, TEST2, TEST3 THERMDA THERMDC THERMTRIP#

TMS TRDY#

TRST#

SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. I STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. I TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). I TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. I TEST1, TEST2, and TEST3 must be left unconnected but should have a stuffing option connection to V SS separately using 1-k, pull-down resisitors. Other Thermal Diode Anode. Other Thermal Diode Cathode. O The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. I TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. I TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both system bus agents. I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.

VCCSENSE

O

VID[5:0]

O

VSSSENSE

O

65

8050 N/B Maintenance

5.2 Intel 855GM/GME North Bridge(1)

Host Interface Signal Descriptions

Signal Name ADS# Type I/O AGTL+ Description Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. The GMCH can assert this signal for snoop cycles and interrupt messages. Block Next Request: Used to block the current request bus owner from issuing a new request. This signal is used to dynamically control the CPU bus pipeline depth. Bus Priority Request: The GMCH is the only Priority Agent on the system bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted. Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal low during CPURST#. The signal is sampled by the processor on the active-to-inactive transition of CPURST#. The minimum setup time for this signal is 4 BCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 BCLKs. BREQ0# should be tristated after the hold time requirement has been satisfied. During regular operation, the GMCH will use BREQ0# as an early indication for FSB Address and Ctl input buffer and sense amp activation. CPU Reset: The CPURST# pin is an output from the GMCH. The GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M) is asserted and for approximately 1 ms after RESET# is deasserted. The CPURST# allows the processor to begin execution in a known state. Note that the ICH4-M must provide CPU strap set-up and hold-times around CPURST#. This requires strict synchronization between GMCH, CPURST# deassertion and ICH4-M driving the straps. Data Bus Busy: Used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer: GMCH will generate a deferred response as defined by the rules of the GMCH's Dynamic Defer policy. The GMCH will also use the DEFER# signal to indicate a CPU retry response.

Signal Name DINV[3:0]#

Type I/O AGTL+

Description Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. Indicates if the associated signals are inverted or not. DINV[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit group never exceeds 8. DINV# Data Bits DINV[3]# HD[63:48]# DINV[2]# HD[47:32]# DINV[1]# HD[31:16]# DINV[0]# HD[16:0]# Deep Sleep #: This signal comes from the ICH4-M device, providing an indication of C3 and C4 state control to the CPU. Deassertion of this signal is used as an early indication for C3 and C4 wake up (to active HPLL). Note that this is a low-voltage CMOS buffer operating on the FSB VTT power plane. Data Ready: Asserted for each cycle that data is transferred. Host Address Bus: HA[31:3]# connects to the CPU address bus. During processor cycles the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during snoop cycles on behalf of Hub interface. HA[31:3]# are transferred at 2x rate. Note that the address is inverted on the CPU bus. Host Address Strobe: HA[31:3]# connects to the CPU address bus. During CPU cycles, the source synchronous strobes are used to transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate. Strobe Address Bits HADSTB[0]# HA[16:3]#, HREQ[4:0]# HADSTB[1]# HA[31:17]# Host Data: These signals are connected to the CPU data bus. HD[63:0]# are transferred at 4x rate. Note that the data signals are inverted on the CPU bus.

BNR#

I/O AGTL+ O AGTL+

BPRI#

DPSLP#

I CMOS

BREQ0#

I/O AGTL+

DRDY# HA[31:3]#

I/O AGTL+ I/O AGTL+

CPURST#

O AGTL+

HADSTB[1:0]#

I/O AGTL+

HD[63:0]#

I/O AGTL+

DBSY# DEFER#

I/O AGTL+ O AGTL+

66

8050 N/B Maintenance

5.2 Intel 855GM/GME North Bridge(2)

Host Interface Signal Descriptions (Continued)

Signal Name HDSTBP[3:0]# HDSTBN[3:0]# Type I/O AGTL+ Description Differential Host Data Strobes: The differential source synchronous strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x transfer rate. Strobe Data Bits HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]# HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, DINV[2]# HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, DINV[1]# HDSTBP[0]#, HDSTBN[0]# HD[15:0]#, DINV[0]# Hit: Indicates that a caching agent holds an unmodified version of the requested line. Also, driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified: Indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. Also, driven in conjunction with HIT# to extend the snoop window. Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic, i.e. no Hub interface snoopable access to system memory is allowed when HLOCK# is asserted by the CPU. Host Request Command: Defines the attributes of the request. HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting agent during both halves of the Request Phase. In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type. The transactions supported by the GMCH Host Bridge are defined in the Host Interface section of this document. Host Target Ready: Indicates that the target of the processor transaction is able to enter the data transfer phase. Response Status: Indicates the type of response according to the following the table: RS[2:0]# Response type 000 Idle state 001 Retry response 010 Deferred response 011 Reserved (not driven by GMCH) 100 Hard Failure (not driven by GMCH) 101 No data response 110 Implicit Write back 111 Normal data response

DDR SDRAM Interface Descriptions

Signal Name SCS[3:0]# Type O SSTL_2 Description Chip Select: These pins select the particular DDR SDRAM components during the active state. NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These signals can be toggled on every rising System Memory Clock edge (SCMDCLK). Multiplexed Memory Address: These signals are used to provide the multiplexed row and column address to the DDR SDRAM. Bank Select (Memory Bank Address): These signals define which banks are selected within each DDR SDRAM row. The SMA and SBA signals combine to address every possible location within a DDR SDRAM device. DDR Row Address Strobe: SRAS# may be heavily loaded and requires tw0 DDR SDRAM clock cycles for setup time to the DDR SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define the system memory commands. DDR Column Address Strobe: SCAS# may be heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs. Used with SRAS# and SWE# (along with SCS#) to define the system memory commands. Write Enable: Used with SCAS# and SRAS# (along with SCS#) to define the DDR SDRAM commands. SWE# is asserted during writes to DDR SDRAM. SWE# may be heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs. Data Lines: These signals are used to interface to the DDR SDRAM data bus. NOTE: ECC error detection is supported: by the SDQ[71:64] signals.

SMA[12:0] SBA[1:0]

HIT#

I/O AGTL+ I/O AGTL+

O SSTL_2 O SSTL_2

HITM#

SRAS#

O SSTL_2

HLOCK#

I/O AGTL+

SCAS#

O SSTL_2

HREQ[4:0]#

I/O AGTL+

SWE#

O SSTL_2

SDQ[71:0]

I/O SSTL_2

HTRDY# RS[2:0]#

O AGTL+ O AGTL+

67

8050 N/B Maintenance

5.2 Intel 855GM/GME North Bridge(3)

DDR SDRAM Interface Descriptions (Continued)

Signal Name SDQS[8:0] Type I/O SSTL_2 Description Data Strobes: Data strobes are used for capturing data. During writes, SDQS is centered on data. During reads, SDQS is edge aligned with data. The following list matches the data strobe with the data bytes. There is an associated data strobe (DQS) for each data signal (DQ) and check bit (CB) group. SDQS[7] -> SDQ[63:56] SDQS[6] -> SDQ[55:48] SDQS[5] -> SDQ[47:40] SDQS[4] -> SDQ[39:32] SDQS[3] -> SDQ[31:24] SDQS[2] -> SDQ[23:16] SDQS[1] -> SDQ[15:8] SDQS[0] -> SDQ[7:0] NOTE: ECC error detection is supported by the SDQS[8] signal. Clock Enable: These pins are used to signal a self-refresh or power down command to the DDR SDRAM array when entering system suspend. SCKE is also used to dynamically power down inactive DDR SDRAM rows. There is one SCKE per DDR SDRAM row. These signals can be toggled on every rising SCK edge. Memory Address Copies: These signals are identical to SMA[5,4,2,1] and are used to reduce loading for selective CPC(clock-per-command). These copies are not inverted. Data Mask: When activated during writes, the corresponding data groups in the DDR SDRAM are masked. There is one SDM for every eight data lines. SDM can be sampled on both edges of the data strobes. NOTE: ECC error detection is supported by the SDM[8] signal. Clock Output: Reserved, NC. Clock Input: Reserved, NC.

AGP Addressing Signal Descriptions

Signal Name GPIPE# Type I AGP Description Pipelined Read: This signal is asserted by the AGP master to indicate a full width address is to be enqueued on by the target using the AD bus. One address is placed in the AGP request queue on each rising clock edge while PIPE# is asserted. When PIPE# is deasserted no new requests are queued across the AD bus. During SBA Operation: This signal is not used if SBA (Side Band Addressing) is selected. During FRAME# Operation: This signal is not used during AGP FRAME# operation. PIPE# is a sustained tri-state signal from masters (graphics controller), and is an input to the GMCH. I Side-band Address: These signals are used by the AGP master GSBA[7:0] AGP (graphics controller) to pass address and command to the GMCH. The SBA bus and AD bus operate independently. That is, transactions can proceed on the SBA bus and the AD bus simultaneously. During PIPE# Operation: These signals are not used during PIPE# operation. During FRAME# Operation: These signals are not used during AGP FRAME# operation. NOTE: When sideband addressing is disabled, these signals are isolated (no external/internal pull-ups are required). 5 contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is used to queue addresses the master isnot allowed to queue addresses using the SBA bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism, but rather a static decision when the device is first being configured after reset

SCKE[3:0]

O SSTL_2

SMAB[5,4,2,1]

O SSTL_2 O SSTL_2

SDM[8:0]

RCVENOUT# RCVENIN#

O SSTL_2 O SSTL_2

68

8050 N/B Maintenance

5.2 Intel 855GM/GME North Bridge(4)

AGP Status Signal Descriptions

Signal Name GST[2:0] Type O AGP Status: Provides information from the arbiter to an AGP Master on what it may do. ST[2:0] only have meaning to the master when its GNT# is asserted. When GNT# is deasserted these signals have no meaning and must be gnored. ST[2:0 000 Description Meaning Previously requested low priority read data is being returned to the master arbiter to an AGP

AGP Flow Control Signals

Signal Name GRBF# Type I AGP Description Read Buffer Full: Read buffer full indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted the GMCH is not allowed to initiate the return low priority read data. That is, the GMCH can finish returning the data for the request currently being serviced. RBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept return read data then it is not required to implement this signal. During FRAME# Operation: This signal is not used during AGP FRAME# operation. Write-Buffer Full: indicates if the master is ready to accept Fast Write data from the GMCH. When WBF# is asserted the GMCH is not allowed to drive Fast Write data to the AGP master. WBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept fast write data then it is not required to implement this signal. During FRAME# Operation: This signal is not used during AGP FRAME# operation.

001

010

011

100 101 110

Previously requested high priority read data is being returned to the master The master is to provide low priority write data for a previously queued write command The master is to provide high priority write data for a previously queued write command. Reserved Reserved Reserved

GWBF#

I AGP

111

The master has been given permission to start a bus transaction. The master may queue AGP requests by asserting PIPE# or start a PCI transaction by asserting FRAME#

69

8050 N/B Maintenance

5.2 Intel 855GM/GME North Bridge(5)

AGP/PCI Signals-Semantics Descriptions

Signal Name GFRAME# Type I/O AGP Description G_FRAME: Frame. During PIPE# and SBA Operation: Not used by AGP SBA and PIPE# operations. During Fast Write Operation: Used to frame transactions as an output during Fast Writes. During FRAME# Operation: G_FRAME# is an output when the GMCH acts as an initiator on the AGP Interface. G_FRAME# is asserted by the GMCH to indicate the beginning and duration of an access. G_FRAME# is an input when the GMCH acts as a FRAME#-based AGP target. As a FRAME#-based AGP target, the GMCH latches the C/BE[3:0]# and the AD[31:0] signals on the first clock edge on which GMCH samples FRAME# active. G_IRDY#: Initiator Ready. During PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions. During FRAME# Operation: G_IRDY# is an output when GMCH acts as a FRAME#-based AGP initiator and an input when the GMCH acts as a FRAME#-based AGP target. The assertion of G_IRDY# indicates the current FRAME#-based AGP bus initiator's ability to complete the current data phase of the transaction. During Fast Write Operation: In Fast Write mode, G_IRDY# indicates that the AGP-compliant master is ready to provide all write data for the current transaction. Once G_IRDY# is asserted for a write operation, the master is not allowed to insert wait states. The master is never allowed to insert a wait state during the initial data transfer (32 bytes) of a write transaction. However, it may insert wait states after each 32-byte block is transferred.

AGP Strobe Descriptions

Signal Name GADSTB[0] Type I/O AGP I/O AGP Description Address/Data Bus Strobe-0: provides timing for 2x and 4x data on AD[15:0] and C/BE[1:0]# signals. The agent that is providing the data will drive this signal. Address/Data Bus Strobe-0 Complement: With AD STB0, forms a differential strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals. The agent that is providing the data will drive this signal. Address/Data Bus Strobe-1: Provides timing for 2x and 4x data on AD[31:16] and C/BE[3:2]# signals. The agent that is providing the data will drive this signal. Address/Data Bus Strobe-1 Complement: With AD STB1, forms a differential strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is providing the data will drive this signal. Sideband Strobe: Provides timing for 2x and 4x data on the SBA[7:0] bus. It is driven by the AGP master after the system has been configured for 2x or 4x sideband address mode. Sideband Strobe Complement: The differential complement to the SB_STB signal. It is used to provide timing 4x mode.

GADSTB#[0]

GADSTB[1]

I/O AGP I/O AGP

GADSTB#[1]

GIRDY#

I/O AGP

GSBSTB

I AGP I AGP

GSBSTB#

70

8050 N/B Maintenance

5.2 Intel 855GM/GME North Bridge(6)

AGP/PCI Signals-Semantics Descriptions (Continued)

Signal Name GTRDY# Type I/O AGP Description G_TRDY#: Target Ready. During PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions. During FRAME# Operation: G_TRDY# is an input when the GMCH acts as an AGP initiator and is an output when the GMCH acts as a FRAME#-based AGP target. The assertion of G_TRDY# indicates the target's ability to complete the current data phase of the transaction. During Fast Write Operation: In Fast Write mode, G_TRDY# indicates the AGP-compliant target is ready to receive write data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert wait states after each block (32 bytes) is transferred on write transactions. G_STOP#: Stop. During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA operation. During FRAME# Operation: G_STOP# is an input when the GMCH acts as a FRAME#-based AGP initiator and is an output when the GMCH acts as a FRAME#-based AGP target. G_STOP# is used for disconnect, retry, and abort sequences on the AGP interface. G_ DEVSEL#: Device Select. During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA operation. During FRAME# Operation: G_DEVSEL#, when asserted, indicates that a FRAME#-based AGP target device has decoded its address as the target of the current access. The GMCH asserts G_DEVSEL# based on the DDR SDRAM address range being accessed by a PCI initiator. As an input, G_DEVSEL# indicates whether the AGP master has recognized a PCI cycle to it. G_REQ#: Request. During SBA Operation: This signal is not used during SBA operation. During PIPE# and FRAME# Operation: G_REQ#, when asserted, indicates that the AGP master is requesting use of the AGP interface to run a FRAME#- or PIPE#-based operation.

Signal Name GGNT#

Type O AGP

Description

GSTOP#

I/O AGP

GDEVSEL#

I/O AGP

GREQ#

I AGP

G_GNT#: Grant. During SBA, PIPE# and FRAME# Operation: G_GNT#, along with the information on the ST[2:0] signals (status bus), indicates how the AGP interface will be used next. Refer to the AGP Interface Specification, Revision 2.0 for further explanation of the ST[2:0] values and their meanings. I/O GAD[31:0] G_AD[31:0]: Address/Data Bus. AGP During PIPE# and FRAME# Operation: The G_AD[31:0] signals are used to transfer both address and data information on the AGP interface. During SBA Operation: The G_AD[31:0] signals are used to transfer data on the AGP interface. I/O Command/Byte Enable. GCBE#[3:0] During FRAME# Operation: During the address phase of a AGP transaction, the G_CBE[3:0]# signals define the bus command. During the data phase, the G_CBE[3:0]# signals are used as byte enables. The byte enables determine which byte lanes carry meaningful data. The commands issued on the G_CBE# signals during FRAME#-based AGP transactions are the same G_CBE# command described in the PCI 2.2 specification. During PIPE# Operation: When an address is enqueued using PIPE#, the C/BE# signals carry command information. The command encoding used during PIPE#-based AGP is different than the command encoding used during FRAME#-based AGP cycles (or standard PCI cycles on a PCI bus). During SBA Operation: These signals are not used during SBA operation. I/O GPAR Parity. AGP During FRAME# Operation: G_PAR is driven by the GMCH when it acts as a FRAME#-based AGP initiator during address and data phases for a write cycle, and during the address phase for a read cycle. G_PAR is driven by the GMCH when it acts as a FRAME#-based AGP target during each data phase of a FRAME#-based AGP memory read cycle. Even parity is generated across G_AD[31:0] and G_CBE[3:0]#. During SBA and PIPE# Operation: This signal is not used during SBA and PIPE# operation. PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP interface logic within the GMCH. The AGP agent will also typically use PCIRST# provided by the ICH4-M as an input to reset its internal logic.

71

8050 N/B Maintenance

5.2 Intel 855GM/GME North Bridge(7)

Hub Interface Signals

Signal Name HL[10:0] HLSTB HLSTB# Type I/O Hub I/O Hub I/O Hub Description Packet Data: Data signals used for HI read and write operations. Packet Strobe: One of two differential strobe signals used to transmit or receive packet data over HI. Packet Strobe Complement: One of two differential strobe signals used to transmit or receive packet data over HI.

DVOBHSYNC O DVO O DVO

Digital Video Output B (DVOB) Port Signal Descriptions

Name DVOBD[11:0] O DVO Type Description DVOB Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOBCLK and DVOBCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the lower 12-bits of pixel data. DVOBD[11:0] should be left as left as NC ("Not Connected") if not used. Horizontal Sync: HSYNC signal for the DVOB interface. DVOBHSYNC should be left as left as NC ("Not Connected") if not used. Vertical Sync: VSYNC signal for the DVOB interface. DVOBVSYNC should be left as left as NC ("Not Connected") if the signal is NOT used when using internal graphics device. Flicker Blank or Border Period Indication: DVOBBLANK# is a programmable output pin driven by the GMCH. When programmed as a blank period indication, this pin indicates active pixels excluding the border. When programmed as a border period indication, this pin indicates active pixel including the border pixels. DVOBBLANK# should be left as left as NC ("Not Connected") if not used. TV Field and Flat Panel Stall Signal. This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel. DVOB TV Field Signal: When used as a Field input, it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source. DVOB Flat Panel Stall Signal: When used as the Stall input, it indicates that the pixel pipeline should stall one horizontal line. The signal changes during horizontal blanking. The panel fitting logic, when expanding the image vertically, uses this. DVOBFLDSTL needs to be pulled down if not used.

DVOBVSYNC

Dedicated LVDS LCD Flat Panel Interface Signal Descriptions

Name ICLKAP ICLKAM IYAP[3:0] IYAM[3:0] ICLKBP ICLKBM IYBP[3:0] IYBM[3:0] Type O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS Voltage 1.25 V± 225 mV 1.25 V±225 mV 1.25 V±225 mV 1.25 V±225 mV 1.25 V±225 mV 1.25 V±225 mV 1.25 V±225 mV 1.25 V± 225 mV Description Channel A differential clock pair output (true): 245-800 MHz Channel A differential clock pair output (compliment): 245-800 MHz. Channel A differential data pair 3:0 output (true): 245-800MHz. Channel A differential data pair 3:0 output (compliment): 245-800 MHz. Channel B differential clock pair output (true): 245-800 MHz. Channel B differential clock pair output (compliment): 245-800 MHz. Channel B differential data pair 3:0 output (true): 245-800MHz. Channel B differential data pair 3:0 output (compliment): 245-800 MHz.

DVOBBLANK# O DVO

DVOBFLDSTL I DVO

72

8050 N/B Maintenance

5.2 Intel 855GM/GME North Bridge(8)

DVOB and DVOC Port Common Signal Descriptions

Name DVOBCINTR# ADDID[7:0] Type I DVO I DVO Description DVOBC Interrupt: This pin is used to signal an interrupt, typically used to indicate a hot plug or unplug of a digital display. ADDID[7:0]: These pins are used to communicate to the Video BIOS when an external device is interfaced to the DVO port. Note: Bit[7] needs to be strapped low when an on-board DVO device is present. The other pins should be left as NC. DVODETECT: This strapping signal indicates to the GMCH whether a DVO device is present or not. When a DVO device is connected, then DVODETECT = 0.

Digital Video Output C (DVOC) Port Signal Descriptions

Name DVOCD[11:0] Type O DVO Description DVOC Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOCCLK and DVOCCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the upper 12-bits of pixel data. DVOCD[11:0] should be left as left as NC ("Not Connected") if not used. Horizontal Sync: HSYNC signal for the DVOC interface. DVOCHSYNC should be left as left as NC ("Not Connected") if not used. Vertical Sync: VSYNC signal for the DVOC interface. DVOCVSYNC should be left as left as NC ("Not Connected") if the signal is NOT used when using internal graphics device. Flicker Blank or Border Period Indication: DVOCBLANK# is a programmable output pin driven by the GMCH. When programmed as a blank period indication, this pin indicates active pixels excluding the border. When programmed as a border period indication, this pin indicates active pixel including the border pixels. DVOCBLANK# should be left as left as NC ("Not Connected") if not used. TV Field and Flat Panel Stall Signal. This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel. DVOC TV Field Signal: When used as a Field input, it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source. DVOC Flat Panel Stall Signal: When used as the Stall input, it indicates that the pixel pipeline should stall one horizontal line. The signal changes during horizontal blanking. The panel fitting logic, when expanding the image vertically, uses this. DVOCFLDSTL needs to be pulled down if not used.

DVOCHSYNC

DVODETECT

I DVO

O DVO O DVO O DVO

DVOCVSYNC

DVOCBLANK#

Analog CRT Display Signal Descriptions

Pin Name VSYNC HSYNC RED Type O CMOS O CMOS O Analog Description CRT Vertical Synchronization: This signal is used as the vertical sync signal. CRT Horizontal Synchronization: This signal is used as the horizontal sync signal. Red (Analog Video Output): This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5-§Ù equivalent load on each pin (e.g., 75-§Ù resistor on the board, in parallel with the 75-§Ù CRT load). Red# (Analog Output): Tied to ground. Green (Analog Video Output): This signal is a CRT analog video output from the internal color palette DAC. The DAC is designed for a 37.5-§Ù equivalent load on each pin (e.g.,75-§Ù resistor on the board, in parallel with the 75- §Ù CRT load). Green# (Analog Output): Tied to ground. Blue (Analog Video Output) : This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5-§Ù equivalent load on each pin (e.g., 75ohm resistor on the board, in parallel with the 75-§Ù CRT load). Blue# (Analog Output): Tied to ground.

DVOCFLDSTL

I DVO

RED# GREEN

O Analog O Analog

GREEN# BLUE

O Analog O Analog

BLUE#

O Analog

73

8050 N/B Maintenance

5.2 Intel 855GM/GME North Bridge(9)

GPIO Signal Descriptions

GPIO I/F Total RSTIN# PWROK AGPBUSY# Type I CMOS I CMOS O CMOS Comments Reset: Primary Reset, Connected to PCIRST# of ICH4-M. Power OK: Indicates that power to GMCH is stable.

GPIO I/F Total MI2CCLK

Type I/O DVO I/O DVO I/O DVO I/O DVO I/O DVO I/O DVO

Comments DVO I2C Clock: This signal is used as the I2C_CLK for a digital display (i.e. TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard reset. DVO I2C Data: This signal is used as the I2C_DATA for a digital display (i.e. TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard reset. DVI DDC Clock: This signal is used as the DDC clock for a digital display connector (i.e. primary digital monitor). This signal is tri-stated during a hard reset. DVI DDC Data: The signal is used as the DDC data for a digital display connector (i.e. primary digital monitor). This signal is tri-stated during a hard reset. DVI DDC Clock: The signal is used as the DDC data for a digital display connector (i.e. secondary digital monitor). This signal is tri-stated during a hard reset. DVI DDC Data: The signal is used as the DDC clock for a digital display connector (i.e. secondary digital monitor). This signal is tri-stated during a hard reset.

MI2CDATA

AGPBUSY: Output of the GMCH IGD to the ICH4-M, which indicates that certain graphics activity is taking place. It will indicate to the ACPI software not to enter the C3 state. It will also cause a C3/C4 exit if C3/C4 was being entered, or was already entered when AGPBUSY# went active. Not active when the IGD is in any ACPI state other than D0. External Thermal Sensor Input: This signal is an active low input to the GMCH and is used to monitor the thermal condition around the system memory and is used for triggering a read throttle. The GMCH can be optionally programmed to send a SERR, SCI, or SMI message to the ICH4-M upon the triggering of this signal. SSC Chip Clock Control: Can be used to control an external clock chip with SSC control. SSC Chip Data Control: Can be used to control an external clock chip for SSC control. LVDS LCD Flat Panel Power Control: This signal is used enable power to the panel interface. LVDS LCD Flat Panel Backlight Enable: This signal is used to enable the backlight inverter (BLI) LVDS LCD Flat Panel Backlight Brightness Control: This signal is used as the Pulse Width Modulated (PWM) control signal to control the backlight inverter. CRT DDC Clock: This signal is used as the DDC clock signal between the CRT monitor and the GMCH. CRT DDC Data: This signal is used as the DDC data signal between the CRT monitor and the GMCH. Panel DDC Clock: This signal is used as the DDC clock signal between the LFP and the GMCH. Panel DDC Data: This signal is used as the DDC data signal between the LFP and the GMCH.

MDVICLK

MDVIDATA

EXTTS_0

I CMOS

MDDCDATA

MDDCCLK

LCLKCTLA LCLKCTLB PANELVDDEN PANELBKLTE N PANELBKLTC TL

O CMOS O CMOS O CMOS O CMOS O CMOS

DDCACLK DDCADATA DDCPCLK DDCPDATA

I/O CMOS I/O CMOS I/O CMOS I/O CMOS

74

8050 N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(1)

Hub Interface Signals

Signal Name HI[11:0] HI_STB/HI_STBS Type I/O I/O Hub Interface Signals Hub Interface Strobe/ Hub Interface Strobe Second: One of two differential strobe signals used to transmit and receive data through the hub interface. Hub Interface 1.5 mode this signal is not differential and is the second of the two strobe signals. Hub Interface Strobe Complement / Hub Interface Strobe First: One of two differential strobe signals used to transmit and receive data through the hub interface. Hub Interface 1.5 mode this signal is not differential and is the first of the two strobe signals. Hub Interface Compensation: Used for hub interface buffer compensation. Hub Interface Voltage Swing: Analog input used to control the voltage swing and impedance strength of hub interface pins. Description

Firmware Hub Interface Signals

Signal Name FWH[3:0]/ LAD[3:0] FWH[4]/ LFRAME# Type I/O I/O Description Firmware Hub Signals. Muxed with LPC address signals. LFRAME# Firmware Hub Signals. Muxed with LPC LFRAME# signal.

HI_STB#/ HI_STBF

I/O

PCI Interface Signals

Signal Name AD[31:0] Type I/O Description PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The ICH4 drives all 0s on AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the Byte Enables. C/BE[3:0]# Command Type 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0110 Memory Read 0111 Memory Write 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1110 Memory Read Line 1111 Memory Write and Invalidate All command encodings not shown are reserved. The ICH4 does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values. Device Select: The ICH4 asserts DEVSEL# to claim a PCI transaction. As an output, the ICH4 asserts DEVSEL# when a PCI master peripheral attempts an access to an internal ICH4 address or an address destined for the hub interface (main memory or AGP). As an input, DEVSEL# indicates the response to an ICH4-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the ICH4 until driven by a Target device.

HICOMP HI_VSWING

I/O I

C/BE[3:0]#

I/O

LAN Connect Interface Signals

Signal Name LAN_CLK LAN_RXD[2:0] Type I I Description LAN I/F Clock: Driven by the LAN Connect component. Frequency range is 5 MHz to 50 MHz. Received Data: The LAN Connect component uses these signals to transfer data and control information to the integrated LAN Controller. These signals have integrated weak pull-up resistors. Transmit Data: The integrated LAN Controller uses these signals to transfer data and control information to the LAN Connect component. LAN Reset/Sync: The LAN Connect component's Reset and Sync signals are multiplexed onto this pin.

LAN_TXD[2:0]

O

LAN_RSTSYNC

O

EEPROM Interface Signals

Signal Name EE_SHCLK EE_DIN EE_DOUT EE_CS Type O I O O Description EEPROM Shift Clock: Serial shift clock output to the EEPROM. EEPROM Data In: Transfers data from the EEPROM to the ICH3. This signal has an integrated pull-up resistor. EEPROM Data Out: Transfers data from the ICH3 to the EEPROM. EEPROM Chip Select: Chip select signal to the EEPROM.

DEVSEL#

I/O

75

8050 N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(2)

PCI Interface Signals (Continued)

Signal Name FRAME# Type I/O Description Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the Initiator asserts FRAME#, data transfers continue. When the Initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the ICH4 when the ICH4 is the Target, and FRAME# is an output from the ICH4 when the ICH4 is the Initiator. FRAME# remains tri- stated by the ICH4 until driven by an Initiator. Initiator Ready: IRDY# indicates the ICH4's ability, as an Initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock that both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the ICH4 has valid data present on AD[31:0]. During a read, it indicates the ICH4 is prepared to latch data. IRDY# is an input to the ICH4 when the ICH4 is the Target and an output from the ICH4 when the ICH4 is an Initiator. IRDY# remains tri-stated by the ICH4 until driven by an Initiator. Target Ready: TRDY# indicates the ICH4's ability, as a Target, to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the ICH4, as a Target, has placed valid data on AD[31:0]. During a write, TRDY# indicates that the ICH4, as a Target, is prepared to latch data. TRDY# is an input to the ICH4 when the ICH4 is the Initiator and an output from the ICH4 when the ICH4 is a Target. TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated by the ICH4 until driven by a target. Calculated/Checked Parity: PAR uses "even" parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. "Even" parity means that the ICH4 counts the number of 1s within the 36 bits plus PAR and the sum is always even. The ICH4 always calculates PAR on 36 bits regardless of the valid byte enables. The ICH4 generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase. The ICH4 drives and tri-states PAR identically to the AD[31:0] lines except that the ICH4 delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all ICH4 initiated transactions. PAR is an output during the data phase (delayed one clock) when the ICH4 is the Initiator of a PCI write transaction, and when it is the Target of a read transaction. ICH4 checks parity when it is the Target of a PCI write transaction. If a parity error is detected, the ICH4 will set the appropriate internal status bits, and has the option to generate an NMI# or SMI#.

PCI Interface Signals (Continued)

Signal Name STOP# Type I/O Description Stop: STOP# indicates that the ICH4, as a Target, is requesting the Initiator to stop the current transaction. STOP# causes the ICH4, as an Initiator, to stop the current transaction. STOP# is an output when the ICH4 is a Target and an input when the ICH4 is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated until driven by the ICH4. Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The ICH4 drives PERR# when it detects a parity error. The ICH4 can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal). PCI Requests: The ICH4 supports up to 6 masters on the PCI bus. REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the other, but not both). If not used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be used as GPIO[1]. NOTE: REQ[0]# is programmable to have improved arbitration latency for for supporting PCI-based 1394 controllers. PCI Grants: The ICH4 supports up to 6 masters on the PCI bus. GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the other, but not both). If not needed for PCI or PC/PCI, GNT[5]# can instead be used as a GPIO. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-up. PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on the PCI Bus. NOTE: This clock does not stop based on STP_PCI# signal. PCICLK only stops based on SLP_S1# or SLP_S3#. PCI Reset: ICH4 asserts PCIRST# to reset devices that reside on the PCI bus. The ICH4 asserts PCIRST# during power-up and when S/W initiates a hard reset sequence through the RC (CF9h) register. The ICH4 drives PCIRST# inactive a minimum of 1 ms after PWROK is driven active. The ICH4 drives PCIRST# active a minimum of 1 ms when initiated through the RC register. PCI Lock: This signal indicates an exclusive bus operation and may require multiple transactions to complete. ICH4 asserts PLOCK# when it performs non- exclusive transactions on the PCI bus. Devices on the PCI bus (other than the ICH4) are not permitted to assert the PLOCK# signal. System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the ICH4 has the ability to generate an NMI, SMI#, or interrupt.

PERR#

I/O

IRDY#

I/O

REQ[4:0]# REQ[5]#/ REQ[B]#/ GPIO[1]

I

TRDY#

I/O

GNT[4:0]# GNT[5]#/ GNT[B]#/ GPIO[17]

O

PCICLK

I

PAR

I/O

PCIRST#

O

PLOCK#

I/O

SERR#

I/OD

76

8050 N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(3)

PCI Interface Signals (Continued)

Signal Name PME# Type I/OD Description PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1-M­S5. PME# assertion can also be enabled to generate an SCI from the S0 state. In some cases the ICH4 may drive PME# active due to an internal wake event. The ICH4 will not drive PME# high, but it will be pulled up to VccSus3_3 by an internal pull-up resistor. PCI Clock Run: Used to support PCI Clock Run protocol. Connects to PCI devices that need to request clock re-start, or prevention of clock stopping. NOTE: An external pull-up to the core power plane is required. PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA Requests for the purpose of running ISA-compatible DMA cycles over the PCI bus. This is used by devices such as PCI based Super I/O or audio codecs which need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI requests, these signals can be used as General Purpose Inputs. REQ[B]# can instead be used as the 6th PCI bus request. PC/PCI DMA Acknowledges [A: B]: This grant serializes an ISA-like DACK# for the purpose of running DMA/ISA Master cycles over the PCI bus. This is used by devices such as PCI based Super/IO or audio codecs which need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI, these signals can be used as General Purpose Outputs. GNTB# can also be used as the 6th PCI bus master grant output. These signal have internal pull-up resistors.

IDE Interface Signals (Continued)

Signal Name PDD[15:0], SDD[15:0] Type I/O Description Primary and Secondary IDE Device Data: These signals directly drive the corresponding signals on the primary or secondary IDE connector. There is a weak internal pull-down resistor on PDD[7] and SDD[7]. Primary and Secondary IDE Device DMA Request: These input signals are directly driven from the DRQ signals on the primary or secondary IDE connector. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel. There is a weak internal pull-down resistor on these signals. Primary and Secondary IDE Device DMA Acknowledge: These signals directly drive the DAK# signals on the primary and secondary IDE connectors. Each is asserted by the ICH4 to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel. Primary and Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device that it may drive data onto the PDD or SDD lines. Data is latched by the ICH4 on the deassertion edge of PDIOR# or SDIOR#. The IDE device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge (PDDAK# or SDDAK#). Primary and Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe for writes to disk. When writing to disk, ICH4 drives valid data on rising and falling edges of PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for reads from disk. When reading from disk, ICH4 deasserts PRDMARDY# or SRDMARDY# to pause burst data transfers. Primary and Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device that it may latch data from the PDD or SDD lines. Data is latched by the IDE device on the deassertion edge of PDIOW# or SDIOW#. The IDE device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge (PDDAK# or SDDAK#). Primary and Secondary Disk Stop (Ultra DMA): ICH4 asserts this signal to terminate a burst.

PDDREQ, SDDREQ

I

CLKRUN#

I/O

REQ[A]#/ GPIO[0] REQ[B]#/ REQ[5]#/ GPIO[1]

I

PDDACK#, SDDACK#

O

GNT[A]#/ GPIO[16] GNT[B]#/ GNT[5]#/ GPIO[17]

O

PDIOR#/ (PDWSTB/PRDMA RDY#) SDIOR#/ (SDWSTB/SRDMA RDY#)

O

IDE Interface Signals

Signal Name PDCS1#, SDCS1# Type O Description Primary and Secondary IDE Device Chip Selects for 100 Range: For ATA command register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. Primary and Secondary IDE Device Chip Select for 300 Range: For ATA control register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. Primary and Secondary IDE Device Address: These output signals are connected to the corresponding signals on the primary or secondary IDE connectors. They are used to indicate which byte in either the ATA command block or control block is being addressed.

PDIOW#/ (PDSTOP) SDIOW#/ (SDSTOP) O

PDCS3#, SDCS3#

O

PDA[2:0], SDA[2:0]

O

77

8050 N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(4)

IDE Interface Signals (Continued)

Signal Name PIORDY#/ (PDRSTB/PWDMA RDY#) SIORDY#/ (SDRSTB/SWDMA RDY#) Type I Description Primary and Secondary I/O Channel Ready (PIO): This signal will keep the strobe active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes) longer than the minimum width. It adds wait states to PIO transfers. Primary and Secondary Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk, the ICH4 latches data on rising and falling edges of this signal from the disk. Primary and Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is de-asserted by the disk to pause burst data transfers.

LPC Interface Signals

Signal Name LAD[3:0]/ FWH[3:0] LFRAME#/ FWH[4] LDRQ[1:0]# Type I/O O I Description LPC Multiplexed Command, Address, Data: For the LAD[3:0] signals, internal pull-ups are provided. LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to an external Super I/O device. An internal pull-up resistor is provided on these signals.

USB Interface Signals

Interrupt Signals

Signal Name SERIRQ PIRQ[D:A]# Type I/O I/OD Description Serial Interrupt Request: This pin implements the serial interrupt protocol. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the legacy interrupts. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. This frees the legacy interrupts. If not needed for interrupts, these signals can be used as GPIO. Interrupt Request 14:15: These interrupt inputs are connected to the IDE drives. IRQ14 is used by the drives connected to the Primary controller and IRQ15 is used by the drives connected to the Secondary controller. APIC Clock: This clock operates up to 33.33 MHz. APIC Data: These bi-directional open drain signals are used to send and receive data over the APIC bus. As inputs the data is valid on the rising edge of APICCLK. As outputs, new data is driven from the rising edge of the APICCLK.

Signal Name USBP0P, USBP0N, USBP1P, USBP1N

Type I/O

Description Universal Serial Bus Port 1:0 Differential: These differential pairs are used to transmit data/address/command signals for ports 0 and 1. These ports can be routed to USB UHCI Controller #1 or the USB EHCI Controller. NOTE: No external resistors are required on these signals. The ICH4 integrates 15 k . pull-downs and provides an output driver impedance of 45 . which requires no external series resistor Universal Serial Bus Port 3:2 Differential: These differential pairs are used to transmit data/address/command signals for ports 2 and 3. These ports can be routed to USB UHCI Controller #2 or the USB EHCI Controller. NOTE: No external resistors are required on these signals. The ICH4 integrates 15 k . pull-downs and provides an output driver impedance of 45 . which requires no external series resistor. Universal Serial Bus Port 5:4 Differential: These differential pairs are used to transmit data/address/command signals for ports 4 and 5. These ports can be routed to USB UHCI Controller #3 or the USB EHCI Controller NOTE: No external resistors are required on these signals. The ICH4 integrates 15 k . pull-downs and provides an output driver impedance of 45 . which requires no external series resistor Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred. USB Resistor Bias: Analog connection point for an external resistor to ground. USBRBIAS should be connected to USBRBIAS# as close to the resistor as possible. USB Resistor Bias Complement: Analog connection point for an external resistor to ground. USBRBIAS# should be connected to USBRBIAS as close to the resistor as possible.

USBP2P, USBP2N, USBP3P, USBP3N

I/O

PIRQ[H:E]#/ GPIO[5:2]

I/OD

USBP4P, USBP4N, USBP5P, USBP4N

I/O

IRQ[14:15]

I

OC[5:0]#

I/O

USBRBIAS

O

APICCLK APICD[1:0]

I I/OD

USBRBIAS#

I

78

8050 N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(5)

Power Management Interface Signals

Signal Name THRM# Type I Description Thermal Alarm: This is an active low signal generated by external hardware to start the hardware clock throttling mode. The signal can also generate an SMI# or an SCI. Thermal Trip: When low, THRMTRIP# indicates that a thermal trip from the processor occurred; the ICH4 will immediately transition to a S5 state. The ICH4 will not wait for the processor stop grant cycle since the processor has overheated. S1 Sleep Control: SLP_S1# provides Clock Synthesizer or Power plane control. Optional use is to shut off power to non-critical systems when in the S1- M (Powered On Suspend), S3 (Suspend To RAM), S4 (Suspend to Disk) or S5 (Soft Off) states. S3 Sleep Control: SLP_S3# is for power plane control. It shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states. S4 Sleep Control: SLP_S4# is for power plane control. It shuts power to all non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state. S5 Sleep Control: SLP_S5# is for power plane control. The signal is used to shut power off to all non-critical systems when in the S5 (Soft Off) states. Power OK: When asserted, PWROK is an indication to the ICH4 that core power and PCICLK have been stable for at least 1 ms. PWROK can be driven asynchronously. When PWROK is negated, the ICH4 asserts PCIRST#. NOTE: PWROK must deassert for a minimum of 3 RTC clock periods for the ICH4 to fully reset the power and properly generate the PCIRST# output Power Button: The Power Button causes SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal causes a wake event. If PWRBTN# is pressed for more than 4 seconds, this causes an unconditional transition (power button override) to the S5 state with only the PWRBTN# available as a wake event. Override occurs even if the system is in the S1-M­S4 states. This signal has an internal pull-up resistor. Ring Indicate: This signal is an input from the modem interface. It can be enabled as a wake event, and this is preserved across power failures. System Reset: This pin forces an internal reset after being debounced. The ICH4 will reset immediately if the SMBus is idle; otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before forcing a reset on the system. Resume Well Reset: This signal is used for resetting the resume power plane logic.

Power Management Interface Signals (Continued)

Signal Name LAN_RST# Type I Description LAN Reset: This signal must be asserted at least 10 ms after the resume well power (VccLAN3_3 and VccLAN1_5 is valid. When deasserted, this signal is an indication that the resume well power is stable. Suspend Status: This signal is asserted by the ICH4 to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC I/F. C3_STAT#: This signal will typically be configured as C3_STAT#. It is used for indicating to an AGP device that a C3 state transition is beginning or ending. If C3_STAT# functionality is not required, this signal may be used as a GPO. NOTE: This signal will be asserted in S1-M on the ICH4-M. Suspend Clock: Output of the RTC generator circuit to use by other chips for refresh clock. AGP Bus Busy: To support the C3 state. This signal is an indication that the AGP device is busy. When this signal is asserted, the BM_STS bit will be set. If this functionality is not needed, this signal may be configured as a GPI. Stop PCI Clock: This signal is an output to the external clock generator for it to turn off the PCI clock. Used to support PCI CLKRUN# protocol. If this functionality is not needed, This signal can be configured as a GPO. Stop CPU Clock: Output to the external clock generator for it to turn off the processor clock. Used to support the C3 state. If this functionality is not needed, this signal can be configured as a GPO. Battery Low: This signal is an input from the battery to indicate that there is insufficient power to boot the system. Assertion will prevent wake from S1-M­S5 state. Can also be enabled to cause an SMI# when asserted. CPU Performance: CPUPERF# is used for Intel SpeedStep technology support. The signal selects which power state to put the processor in. SpeedStep Mux Select: SSMUXSEL is used for Intel SpeedStep technology support. The signal selects the voltage level for the processor. VGATE/VRM Power Good: VGATE/VRMPWRGD is used for Intel SpeedStep technology support. This is an output from the processor's voltage regulator to indicate that the voltage is stable. This signal may go inactive during an Intel SpeedStep transition.

THRMTRIP#

I

SUS_STAT#/ LPCPD#

O

SLP_S1#

O

SLP_S3#

O

C3_STAT#

O

SLP_S4#

O

SUSCLK AGPBUSY#

O I

SLP_S5#

O

PWROK

I

STP_PCI#

O

STP_CPU#

O

PWRBTN#

I

BATLOW#

I

CPUPERF#

OD

RI#

I

SSMUXSEL

O

SYS_RESET#

I

VGATE/ VRMPWRGD

I

RSMRST#

I

79

8050 N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(6)

Power Management Interface Signals (Continued)

Signal Name DPRSLPVR Type O Description Deeper Sleep - Voltage Regulator: This signal is used to lower the voltage of VRM during C4 and S1-M states. When the signal is high, the voltage regulator outputs the lower "Deeper Sleep" voltage. When the signal is low (default), the voltage regulator outputs the higher "Normal" voltage. During PCIRST#, the output driver is disabled and an internal pull-down is enabled. This is needed for implementing a strap on the pin. When PCIRST# deasserts, the output driver is enabled. To guarantee no glitches on the DPRSLPVR pin, the pull-down is disabled after the output driver is fully enabled. NOTE: DPRSLPVR is sampled at the rising edge of PWROK as a functional strap.

Processor Interface Signals (Continued)

Signal Name IGNNE# Type O Description Ignore Numeric Error: This signal is connected to the ignore error pin on the processor. IGNNE# is only used if the ICH4 coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register is written, the IGNNE# signal is not asserted. Speed Strap: During the reset sequence, ICH4 drives IGNNE# high if the corresponding bit is set in the FREQ_STRP register. Initialization: INIT# is asserted by the ICH4 for 16 PCI clocks to reset the processor. ICH4 can be configured to support CPU BIST. In that case, INIT# will be active when PCIRST# is active. Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt to the processor. The ICH4 can generate an NMI when either SERR# or IOCHK# is asserted. The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI Status and Control Register. Speed Strap: During the reset sequence, ICH4 drives NMI high if the corresponding bit is set in the FREQ_STRP register. System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the ICH4 in response to one of many enabled hardware or software events. Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the ICH4 in response to one of many hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock. Keyboard Controller Reset CPU: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the ICH4's other sources of INIT#. When the ICH4 detects the assertion of this signal, INIT# is generated for 16 PCI clocks. NOTE: The ICH4 ignores RCIN# assertion during transitions to the S1-M, S3, S4 and S5 states. A20 Gate: A20GATE is from the keyboard controller. The signal acts as an alternative method to force the A20M# signal active. It saves the external OR gate needed with various other PCIsets.

INIT#

O

NMI

O

Processor Interface Signals

Signal Name A20M# Type O Description Mask A20: A20M# will go active based on either setting the appropriate bit in the Port 92h register, or based on the A20GATE input being active. Speed Strap: During the reset sequence, ICH4 drives A20M# high if the corresponding bit is set in the FREQ_STRP register. CPU Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that time, no snoops occur. The ICH4 can optionally assert the CPUSLP# signal when going to the S1-M state. Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor. FERR# is only used if the ICH4 coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is asserted, the ICH4 generates an internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. NOTE: FERR# can be used in some states for notification by the processor of pending interrupt events. This functionality is independent of the General Control Register bit setting. CPU Interrupt: INTR is asserted by the ICH4 to signal the processor that an interrupt request is pending and needs to be serviced. It is an asynchronous output and normally driven low. Speed Strap: During the reset sequence, ICH4 drives INTR high if the corresponding bit is set in the FREQ_STRP register.

CPUSLP#

O

SMI#

O

STPCLK#

O

FERR#

I

RCIN#

I

A20GATE

I

INTR

O

80

8050 N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(7)

Processor Interface Signals (Continued)

Signal Name CPUPWRGD Type OD Description CPU Power Good: This signal should be connected to the processor's PWRGOOD input. To allow for Intel ® SpeedStepTM technology support, this signal is kept high during an Intel SpeedStep technology state transition to prevent loss of processor context. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the ICH4's PWROK and VGATE / VRMPWRGD signals. Deeper Sleep: This signal is asserted by the ICH4 to the processor. When the signal is low, the processor enters the Deeper Sleep state by gating off the processor Core clock inside the processor. When the signal is high (default), the processor is not in the Deeper Sleep state. This signal behaves identically to the STP_CPU# signal, but at the processor voltage level.

Real Time Clock Interface Signals

Signal Name RTCX1 RTCX2 Type Special Special Description Crystal Input 1: This signal is connected to the 32.768 kHz crystal. Crystal Input 2: This signal is connected to the 32.768 kHz crystal.

Other Clock Signals

Signal Name CLK14 CLK48 Type I I Description Oscillator Clock: Used for 8254 timers. It runs at 14.31818 MHz. This clock is permitted to stop during S1-M (or lower) states. 48 MHz Clock: This clock is used to run the USB controller. It runs at 48 MHz. This clock is permitted to stop during S1-M (or lower) states. 66 MHz Clock: This is used to run the hub interface. It runs at 66 MHz. This clock is permitted to stop during S1-M (or lower) states.

DPSLP#

O

CLK66

I

SMBus Interface Signals

Signal Name SMBDATA SMBCLK SMBALERT#/ GPIO[11] Type I/OD I/OD I Description SMBus Data: External pull-up is required. SMBus Clock: External pull-up is required. SMBus Alert: This signal is used to wake the system or generate SMI#. If not used for SMBALERT#, it can be used as a GPI.

Miscellaneous Signals

Signal Name SPKR Type O Description Speaker: The SPKR signal is the output of counter 2 and is internally "ANDed" with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PCIRST#, its output state is 0. NOTE: SPKR is sampled at the rising edge of PWROK as a functional strap. RTC Reset: When asserted, this signal resets register bits in the RTC well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). NOTES: 1. Clearing CMOS in an ICH4-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. 2. Unless entering the XOR Chain Test Mode, the RTCRST# input must always be high when all other RTC power planes are on.

System Management Interface Signals

Signal Name INTRUDER# Type I Description Intruder Detect: Can be set to disable system if box detected open. This signal's status is readable, so it can be used like a GPI if the Intruder Detection is not needed. System Management Link: SMBus link to optional external system management ASIC or LAN controller. External pull-ups are required. Note that SMLINK[0] corresponds to an SMBus Clock signal, and SMLINK[1] corresponds to an SMBus Data signal.

RTCRST#

I

SMLINK[1:0]

I/OD

81

8050 N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(8)

AC'97 Link Signals

Signal Name AC_RST# Type O Description AC '97 Reset: This signal is a master hardware reset to external Codec(s). O AC '97 Sync: This signal is a 48 kHz fixed rate sample sync to the AC_SYNC Codec(s). I AC97 Bit Clock: This signal is a 12.288 MHz serial data clock AC_BIT_CLK generated by the external Codec(s). This signal has an integrated pull-down resistor. AC97 Serial Data Out: Serial TDM data output to the Codec(s). O AC_SDOUT NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a functional strap. I AC97 Serial Data In 2:0: These signals are Serial TDM data inputs AC_SDIN[1:0] from the three Codecs. NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: The ACLINK Shutoff bit in the AC'97 Global Control Register is set to 1, or Both Function 5 and Function 6 of Device 31 are disabled. Otherwise, the integrated pull-down resistor is disabled.

Power and Ground Signals

Signal Name VCC3_3 VCC1_5 VCCHI Description 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 or G3 states. 1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3 states. 1.5 V supply for Hub Interface 1.5 logic. 1.8 V supply for Hub Interface 1.0 logic. This power may be shut off in S3, S4, S5 or G3 states. Reference for 5 V tolerance on core well inputs. This power may be shut off in S3, S4, S5 or G3 states. Analog Input. Expected voltages are: · 0.9 V for HI 1.0 (Normal Hub Interface) Series Termination · 350 mV for HI 1.5 (Enhanced Hub Interface) Parallel Termination This power is shut off in S3, S4, S5, and G3 states. 3.3 V supply for resume well I/O buffers. This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available. 1.5 V supply for resume well logic. This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available. Reference for 5 V tolerance on resume well inputs. This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available. 3.3 V supply for LAN Connect interface buffers. This is a separate power plane that may or may not be powered in S3­S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1-M. 1.5 V supply for LAN Controller logic. This is a separate power plane that may or may not be powered in S3­S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1-M. 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not expected to be shut off unless the RTC battery is removed or completely drained. NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an ICH4-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. 1.5 V supply for core well logic. This signal is used for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. RTC well bias voltage. The DC reference voltage applied to this pin sets a current that is mirrored throughout the oscillator and buffer circuitry. Powered by the same supply as the processor I/O voltage. This supply is used to drive the processor interface outputs. Grounds.

V5REF HIREF

VCCSUS3_3

VCCSUS1_5

General Purpose I/O Signals

Signal Name GPIO[43:32] GPIO[31:29] GPIO[28:27] GPIO[26] GPIO[25] GPIO[24:18] GPIO[17:16] Type I/O O I/O I/O I/O I/O O Description Can be input or output. Main power well. Not implemented. Can be input or output. Resume power well. Unmuxed. Not implemented. Can be input or output. Resume power well. Unmuxed. Not Implemented in Mobile (Assign to native Functionality). V5REF_SUS

VCCLAN3_3

Fixed as Output only. Main power well. Can be used instead as PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for PCI GNT[5]#. Integrated pull-up resistor. I Not implemented. GPIO[15:14] I Fixed as Input only. Resume power well. Unmuxed. GPIO[13:12] I Fixed as Input only. Resume power well. Can be used instead as GPIO[11] SMBALERT#. I Not implemented. GPIO[10:9] I Fixed as Input only. Resume power well. Unmuxed. GPIO[8] I Fixed as Input only. Main power well. Unmuxed. GPIO[7] I Not Implemented in Mobile (Assign to Native Functionality) GPIO[6] I Fixed as Input only. Main power well. Can be used instead as GPIO[5:2] PIRQ[E:H]#. I Fixed as Input only. Main power well. Can be used instead as GPIO[1:0] PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI REQ[5]#. NOTE: Main power well GPIO are 5V tolerant, except for GPIO[43:32]. Resume power well GPIO are not 5V tolerant.

VCCLAN1_5

VCCRTC

VCCPLL VBIAS V_CPU_IO VSS

82

8050 N/B Maintenance

6. System Block Diagram

U713 INTEL BANIAS/DOTHAN Host 400MHZ U727 PCMCIA CARD READER CB710 U714 J711 DDR 266 North Bridge 855GME

TV

J6 Card Reader Socket

RGB LVDS

CRT

LCD

Mini PCI Card Socket

U719 RTL8100CL

66MHZ

Amplifier TPA0212 MIC

IEEE 1394

PCI BUS U715 ICH4-M AC 97 U726 AUDIO CODEC ALC655 U524

Speaker HP/OPT Jack Subwoofer Line In

HDD

MDC CD-ROM LPC BUS

RJ11

USB2.0

U15

FWH BIOS

U16

WINBOND W83L950D

Internal KB Touch Pad FAN 83

8050 N/B Maintenance

7. Maintenance Diagnostics

7.1 Introduction

Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can alert you to the problems of your computer.If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs before the display is initialized, then the screen cannot display the error message. Error codes or system beeps are used to identify a post error that occurs when the screen is not available. The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can determine where the problem occurred by reading the last value written to the port by the debug card plug at MINI PCI slot.

84

8050 N/B Maintenance

7.2 Diagnostic Tool for Mini PCI Slot :

The Mini PCI DOG killer card is a single-step debug tool which utilizes Mini PCI interface (Type III A) and is able to hold a PCI bus cycle so that address, data and control bus states on PCI bus can be inspected. Especially, the tool can help an engineer trace address/data bus for BIOS read cycles as soon as power on and debug open or short circuit problems easily. Usually, this sort of problem will make a PC motherboard fail to boot.

P/N:411906900001 Description: PWA-MPDOG;MINI PCI DOGKELLER CARD Note: Order it from MIC/TSSC

85

8050 N/B Maintenance

7.3 Error Codes - 1

Following is a list of error codes in sequent display on the debug board.

POST (HEX)

DESCRIPTION

POST (HEX)

DESCRIPTION

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Fh F0h F1h 99h 10H 11H 12H 13H 14H 15H 16H

Boot started Disable A20 through A20 Initialize CS Test RAM Move BL into the RAM Execution in RAM Check OVERRIDE option Shadow System BIOS Checksum System BIOS ROM Proceed with Normal Boot Proceed with Crisis Boot Fatal Error .... - No RAM ..._ - RAM test failed Resume SMRAM not Found Some Type Of Long Reset Turn off FASTA20 for POST Signal Power On Reset Initialize the Chipset Search For ISA Bus VGA Adapter Reset Counter/Timer 1 user register config through CMOS

17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH

Size Memory Dispatch To RAM Test checksum the ROM Reset PIC's Initialize Video Adapter(s) Initialize Video (6845 Regs) Initialize Color Adapter Initialize Monochrome Adapter Test 8237A Page Registers Test Keyboard Test Keyboard Controller Check If CMOS Ram Valid Test Battery Fail & CMOS X-SUM Test the DMA controllers Initialize 8237A Controller Initialize Int Vectors RAM Quick Sizing Protected mode entered safely RAM test completed Protected mode exit successful Setup Shadow Going To Initialize Video

86

8050 N/B Maintenance

7.3 Error Codes - 2

Following is a list of error codes in sequent display on the debug board.

POST (HEX)

DESCRIPTION

POST (HEX)

DESCRIPTION

2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H

Search For Monochrome Adapter Search For Color Adapter Signon messages displayed special init of keyboard ctlr Test If Keyboard Present Test Keyboard Interrupt Test Keyboard Command Byte TEST, Blank and count all RAM Protected mode entered safely (2). RAM test complete Protected mode exit successful Update OUTPUT port Setup Cache Controller Test If 18.2Hz Periodic Working test for RTC ticking initialize the hardware vectors Search and Init the Mouse Update NUMLOCK status special init of COMM and LPT ports Configure the COMM and LPT ports Initialize the floppies

42H 43H 44H 45H 46H 47H 48H 49H 50H 51H 52H F8H F9H FAH FBH FCH FDH FEH 88H CAH CBH

Initialize the hard disk Initialize option ROMs OEM's init of power management Update NUMLOCK status Test For Coprocessor Installed OEM functions before boot Dispatch To Op. Sys. Boot Jump Into Bootstrap Code ACPI INIT PM INIT & GEYSERVILLE CPU INIT USB HC INIT PXE BIOS decomp error PCI BIOS decomp error PNP BIOS decomp error LOGO BIOS decomp error LOGO Image decomp error Energy Image decomp error ROMDEBUG Image decomp error PM code decomp error CPU SMM remap code CPU SMM BASE remap Done

87

8050 N/B Maintenance

7.3 Error Codes - 3

Following is a list of error codes in sequent display on the debug board.

POST (HEX)

DESCRIPTION

POST (HEX)

DESCRIPTION

D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H

check rom signature, 1.x video enable RAM area in regs copy ROM to RAM in regs update segment range attr configure memory registers configure I/O registers configure IRQ assignments turn on PCI device 2.x video r/w segment OEM defined, rom init disable add-in rom card decode PCI return(config and no video) enable RAM area in regs copy ROM to RAM in regs update segment range attr configure memory registers configure I/O registers configure IRQ assignments turn on PCI device 2.x video r/w segment OEM defined, rom init

E5H E6H E7H E8H E9H A1H A2H A3H A4H A5H A6H A7H A8H A9H

disable add-in rom card decode PCI return(config and no video) look for PCI bridge device search IDE controllers on the PCI bus start of cardbus config Enable/Verify R/W Status Runtime Data Get/Verrify R/W Stattus NVRAM data area Resolve System Nodes with the CMOS settings Init. var. in the PNP BIOS Runtime Data area Hook INT 15 copy/setup $PnP Install Check in F0000 seg. Allow the OEM any Last Minute Hooks Write protect RTData Area & NVRAM Copy Buffer return from pnp_init proc

88

8050 N/B Maintenance

8. Trouble Shooting

8.1 No Power 8.2 Battery Can not Be Charged 8.3 No Display 8.4 External Monitor No Display 8.5 Memory Test Error 8.6 Keyboard/Touch pad Test Error 8.7 USB Port Test Error 8.8 Hard Disk Drive Test Error 8.9 CD-ROM Driver Test Error 8.10 Audio Failure 8.11 LAN Test Error 8.12 Modem Test Error 8.13 MINI-PCI Test Error 8.14 Card Bus&Reader Test Error 8.15 TV Encoder Test Failure 8.16 IEEE 1394 Failure

89

8050 N/B Maintenance

8.1 No Power

When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

P32

Power In PJ 701

PF1 PL1 PL2 PR701

PD702

P32

U11

P25

Q13

P25

PWR_VDDIN

F3,U13

VDD5

P25

Q48

VDD5S

P25

Q51,L71

P25

U6

P25

P32

PQ701

PD704

VDD3_AVREF

VDD3

Q43

VDD3S

VDD1.5

ADINP

PF703 PU7 PL708 PQ707

PD703

P32

P27

JS704 PU2 PL701 PL703 PU702 PR711 JS711,JS713,JS715

P24

U707,Q701

P25

L746 L706,L707 L743

P18

DVMAIN

+3VS-P

+3VS

+3V

P25

1394_AVCC

+PHYVDD

P27

PL702 PR707 PU701 U705,L708

PL710 PD709 PD713 PQ704

P24

JS718,JS719,JS721

U701

L702 L701

P15

P33

PD704

+5VS_P

+5VS

+VCC_USB_0 +VCC_USB_1 +VCC_USB_2

P25

U728

Charge

P32

Battery

Discharge

U704,L70 3 L704,Q10

P17

+5V

U18

+CARD_VCC

P20

NOTE:.

P27 Page on M/B board circuit diagram.

PU3,PU9,PU10,PU11 PU12,PU13,PL711, PD718,PR740

VA

P31

+VCC_CORE

To Next Page 90

8050 N/B Maintenance

8.1 No Power

When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. Continue To Previous Page

P27

DVMAIN

JS706,PL712 PU14 PU707,PL714,PR741 PU705,PL713,PR739

P29

JS71,JS717

P24

+1.8V_P

P29

JS72,JS722

+1.8V

P5

+1.35V_P

+1.35V

JS10,PL3 PU703

PU6,PL707,PR732

P28

JS728,JS729,JS730

P24

+1.05V_P

PU4,PL706,PR719

+VCCP

JS72,JS725

P28

P24

+1.5V_P

P26

+1.5V

P24

JS703,PL716 PU15

PU709,PL717,PR744

+1.25V_DDR_P

P26

JS1,JS12

+1.25V_DDR

P24

L732

PU708,PL715,PR742

JS708,JS709,JS710

P16

+2.5VS_DDR_P

+2.5VS_DDR

DVDD

91

8050 N/B Maintenance

8.1 No Power

When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

No power AC POWER Is the Notebook connected to power (Either AC adaptor or battery)? Yes Please try another known good battery or AC adapter. Where From Power Source Problem(First use AC to power it) Please replace the faulty AC adaptor or Battery. BATTERY

Check following parts and signals: Parts: Signals:

PF1 ALWAYS DVMAIN ADEN# BATT_DEAD PL1 PL2 PD702 PQ701

No

Connect AC adaptor or battery

Power OK? NO

Yes

Check following parts and signals: Parts: Signals:

J703 PF702 PQ6 PQ704 BATT

Board-level Troubleshooting

PL704 PL705

92

8050 N/B Maintenance

8.1 No Power(1)

When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

PL1

120Z/100M PD702 BAV70LT1

PJ701 PF1 7A/24VDC PL2 120Z/100M PR701 .01

PWR_VDDIN

PD701 RLZ24D To chapter 8.2 ADINP PQ701 AO4407

3 2 1 8 7 6 5

G D

PD704 BAV70LT1

1 2

PD703 SBM1040 3

DVMAIN

4 5 76 H8_I_LIMIT R428 0 I_LIMIT PR1 10 6

RS+ RSOUT

P32

VCC GND1 GND0

3 2 1

PR702 470K

23

LEARNING

PQ702 2N7002

PR71 226K

G D 8 7 6 5

U16

PR705 1M

PR45 33K BATT

WINBOND KBC

14

D21 RLS4148

ADEN#

PQ6 2N7002

PQ24 DTC144WK

S

P22

S

PU1

PR720 PR703 100K

100K

3 2 1 PQ704 AO4407

93

8050 N/B Maintenance

8.1 No Power(2)

When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

PD704 BAV70LT1 PWR_VDDIN PQ704 AO4407 3 2 1

4 VDD3S PF702 7A/24VDC PL705 120Z/100M 8 7 6 5

PR720 100K DVMAIN

BATT

PL704 120Z/100M PR716 499K PC722 0.01U PR714 100K BAT_V 8 RP45 22*4 1 78 PR45 33K

PR20 4.99K P32

J703

7 6 5 4 3 2 1 PR23

BATTCONNECTOR

BAT_T

7

2

77

P22 D21 RLS4148

U16 WINBOND KBC

0 BAT_C 6 3 2

14

ADEN#

PQ6 2N7002

PR24

0

BAT_D

5

4

3

PD2 BAV99 VDD3

PD3 BAV99

94

8050 N/B Maintenance

8.2 Battery Can not Be Charged

There are problems in charging the battery.

Battery can not Charge Board-level Troubleshooting

Is the notebook connected to power (AC adaptor)?

No

Connect AC adaptor. Check following parts and signals:

Yes

Replace Motherboard

Parts

PF703 PL708 PQ707 PL710 PD713 PD714 PD709 PQ13 PQ14 PU7 PQ15 PD5 PR65 PR70 PQ11 PC33 PR63 PU5 PR74 PR75 PR76 PQ12

Signal

ADINP CHANGING BATT BAT_V BAT_T BAT_C BAT_D

BATT_DEAD I_CTRL

1. Make sure that the battery is good.

2. Make sure that the battery is installed properly.

Battery charge OK? No

Yes

Please replace the faulty Battery.

95

8050 N/B Maintenance

8.2 Battery Can not Be Charged

There are problems in charging the battery.

PQ707 AO4407 From chapter 8.1(1) ADINP PF703 TR/3216FF-3A PL708 BEAD_120Z/100M

3 2 1 8 7 6 5 G D

PL710 33UH

PL709 3.0UH

PD713 EC31QS04

Reference chapter 8.1(1) BATT

PR87 4.7K PR86 0

PR88 4.7K PQ15 MMBT2222A PR89 100K

PQ13 DTA144WK PD5 BAS32L

26

CHARGING

PQ14 2N7002 PC48 0.01U CHARGING

11 P22 10 R483 0 I_CTRL PR78 0 PR79 124K

C2 P33

C1 21IN+

8 16 21N+

12 VCC 13 2

U16

15

PU7 TL594C

BATT_DEAD# DVMAIN VDD5

WINBOND KBC

Reference chapter 8.1(2) 78 77 2 3 BAT_V BAT_T BAT_C BAT_D PC36 0.01U Q39 DTC144TKA =8.56V BATT_DEAD 7 PU5 LMV393M PR69 100K 8 + 4 PR63 80.6K PC33 0.1U 5 6 PQ11 SCK431LCSK-.5 1.25V PR65 590K PR70 3.3K

S

PD714 EC31QS04

PD709 BZV55C15V PR74 13.7K

PC39 1000P

PR75 20K

PR76 249K

From U16

PQ12 2N7002

96

8050 N/B Maintenance

8.3 No Display

There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.

No Display

Monitor or LCD module OK? Yes

No

Replace monitor or LCD.

Board-level Troubleshooting

Make sure that CPU module, DIMM memory are installed Properly. Yes Correct it.

Replace Motherboard Using debug card,depending on the error codes to make sure which parts maybe faulty

Display OK? No

1.Try another known good CPU module, DIMM module and BIOS. 2.Remove all of I/O device (FDD, HDD, CD-ROM.......) from motherboard except LCD or monitor. 1. Replace faulty part. 2. Connect the I/O device to the M/B one at a time to find out which part is causing the problem.

Using circuit diagram ,check the faulty parts

Display OK? No

Yes

97

8050 N/B Maintenance

8.3 No Display(1)

****** System Clock Check ******

R874 R875

+3V

R860

4.7K

FS0 FS1 FS2 R863 R894 4.7K 4.7K

54 55 40

44,45

33*2

HCLK_CPU

HCLK_CPU#

P2

P3

U713

35,38 48,49 R865 R872 R873 R878 33*4 48M_DREFCLK 66M_DEFSSCLK HCLK_MCH HCLK_MCH#

CPU

P4

P5

+3V R863 L722 L726 L43 L718 8.2K 120Z/100M 120Z/100M 120Z/100M 120Z/100M CLKANA CLK66 CLKCPU CLKPCI 43 1,26,37 19,32 46,50 8,14 R877 33 33 33 USBCLK_ICH PCICLK_ICH 14M_ICH P11

U714

11 39 R816 R895 33 33 R1137 0 PCICLK_MINIPCI P19 MINIPCI_SIO48M

NB

MINI

J713 -PCI

U712

2 X703 14.318MHZ 3

7

R824 R858

P13 P14

ICH4_M

Clock Generator ICS950810

56

U715

R859

33

R472

0

14M_CODEC

P20

+3V

+3V

C804 27P

C794 27P 12 R826 33 PCICLK_CARD

U726

P17

AUDIO CODEC CARDBUS READER LAN

PR731 2K

PR56 0

CORE_CLKEN#

R821 0

R831 10K VTT_PWRGD# +3VS_P 29,30 PR715 100K P28 28 13 R827 33 PCICLK_LAN

U727

P16

U719

SMBCLK SMBDATA

P6 DDR J711 SODIMM P18

PQ8 2N7002

PR59 1M

PR57

0

VCCP_PWRGD

PR717

0

27

16

R828

33

PCICLK_1394

PU703 LTC3728L

10 R825 33 PCICLK_FWH

U724

P23

IEEE 1394 BIOS SYS WINBOND KBC

U15

FS2 001 x 0:00 1:3.3V FS1 0 FS0 1 CPU 100.00 17 R817 33 PCICK_KBC P22

U16

UNIT:MHZ

98

8050 N/B Maintenance

8.3 No Display(2)

****** System Reset Check ******

U10 P25 MAX809

SW2 R7 1K +3VS PWRBTN# 1 P22 18 H8_PWRON P26 P27 P31 Convert GND +3V 3 VCC RESET# 2 PWROK +VCCP PWROK R301 330 RSMRST# +3V 8 H8_RSMRST H8_SUSB W83L950D +5V ICH_PWRBTN# Q42 FDV301N VRMPWRGD U9D ICH_VGATE P13 P14 HPWRGD P4 P5 HCPURST# HPWRGD P2 P3

TC010-PSS11CET

U16 WINBOND KBC

7 ICH_PWRBTN

Power Module

LTC3728L Q31 Convert to

1

U713 BANIAS

VDD3

R531 10K

U21 IMP811 P25

3 4 MN RESET VCC 2 H8_RESET# 25

U714 U715 NORTH BRIDGE ICH4_M 855GM /GME

U727 CARDBUS READER

U15 BIOS

SST49LFOO4A

J714 J708 CDROM HDD CONNECTOR CONNECTOR

P17 P23

P15 44 RSTDRV1# R492 10K Q49 Q41 DTC144TKA R909 0 R476 10K Q37 DTC144TKA Convert to

SUSB# +3V

U9A PCIRST#0 JL3 3

1 2

PCIRST#

P15

5

RSTDRV2# P18 92 1394_PCIRST# JL1

74AHC08_V JL4 MCH_PCIRST# +3V

U724 1394 VT6307L

4 CARD_PCIRST# P19 J713 26 MINIPCI_PCIRST# JL8 +3V MINIPCI CONNECTOR JL7 5

U9B 6 JL5 KBC_PCIRST# 64

P22

74AHC08_V

U16 WINBOND KBC

P16

JL6 U9C FWH_PCIRST# JL9 7 9 8

LAN_PCIRST#

27

2

U719 LAN Controller RTL8100CL

P11

74AHC08_V 13 TV_PCIRST# JL10

U2 TV_CARD CH7011A

99

8050 N/B Maintenance

8.3 No Display(3)

****** VGA Controller Checking ******

R16 1M F1 2A +3V

Q9 SI4835DY 3 2 1 S R19 10K G D 8 7 6 5 R801 0 FPVDEN R22 0 C14 0.22U L15 120Z/100M 1,2,3 P5 ICLKAM ICLKAP IYAM0 R361 R363 R349 R350 R353 R357 R1176 R1177 R1178 R1179 0 0 0 0 0 0 0 0 0 0 TXCLKTXCLK+ TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXOUT3TXOUT3+ 15 13 28 26 22 20 P12

U714

IYAP0 IYAM1

J2

855GM/GME

IYAP1 IYAM2 IYAP2 IYAM3 IYAP3

LCD CONNECTOR

27 25 21 19

+3V

P14

R11~R14 10K*4 RP26 0*4 PANEL_ID[0..3] 6,7,10,14

U715 ICH4_M

100

8050 N/B Maintenance

8.3 No Display(4)

****** Back Light & Cover Switch Checking ******

+3V To U713 in this page R372 10K P4 +3V PWROK D15 BAT54 VDD3S P12 DVMAIN L17 120Z/100M 1,2

U714 855GM

27

L18

120Z/100M

3

R380 H8_ENABKL R383 0 D16 BAT54 10K

J1

R323 0 ENABKL_VGA_C L10 120Z/100M 4

ENABKL_NB

R384

0

D2

BAT54

ENABKL_VGA

Inverter

P22 11 35 36 79 BLADJ BATT_R# BATT_G# AC_POWER# BATT_POWER# 8 7 6 5 R5 0 1 2 3 4 L9 120Z/100M 6 8 9 10 11

U16

+3VS U703D 74AHC14_V +3VS U703C 74AHC14_V +3VS U703B 74AHC14_V Q720 DTC114TKA Q719 DTC114TKA

WINBOND KBC

R1152 13 BATT_LED#

SUSB# P13

C947 4.7U 1M R1140 180K PWROK +3VS

U715 ICH4-M

R373 470K 16 H8_LIDSW# R3 1K

SW1

30V/0.1A

101

8050 N/B Maintenance

8.3 No Display(5)

CPU Core does not exist .

DD_CPU PF2 7A/24VDC PL5 120Z/100M PL4 120Z/100M

D

DVMAIN

S1+

PU9 FDS6694

G

D

PU10 FDS6694

S1-

8 7 6 5

G S

8 7 6 5

24 +5VS_P PR5 10 29

S

3 2 1

3 2 1

PR4

10K

31 23

8 7 6 5 8 7 6 5 8 7 6 5

PL711 0.68UH

PR740 0.001

+VCC_CORE

P13

P31 STOP_CPU# PR32 0 4 21

G

D

U715 ICH4_M

PU12 FDS6694

G

D

PU13 FDS6694

G

D

PU11 FDS6694 PD718 EC31QS04-TE12L

3 2 1

S

S

S

3 2 1

3 2 1

VID0 P3 VID1 VID2 VID3 VID4 VID5

PR52 PR44 PR40 PR34 PR33 PR31

0 0 0 0 0 0

13 14 15 17 18 19

PU3 LTC3734

22 +5VS_P PC12 PC13 0.1U 10U PR104 0 VOS-

U713 CPU BANIAS

+3VS PC18 PR28 576K 1000P PR30 100K PR29 PR38 10 S1PR37 10 S1+ PC11 220P PR19 13.3K PC15 100P 28 1 PR15 PR16 PR43 PR17 56.2k 1.3M 499K 12.7K To Pin12 8 9 11 10 P26 PC21 1000P 13.3K 7 30 2 3 P11 12 From Left

PR729 249K

PQ9 MMBT3904L +3V

+VCC_PWRGD PR59 1M PR57 0 TO

P28

PU703

LTC3728L PR731 2K

+3V

VOS-

R831 10K

G D

6

U712 CLKGEN

ICS950810

28

R821 0

PR56 0 PR58 4.12K DVMAIN

PQ8 2N7002 S PD4 BAT54C 2 VDD5 3 1 PQ10 MMBT3904L PR49 100K +3VS PQ5 2N7002

PR60 43.2K

+2.5VS_DDR

R251 220K

PR50 1M PC28 3300P

Q19 2N7002 PR61 PWRON_SUSB# 0

PU15

LTC3728L RUN/SS

PQ7 2N7002

102

8050 N/B Maintenance

8.4 External Monitor No Display

There is no display or picture abnormal on CRT monitor, but LCD can normally display.

External Monitor No Display

1. Confirm monitor is good and check the cable are connected properly. 2. Try another known good monitor.

Board-level Troubleshooting

Check if J702 are cold solder?

Yes Re-soldering.

No

Display OK?

Yes

Check following parts and signals: Replace faulty monitor. Parts: Replace Motherboard

U715 R6 R10 R785 R138 R136 R137 R783 R135 R139 Q5 Q6 Q7 Q8 L12 L13 L11 L7

Signals:

CRT_IN# DDCK DDDA HSYNC VCYNC RED GREEN BLUE

No

103

8050 N/B Maintenance

8.4 External Monitor No Display

There is no display or picture abnormal on CRT monitor, but LCD can normally display.

R703 +5V_H R6 4.7K +5V_H R1 R10 4.7K Q6 2N7002 L12 120Z/100M CHAGND GND 0 0

855_CRT_DDCK

R1166

0

+3V 855_CRT_DDDA R331 0 Q5 2N7002 R804 802K P4 P13 L13 BEAD_600Z/100M CRT_IN# L11 120Z/100M 14 R9 1K 15 5 P12

+5V_H

855_CRT_VSYNC

Q7 2N7002

U715 ICH

U714 NB

855_CRT_HSYNC Q8 2N7002 L7 120Z/100M

J702

13 3

855GM/ GME

855_CRT_RED R1167 0 L58 220Z/100M

CRT CONNECTOR

12 2

855_CRT_GREEN

R343

0

L59

220Z/100M

855_CRT_BLUE

R344

0

L60

220Z/100M

1 6,7,8,16,17

CHAGND

104

8050 N/B Maintenance

8.5 Memory Test Error

Either on board or extend SDRAM is failure or system hangs up.

Memory Test Error

1.If your system installed with expansion SO-DIMM module then check them for proper installation. 2.Make sure that your SO-DIMM sockets are OK. 3.Then try another known good SO-DIMM modules.

Board-level Troubleshooting

Check following parts and signals Parts:

U714 J711 J712 U712 R979 R1040 R1030 R1031 R1011 R1016 R948 R949 R950 R955 R340 C337 C346

Signals:

MD[0..63] SMBCLK SMBDATA DQS[0..7] DM[0..7] MCB[0..7] MA0 MA3 MA[6..12] WE# CAS# RAS# BA[0,1] NB_DM8 NB_DQS8 CLK_DDR[0..5] CLK_DDR[0..5]#

Test OK? No

Yes

Replace the faulty SDRAM module. Replace Motherboard

If your system host bus clock running at 100MHZ then make sure that SO-DIMM module meet require of DDR 333.

No

Replace the faulty SDRAM module.

Yes

105

8050 N/B Maintenance

8.5 Memory Test Error

Either on board or extend SDRAM is failure or system hangs up.

+3V +1.25V_DDR +2.5VS_DDR 197

RP29~RP43 56*8

R340 75

C337 0.01U

C346 0.1U

NB_MD[0..63] NB_DQS[0..7] NB_DM[0..7] P4 P5 NB_CB[0..7] NB_MA0 NB_MA3 NB_MA[6..12]

R948,R949... R1011,R1016.. R950,R955.. R977,R978.. R972~R975 R1032~R1036 R969~R971 R1030 R1031

10 10 10 10 10 10 MA0 MA[6..12] WE# RAS#

MD[0..63] DQS[0..7] DM[0..7] MCB[0..7] MA3 CAS# BA[0,1]

P6

J711 & J712

U714 NB 855GM /GME

NB_WE# NB_RAS# SMA [1,2] SMA[4,5] CKE [0~3] CS# [0,1]

NB_CAS# NB_BA[0,1] SMAB[1,2] SMAB [4,5]

DDR-SODIMM

NB_DM8 NB_DQS8 NB_CLK_DDR[0..5] NB_CLK_DDR[0..5]#

R979 R1040 R335~R338 R319 R359 R1103~R1106 R320 R360

10 10

NB_DM8 NB_DQS8 NB_CLK_DDR[0..5] NB_CLK_DDR[0..5]#

10*12

P11

29 30 VDD3S +3V

SMBDATA SMBCLK

193 195

U712 CLOCK GENERATOR

P13

R315 2.2K SMB_DATA

R318 2.2K

Q21 2N7002

R316 10K

R317 10K

U715 ICH4-M

SMB_CLK

Q22 2N7002

0.6MM/200P /H5.2

106

8050 N/B Maintenance

8.6 Keyboard (K/B) /Touch-Pad (T/P) Test Error

Error message of keyboard or touch-pad failure is shown or any key does not work.

Keyboard or Touch-Pad Test Error Check U16, J4,J5 for cold solder? No Correct it. Board-level Troubleshooting

Yes

Re-soldering

Is K/B or T/P cable connected to notebook properly? Yes

No

Check following parts and signals: Parts Replace Motherboard

U16 U715 F701 L716 L36 L37 R132 R151 J4 J5

Try another known good Keyboard or Touch-pad.

Signals

VDD3 VDD_AVREF KBC X+ KBC XH8/T_CLK H8/T_DATA KI[0:7] KO[0:15] PWRBTN# KBD_US/JP#

Test Ok?

Yes

Replace the faulty Keyboard or Touch-Pad

No

107

8050 N/B Maintenance

8.6 Keyboard (K/B) /Touch-Pad (T/P) Test Error

Error message of keyboard or touch-pad failure is shown or any key does not work.

VDD3_AVREF

R414

0

72 +5V

F701 0.5A/POLYSW

L716 120Z/100M 6

VDD3 71

9

T_DATA

L36

120Z/100M

5 P23

C445 0.1U

C448 0.1U

C449 10U 30

6

T_CLK SW4

L37

120Z/100M

4

SW_LEFT P22 SW_RIGHT P11 17 PCICK_KBC R817 33 PCICLK_KBC 70

R132

0

3

J4

R151

0

2

U712 CLKGEN

SW5

U16

+3V VDD3 R392 8.2K SERIRQ 69 55~62 LAD[0..3] 65~68 39~54 KI 0~7 KO 0~15 17~24 1~16 GND

1

WINBOND KBC

RP44 4.7K*8

P13 U9 KBC_PCIRST# 64 29

P22 KBC_XR404 1M

U715

LFRAME#

63 28 KBC_X+

H8_SUSB

22 1 2 X1 8MHz

J5

+3V

ICH4_M

SUSB# Q49 DTC144TKA C447 22P

C450 22P

R165 10K

KBD_US/JP#

25

108

8050 N/B Maintenance

8.7 USB Port Test Error

An error occurs when a USB I/O device is installed.

USB Test Error

Check if the USB device is installed properly. (Including charge board.)

Board-level Troubleshooting

Test OK? No

Yes

Correct it Replace Motherboard Check following parts and signals: Parts: Signals:

L22 L708 R701 C701 R706 C713 C703 C709 +5VS USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2USBOC0# +VCC_USB_0 +VCC_USB_1 +VCC_USB_2

Replace another known good USB device.

Re-test OK?

Yes

Replace the faulty part

U715 U705 U701 U712 J701 J706 L701 L702 L2 L5

No

109

8050 N/B Maintenance

8.7 USB Port Test Error

An error occurs when a USB I/O device is installed.

+5VS R877 33 P11 39 3 4 C703 1U USB_OC0#

U701

VIN0

P15 1 VOUT0 VOUT1 5 R701 33K + C701 150U GND

L702 120Z/100M

+VCC_USB_0

1 P15

USBCLK_ICH

U712 CLK-GEN

VIN1

2

L701 120Z/100M

+VCC_USB_1

A1

J701

USBP0+ P14 1 4

L2 90Z/100M 2 3 L5 90Z/100M 1 2 3

USB Port Connector

3

USBP0USBP1+

2 A3

U715

USBP1-

4

A2 4 A4

ICH4_M

USB/4PX2/DIP +5VS 3 4 C709 1U USB_OC1#

U705

VIN0

P15 VOUT0 GND 2 1

L708 120Z/100M

+VCC_USB_2

1

VIN1

VOUT1 5 R706 33K

+ C713 150U

P15

J706 USB Port Connector

USBP2+ 1 4

L22 90Z/100M 2 3

3

USBP2-

2 4 GND1 GND2

USB/4PX1

110

8050 N/B Maintenance

8.8 Hard Disk Drive Test Error

Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to hard disk.

Hard Driver Test Error

1.Check the BIOS setup 2.Replace another good hard driver or cable try again

Board-level Troubleshooting Check following parts and signals:

Re-boot OK? No

Yes Replace the faulty parts.

Parts:

U715 J714 Q37 Q41 L733 R476 R492 R1081 R1074

Signals:

PCIRST#0 PIORDY PDD[0..15] PDA[0..2] PDIOR# PDIOW# PDDACK# PDCS1# PDCS3# PDDREQ IRQ14 +5V +5V_HDD

Check the system driver for proper installation.

Replace Motherboard

Re - Test OK? No

Yes

End

111

8050 N/B Maintenance

8.8 Hard Disk Drive Test Error

Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to hard disk.

+3V

+5V_HDD L733 120Z/100M

R1081 4.7K

R1074 8.2K

+5V

3

PD_D[0..15]

27~42

P15

PDIOW# P11 PDIOR# PIORDY PDDACK# IRQ14 PDA[0.. 2]

22 20 18 16 14 9,10,12 8 7 +5V

J714

U715

HDD CONNECT

ICH4_M

PDCS1# PDCS3#

PCIRST#0

R492

10K

RSTDRV1#

44

R476 10K Q41 DTC144TKA Q37 DTC144TKA

112

8050 N/B Maintenance

8.9 CD-ROM Test Error

CD-ROM driver can't run normally,maybe an error message is shown when reading data from CD-ROM.

CD-ROM Driver Test Error

Check the CD-ROM driver for proper installation.

Board-level Troubleshooting Check following parts and signals:

Test OK? No

Yes

Parts: Correct it

U715 J708 Q37 Q41 R492 R476 R909 R833 R834 L723

Signals:

PCIRST#0 CDROM_COMM RSTDRV2# SIORDY SDD[0..15] SDA[0..2] SDIOR# SDIOW# SDDACK# SDCS1# SDCS3# SDDREQ IRQ15 +5V +5V_CDROM CDROM_LEFT CDROM_RIGHT

Try another known good compact disk.

Replace Motherboard

Re - Test OK?

Yes

Replace the faulty parts.

No

113

8050 N/B Maintenance

8.9 CD-ROM Test Error

CD-ROM driver can't run normally,maybe an error message is shown when reading data from CD-ROM.

+3V

+5V_CDROM

+5V R833 4.7K R834 8.2K

L723 120Z/100M

38~42

SD_D[0..15] P11 SDIOW# SDIOR# SIORDY SDDACK# IRQ15

6~21

25 24 27 28 29 31,33,34 35 P15

U715

ICH4_M

J708

SDA[0.. 2] SDCS1# SDCS3# +5V

CDROM CONNECT

36

PCIRST#0

R492

10K

R909

0

RSTDRV2#

5

R476 10K Q41 DTC144TKA P20 Q37 DTC144TKA

18 20 19

C507 C513 C515

1U 1U 0.22 R549 6.8K R546 6.8K

R538 R547 R550 R537 6.8K

6.8K 6.8K 0

CDROM_LEFT CDROM_RIGHT CDROM_COMM

1 2 3

U726 AUDIO CODEC

114

8050 N/B Maintenance

8.10 Audio Failure

There is trouble with the sound from speaker or completely no sound

Audio Failure

1. Check if speaker cables are connected properly. 2. Make sure all the drivers are installed properly.

Board-level Troubleshooting Check following parts and signals: Parts: Signals:

D715 Q711 Q713 Q23 D17 D19 D22 U18 ROUT+ ROUTSBSPKR CARDSPK# PC_BEEP AVDD ACRST# ACSDOUT ACSDIN0 ACBITCLK 14M_CODEC MIC_VREF 2464_VREF AMP_LEFT AMP_RIGHT SUB_LEFT SUB_RIGHT AMP_SHUTDOWN ROUT+ ROUTLOUT+ LOUT-

Test OK? No

Yes Correct it.

Try another known good speaker, CD-ROM.

Replace Motherboard

U18 U17 U524 U726 U715 U712 U19 U725 J3 J7 J705 J719 L741

Re-test OK? No

Yes

Replace the faulty parts.

115

8050 N/B Maintenance

8.10 Audio Failure(Audio Codec)

There is trouble with the sound from speaker or completely no sound

+5V

U18

IN GND EN

P20 OUT

VA 5 4 ADJ

U17

VCC

P20 To U715 A 1 2 C457 C458 0.1U 0.1U CARDSPK# SBSPKR

INTERNAL MIC1

+ -

J719 EXTERNAL MIC JACK

BEAD_600Z/100M R1150 R1155 0 0

L734

Y

B NC7S32 P17 L70 BEAD_600Z/100M

MIC5205BM5 R438 10K L66 120Z/100M C456 1U

C467 0.01U

U727 CARD READER

CB710

L744 BEAD_600Z/100M

+3V PC_BEEP AVDD

1,9 12 25,38

21

MIC

C975

1U

R1157

0 P20

R535 P20

0

R1154

4.7K 2464_VREF

R1153

0

J721 Line/In Jack

28

R532

0 L76

To Next Page U19

U726

SBSPKR P14 ACRST# ACSDOUT 11 5 R530 R812 ACBITCLK L69 22 0 0 R498 22 ACSYNC 8 10 6

24

C969 1U C974 1U

R519 0 R324 0

24

BEAD_600Z/100M L53 BEAD_600Z/100M L751 120Z/100M

AUDIO CODEC ALC655

35

U715 ICH4_M

+5V

L67

120Z/100M

7,18,19

ACSDIN0

AOUT_L

R1130

0

R1135

0

AMP_LEFT

C484 C480

1U 1U

5 6

P21

U524

36 AOUT_R R1127 0 R1128 0 AMP_RIGHT C492 C497 1U 1U 20 23 TPA0212_GND

AMP

P11

TO NEXT PAGE J720 56 R859 33 14M_CODEC R472 0 2 48 SPDIFOUT TO NEXT PAGE D22 47 EAPD

TO NEXT PAGE U19 SUB_LEFT TO NEXT PAGE U19 SUB_RIGHT

U712 CLKGEN

ICS950810

116

8050 N/B Maintenance

8.10 Audio Failure(Audio Amplifier & Subwoofer)

There is trouble with the sound from speaker or completely no sound

From Previous Page U726 SPDIFOUT 15,17 DEVICE_DECT VA

21 16 P21 4

ROUT+ ROUT-

L52 L50

600Z/100M 600Z/100M

J7 Internal Speaker Connector J3 HDR/MA-2

R322 4.7K

R1183 10K L754 600Z/100M 600Z/100M

J720

P21

HP/OPT CONNECTOR

AGND

L755

LOUT+ LOUTC474 100U + C474 + C489 100U

L14 L16

600Z/100M 600Z/100M DECT_HP#OPT L55 L757 600Z/100M R329 R528 22 22 L80 L78 600Z/100M 600Z/100M +3V L758 600Z/100M Q711 DTA144WK 600Z/100M LED Drive IC GP1FD310TP

U524 AUDIO AMP TPA0212_GND

9

+5V

R1158 10K D715 BAW56

DEVICE_DECT# R1185 10K OPTIN# VA Q713 +3V +5V From Previous Page U726 D22 BAT54C EAPD R367 10K R477 AMP_SHUTDOWN DEVICE_DECT# Q23 DTC144TKA 0 0 1 1

DECT_HP#/ OPT REMARK 0 1 0 1 HP in OPT in No this condition No device

VDD3S

R906 0 P13 R905 8.2K

Q38

DEVICE_DECT To U524

U715 ICH4_M

R445 P2 0 KBC_MUTE VA D27 RLS4148 U19 LMV822 R511 C482 100 0.15U R463 R479 22.1K 22.1K 3 1 SUB_RIGHT 2 C496 SUB_OUTR 0.22U R502 8.2K D17 RLS4148 R1125 0 1 P21 C471 R1122 From Previous Page U726 2464_VREF D19 RLS4148 80

U16 WINBOND KBC

1000P 2.1K 5 8 R26 R27 0 0 P21

Subwoofer Speaker Connector

J705

R510 C490 0.15U R509

22.1K 22.1K

5 7 6 C483 SUB_OUTL 0.22U R496 8.2K 4

U725 LM4871

6 L63 120Z/100M

HDR/MA-2 +5V

SUB_LEFT

117

8050 N/B Maintenance

8.11 LAN Test Error

An error occurs when a LAN device is installed.

LAN Test Error

1.Check if the driver is installed properly. 2.Check if the notebook connect with the LAN properly. Board-level Troubleshooting Test OK? No Check if BIOS setup is ok. Replace Motherboard Re-test OK? No

118

Check following parts and signals: Parts:

U719 U717 U723 J709 L732 L735 L737 L51 L49 Q709 X706 R1101 R1111 R1115 R907 R211 R212

Signals:

EECK EEDI EEDO EECS PJRX+ PJRXPJTX1PJTX+ LAN_XTANL1 LAN_XTANL2 PCICLK_LAN LAN_WAKE PCI_AD[0..31] PCI_C/BR#[0..3] PCI_PAR LAN_PCIRST# PCI_STOP# AVDDL DVDD SB_PME# PCLKRUN# PCI_DEVSEL# PCI_FRAME# PCI_INTE# PCI_REQ3 PCI_IRDY# PCI_SERR

Yes

Correct it.

Yes Correct it.

8050 N/B Maintenance

8.11 LAN Test Error

An error occurs when a LAN device is installed.

+3VS AVDDL 26,41,56,71 84,94,107 L737 +2.5VS_DDR L732 120Z/100M L735 VDD3S +3VS P16 93C46 R907 10K R211,R212,R241... 8.2K*11 SB_PME# PCLKRUN# PCI_FRAME# PCI_TRDY# PCI_SERR# PCI_GNT3# PCI_INTE# PCI_PERR# PCI_STOP# 31 1 PCI_DEVSEL# 65,68,61,29,25 MDI0+ 2 3 L51 1 4 P16 PMDI07 PMDI0+ 8 9 10 15 16 PJTX+ PJTX1PJRX+ PJRXR152 75 RP27 0*4 1 P16 2 3 6 120Z/100M 12 106 EECS 4 DVDD 120Z/100M 3,7,16,20 111 24,32,45,54,64 78,99,110,116,126 109 108 EECK EEDI EEDO 1 2 3 CS P16 SK DI DO VCC 8 C911 1U GND 5

+3VS

R1110

3.6K

U723

J709 LAN CONNECTOR

P13

PCI_IRDY# PCI_REQ3# PCI_PAR

63,67,70,75,69

2

MDI0-

U719

30 5 MDI1+ 2 3 PCI_C/BE#[0..3] LAN_PCIRST# PCI_AD[0..31] 76 44,60.. 33,34... L49 1 PMDI1+ 2

U717

11

MCT4

MDO2+ MD23MDO3+ MDO3-

4 5 7 8

U715 ICH4_M

LAN Controller

27 6 +3VS MDI1-

14 4 PMDI11

MCT3

R930 75

RTL8100CL

PCI_AD18 Q709 DTC144TKA LAN_WAKE 105 121 LAN_XTAL1 R947 100 LF-H80P

R1115 10K R1111 0

122

LAN_XTAL2 R1101 X706 1M

P11

1 13 PCICLK_LAN 28

2 25MHZ

U712 ICS950810

C914 27P

C915 27P

119

8050 N/B Maintenance

8.12 Modem Test Error

An error occurs when run the modem

MODEM Test Error

1.Check if the driver is installed properly. 2.Check if the notebook connect with the phone LAN properly.

Board-level Troubleshooting

Check following parts and signals: Test OK? No Replace a known good modem Replace Motherboard Yes Correct it. Parts:

J717 J715 U726 R1132 C937 R498 L69 R1120 R1131 L724 F2

Signals:

+5V +3VS +3V MONO_OUT ACSDOUT ACRST# ACSYNC ACBITCLK ACSDIN1 MODEMP MODEMN

Re-test OK? No

Yes Correct it.

120

8050 N/B Maintenance

8.12 Modem Test Error

An error occurs when run the modem

10,18 17 +3VS P20

+5V

+3V

21

R1132

4.7K

16

37 P20

C937

0.1U

MONO_OUT

1

J717

5 ACSDOUT 23

MODEM CONNECTOR

U726 ALC555

11

ACRST#

25

10

ACSYNC

22

6

R498

22

L69

0

R1120

22

ACBITCLK

30

P14 R1131 22 ACSDIN1 24

U715 ICH4_M

C148 C806 1000P 1000P

Phone Lan Connector HDR/MA-2

P20

2

2 1

3 L724 4 50UH

MODEMP

A2

P16

Lan Connector RJ11-2P /RJ45-8P

JP, use 4pcs of 2kV 1000P cap US, use 2pcs of 2kV 1000P cap

J709

J715

1 F2

MODEMN

A1

UK, use 4pcs of 3kV 1000P cap

MINISMDC014-2

121

8050 N/B Maintenance

8.13 Mini PCI Test Error

An error message is shown after Mini PCI device is installed or the Mini PCI device does't work.

Mini PCI Test Error

1.Please check if the Mini PCI device is installed properly. 2.Confirm Mini PCI device driver is installed ok.

Board-level Troubleshooting

Check following parts and signals: Parts:

Signals

PCI_AD[0:31] PCI_C/BE# [0:3] PCI_REQ2# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_INTD# PCI_RESET# PCI_GNT2# PCI_SERR# CLKRUN# PCI_PERR# LAD [0:3] LFRAME# LRDQ0# WIRELESS_PD# MINIPCI_PME# SIO_48M PCICLK_MINIPCI

Yes Test OK? No Please try another known good Mini PCI device. Please replace Motherboard Correct it

U715 J509 U712 U9 Q704 R1137 R1079 R1007

Re-test OK?

Yes

Please change the faulty part then end.

R1077 R1075 R1091

No

122

8050 N/B Maintenance

8.13 Mini PCI Test Error

An error message is shown after Mini PCI device is installed or the Mini PCI device does't work.

+3V +5V 1897

R179 R211.. PCI_INTD# PCI_GNT2# PCI_REQ2# P13 P14 PCI_PERR# PCLKRUN# PCI_IRDY# PCI_SERR# PCI_STOP# PCI_DEVSE# PCI_FRAM# PCI_TRDY#

+3V

R1007

10K

13

R1068

R1080

R1083

P19 WIRELESS_PD# 14,24

U715

PCI_AD[0..31]

ICH4_M

LAD[0..3] LFRAME#

PCI_C/BE#[0..3] LRDQ0#

PCI_AD17 R1075 R1091 MINIPCI_LPCDRQ#

R1092

100

48

J713

+3V

MINIPCI CONNECTOR

PCIRST#

9 10 +3V

U9C 8 JL8 R1077 0 26

Q704 SB_PME# R915 0 MINIPCI_PME# 34

P11

39

R895

33

SIO_48M

R1137

0

121

U712 ICS950810

11

R816

33

PCICLK_MINIPCI

R1079

0

25

123

8050 N/B Maintenance

8.14 CardBus & Reader Test Error

An error occurs when a PC card device is installed.

PC Card Slot Failure

1. Check if the PCMCIA CARD device is installed properly. 2. Confirm PCMCIA card driver is installed ok.

Board-level Troubleshooting Check following parts and signals: Parts: Signals

AD[0..31] C/BE# [0..3] DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# SERR# P_REQ0# SERIRQ PCIRST# P_GNT0# PIRQA# SUSB# RI# PCLK_CARD VCC5_EN# VCC3_EN# VPPD0 VPPD1 +VPPOUT +3V +5V

Test OK? No

Yes

Correct it

U727 J716 U728 J6 U9 R186 R180 R211 R212 R1121 R1129 R826 R1203

Try another known good PCMCIA card device.

Replace Motherboard

Re-test OK? No

Yes

Change the faulty part then end.

124

8050 N/B Maintenance

8.14 CardBus & Reader Test Error

An error occurs when a PC card device is installed.

+3V

+3V R211, R212... 8.2K*7 R186 8.2k R180 R231 8.2k*2 PCI_AD[0..31] P13 PCLKRUN# PCI_DEVSEL# PCI_FRAME#

R1201 R1199 PCI_AD20

10K*2 VCCD0# R1202 100 VCCD1# VPPD0

VCC5_EN# VCC3_EN# VPPD0 VPPD1

1 2 15 14 P17

+CARD_VCC

17,51

+VPPOUT

18,52

PCI_IRDY# PCI_TRDY#

PCI_STOP# PCI_PERR#

VPPD1

U728

P17

PCI_GNT0#

U715

PCI_REQ0# PCI_SERR# SERIRQ

P17

+3V R1121 R1129 10K 10K

3,4 16 8 5,6

TPS2211A

ICH4_M

SUSB# R1200 4.7K U9 8 9 PCI_PAR PCI_C/BE#[0..3] JL7 CARD_PCIRST#

U727 CardBus Reader

+5V

10

J6

CCBE[0..3]#

7,12,21,61 36,67 2~6,8~11... 43,57 4732,40 48~50 13,15,53 59,62,63 14,16,20 54,58,60 19

CB710

CCD2# CCD1# CAD[0..31] P11 12 R826 33 PCICLK_CARD R2_ A18 CBLOCK# CPAR CSERR# CPERR# CFRAME# R1213 33 R2_ D2 CSTOP# CGNT# CAUDIO CINT# CRST# CVS[1,2] R2_ D14 CDEVSEL# CTRDY# CSTSCHG CIRDY# CREQ# CCLK

FM/34 PX2/1. 27MM

U712 CLKGEN

ICS950810

20,27,29

+SD_MSVDD R1198 10 SDCD# SD_WP# SD_CLK SD_CMD SD[0..3]

SD Card MS Card

7 1,4,6 8~11

P17

J716 MA/15PX2/ST

5 2,12,14

R1203

10 MS_INS# MS_BS

MS_SCLK MS_SDIO

125

8050 N/B Maintenance

8.15 TV ENCODER Test Failure

An error occurs when using the computer as TV.

TV Fail

1. Check if the TV device is installed properly. 2. Confirm TV driver is installed ok. Board-level Troubleshooting Test OK? No Yes Correct it.

U2 J704 U714 U715 U9 Q702 Q712 L56 L19 L20 C17 C19 C344 R59 R807 R395 R162 R113 R114 R157 R111 R112 R115 R128 R147 R1240 R763 R766 X701

Check following parts and signals: Parts: Signals

DOVCD[0..11] POUT/DET# TV_DDDA TV_DDCK DVOVREF TV_PCIRST# 855_TV_COMP 855_TV_LUMA 855_TV_CRMA DVOCCLK DVOCCLK# DVOCVSYNC DVOCHSYNC XIN XOUT

Check if BIOS setup is ok. Replace Motherboard Re-test OK? No Yes Correct it.

126

8050 N/B Maintenance

8.15 TV ENCODER Test Failure

An error occurs when using the computer as TV.

+1.5V

+3V

XIN 1 X701 2 14.318MHZ XOUT

42

43

R59 1K R807 10K R935 10K

C52 20P

C56 20P P26 DVOVREF 3

P4

R162

0

Q702 2N7002

TV_DDCK

15

U714 855GM/ GME

R113 R114,R157 R125,,R128,R147

0

Q712 2N7002 DVOCCLK DVOCCLK# DVOCVSYNC DVOCHSYNC

TV_DDDA

14

U2

0*5 POUT/DET# 4,5,46,56,57

R111,R112,,R115..

0*12

DVOCD[0..11]

50~55,58~63

CH7011A

U9 10 P13 9 8 JL10 TV_PCIRST# 13

U715 ICH4_M

L56

P11

120Z/100M 33P R1240 0 855_TV_COMP 39

7

C344

J704 TV_CARD CONNECTOR

4

L19 C17

120Z/100M 33P R763 0 855_TV_LUMA 37

L20 6 C19

120Z/100M 33P R766 0 855_TV_CRMA 38

127

8050 N/B Maintenance

8.16 IEEE 1394 Test Failure

An error occurs when a IEEE 1394 device is installed..

IEEE 1394 Fail

1. Check if the 1394 device is installed properly. 2. Confirm 1394 driver is installed ok. Board-level Troubleshooting Test OK? No Yes Correct it.

U724 U722 J718 U9 U712 U715 L743 L746 L740 L83 R1117 R828 R1116 R1142 R1141 X707 PCI_AD[0..31] PCI_C/BE# [0..3] PC_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_PAR PCI_PERR# PCI_REQ1# PCI_PME# +3V,+3VS +PHYVDD 1394_PCIRST# PCI_GNT1#EE CS_1394 EECK_1394 EEDI_1394 EEDO_1394 TPBIAS TPA+_6307 TPA-_6307 TPB+_6307 TPB-_6307 1394_AVCC XI XO

Check following parts and signals: Parts: Signals

Check if BIOS setup is ok. Replace Motherboard Re-test OK?

No Yes

Correct it.

128

8050 N/B Maintenance

8.16 IEEE 1394 Test Failure

An error occurs when a IEEE 1394 device is installed..

+PHYVDD +3V +3V L743 120Z/100M R211, R212, R218... 8.2K +3VS L746 120Z/100M PCI_AD[0..31] 5~28,97~120 32 EECK_1394 2 SK PCI_AD21 P13 PCI_C/BE#[0..3] PCI_FRAME# PCI_GNT1# PCI_DEVSEL# PCI_REQ1# PCI_TRDY# PCI_INTG# PCI_IRDY# PCI_STOP# 4,15,107,122 123,126... PCI_PERR# R1117 100 108 31 EEDI_1394 3 62,65,75 76,89,90 29 EECS_1394 1 1394_AVCC 24,8,20... 39,49 VCC0~7 VCCRAM +3V 8 VCC

CS

P18

U722 93C46

DI

P18

30

EEDO_1394

4 DO

U715 ICH4_M

PCI_PAR

3

U724

PCI_PME# 1 2 U9 3 JL2 1394_PCIRST# 92 37 70 TPB-_6307 3 2 4 1 L740 120Z/100M 2 1 P18

VT6307L

71

TPB+_6307

J718 1394 CONNECTOR

72 P11 16 R828 33 PCICLK_1394 93

TPA-_6307 3 2 4 1 L83 120Z/100M

3

U712 ICS950810

73 XI 60

TPA+_6307

4 R1143 54.9 R1144 54.9 R1142 54.9 R1141 54.9

R1116 X707

1M

XO

61 C965 270P R1148 4.99K

24.576MHZ C939 10P C932 10P 74 TPBIAS

129

8050 N/B Maintenance

9. Spare Part List(1)

Part Number Description

442672600031 AC ADPT ASSY;19V,3.16A,DELTA,706 361400003030 ADHESIVE;ABS+PC PACK,G485,CEMIDA 361400003005 ADHESIVE;HEAT,T RANSFER,HTA-48(W) 441681730001 BATT ASS'Y;11.1V,4.0Ah,LI,BL3244 441681730002 BATT ASSY;11.1V,4.0Ah,LI,CASE CL 441681730003 BATT ASSY;11.1V,4.0Ah,LI,CORE PA 338536010006 BATTERY;LI,3.6V/2.0AH,18650,PANA 340680900025 BEZEL ASSY;DVDRW,MKE,UJ815,8050 242670800113 BFM-WORLD MARK;WINXP,7521N 340680900006 BRACKET ASSY;SYSTEM,8050 340680900009 BRACKET ASSY;TP,8050 342672200010 BRACKET;CD-ROM,8500 322680900001 CABLE FFC;TP,8050 272075103408 CAP ;0.1U CR 50V 10% 0603 X7R S 272005104705 CAP ;1U CR 50V +80-20% 0805 Y5V 272075101404 CAP; 0.001U CR 50V 10% 0603 X7R 272075471409 CAP; 0.0047U CR 50V 10% 0603 X7 272075223702 CAP; 0.22U CR 50V +80-20% 0603 272105103702 CAP;.01U ,50V,+80-20%,0402,SMT 272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S 272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S 272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S 272075473401 CAP;.047U,50V,10%,0603,X7R,SMT 272102473402 CAP;.047uF ,16V ,+-10%,0402,X7R, 272072824401 CAP;.082U ,16V ,10%,0603,X7R,SMT C10,C11,C12,C15,C3,C5,C6,C7,C8 C14A,C14B,C4A,C4B C13 C4 C1,C2,C20A,C24,C25 C171,C176,C337,C339,C343,C386 C13,C8 C11,C3 C9 C313 C841 C16

Price(US)

Part Number Description

272071154401 CAP;.15U ,CR,10V,10%,0603,X7R,SM 272105104701 CAP;.1U ,16V,+80-20%,0402,SMT 272102104401 CAP;.1U ,CR,10V,10%,0402,X5R,SM 272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM 272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM 272073104401 CAP;.1U ,CR,25V,10%,0603,X7R,PR 272005104402 CAP;.1U ,50V,+/-10%,0805,X7R,SMT 272005104404 CAP;.1U,CR,50V,10%,0805,SMT 272102224701 CAP;.22U ,10V ,+80-20%,0402,Y5V, 272071332401 CAP;.33U ,10V ,10%,0603,X7R,SMT 272102334701 CAP;.33U ,CR,10V ,+80-20%,0402,Y 272030102401 CAP;1000P,2KV,10%,1808,X7R,SMT 272105102501 CAP;1000P,50V ,+/-20%,0402,X7R,S 272105102408 CAP;1000P,CR,50V,10%,0402,X7R,SM 272075102403 CAP;1000P,CR,50V,10%,0603,X7R,SM 272105101402 CAP;100P ,50V ,+ -10%,0402,NPO,S 272075101401 CAP;100P ,50V ,10%,0603,COG,SMT 272105101401 CAP;100P ,50V ,5%,0402,COG,SMT 272010101301 CAP;100P,2KV,5%,1206,NPO,SMT,onl 272010101302 CAP;100P,2KV,5%,1206,NPO,SMT,onl 272105100303 CAP;10P ,CR,50V ,5%,0402,NPO,SM 272021106501 CAP;10U ,10V ,20%,1210,X7R,SMT 272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S 272023106502 CAP;10U,25V,M,1210,T2.5MM,X5R,SM 272001106702 CAP;10U,6.3V,+- 20%,0805,X5R,SMT

Price(US)

C482,C490 C1000,C104,C12,C13,C133,C16,C PC44 C17 C12,C6 C22,C7 PC9 PC4,PC51,PC52,PC65,PC66,PC7,P C14,C483,C496,C515 C2 C964 C148,C327,C806 C1006,C1007,C1008,C340,C357,C C960,C962,PC14,PC17,PC18,PC19 C471 C10,C330,C455,C498,C520,C521,C C20,C21 C150,C18,C20,C503 C18

C789,C790,C791,C795,C796,C797 C475 C166,C174,C238,C271,C355,C772 PC703,PC704,PC705,PC721,PC73 C155,C156,C157,C158,C168,C173

130

8050 N/B Maintenance

9. Spare Part List(2)

Part Number Description

272431157507 CAP;150U ,TPC,6.3V,20%,H1.9,7343 272431157512 CAP;150U,6.3V,+/-20%,H2.8,PT,NCC 272105181403 CAP;180P,50V,10%,0402,SMT 272001105403 CAP;1U ,10%,10V ,0805,X7R,SMT 272012105401 CAP;1U ,CR,16V ,10%,1206,X7R,S 272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, 272102105701 CAP;1U ,CR,6.3V ,80-20%,0402,Y 272071105403 CAP;1U ,10V ,10%,0603,X5R,SMT 272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y 272071225401 CAP;2.2U ,CR,6.3V ,10%,0603,X5R, 272105200401 CAP;20P ,50V,+-10%,0402,SMT PC24,PC25,PC61,PC63,PC738 PC3,PC46 C14A,C14B PC701 C1002,C11,C160,C206,C210,C219 C10,C4 C921,C961 C1001,C151,C161,C239,C24,C283 C52,C56 C470,C494,C509,C728,C869 C15A C5 C165,PC11,PC73,PC734,PC75 PC729,PC749 PC775,PC778,PC781,PC784,PC78 C447,C450,C855,C861 C15,C21,C782,C965 C794,C804,C914,C915 PC28,PC56 PC787,PC788 C17,C19,C344 C1 C311,C517,C871,C941,C947

Price(US)

C701,C713,C768,PC712,PC719,PC

Part Number Description

272070475701 CAP;4.7U,CR,6.3V,+80-20%,0603,Y5 272075471401 CAP;470P ,50V,10%,0603,X7R,SMT 272105470402 CAP;47P ,50V ,+ -10%,0402,NPO,S 272030050302 CAP;5P,3KV,5%,1808,NPO,SMT,only 221673150002 CARD BOARD;FRAME,PALLET,8060 221673150003 CARD BOARD;TOP/BTM,PALLET ,8060 221600020252 CART ON;BATT ERY,CAIMAN,PWR 221673120003 CART ON;N-B,8060 431680900003 CASE KIT;8050,INTERGRAT E 335152000026 CFM-BAT;FUSE,THERMAL,NEC,SF91E 242678500005 CFM-INTEL;CENT RINO,NOTEBOOK,8081 273000500115 CHOKE COIL;400uH MIN,120m MAX; 273000150313 CHOKE COIL;90OHM/100MHZ,20%,2012 361200001018 CLEANNER;YC-336,LIQUID,STENCIL/P 331000000302 CON HOLDER;PCMCIA,UP,STANDOFF 0. 291000000023 CON;4-IN-1 MEMORY CARD,MS,SD,XD, 291000000706 CON;BATT ERY,7P,MA,2.5MM,R/A,C103 331710015016 CON;D,FM,15P,3ROW,SUYIN,070912FR 291000622007 CON;DIMM,R/A,200P,.6,H9.2,REVERS 291000152603 CON;FPC/FFC,26P,1MM,R/A,KBD,SMT 331040050018 CON;HDR,BT B R/A,0.8MM,S-T ECH1507 291000023008 CON;HDR,FM,15P*2,0.8MM.H5,R/A,SM 331030044019 CON;HDR,FM.22P*2,R/A,ST,ACE-1A2, 291000021105 CON;HDR,MA,11P*1,ACES,87213-1100 291000021105 CON;HDR,MA,11P*1,ACES,87213-1100

Price(US)

C860,C908 C15B C1,C143,C144,C154,C172,C2,C4,C C19

272105222501 CAP;2200P,50V ,+/-20%,0402,X7R,S 272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT 272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT 272105221403 CAP;220P ,CR,50V ,10%,0402,X7R,S 272431227504 CAP;220U ,4V ,20%,7343,POSCAP,SM 272431227528 CAP;220U,2.5V,TPE-MC,20%,POSCAP, 272105220402 CAP;22P ,50V ,+ -10%,0402,NPO,S 272105271403 CAP;270P ,50V,+-10%,0402,X7R,SMT 272105270303 CAP;27P ,50V ,5%,0402,COG,SMT 272105332402 CAP;3300P,50V,10%,0402,SMT 272431337506 CAP;330U,4V,20%,7343,SMT 272103331401 CAP;33P ,25V ,+/-10%,0402,NPO,S 272023475401 CAP;4.7U ,25V ,10%,1210,X5R,SMT 272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y

L724 L2,L22,L5

J6 J2 J703 J702 J711 J5 J708 J717 J714 CN1 J1

131

8050 N/B Maintenance

9. Spare Part List(3)

Part Number Description

291000013027 CON;HDR,MA,15P*2,ACES,88026-3000 291000013026 CON;HDR,MA,15P*2,ACES,88029-3000 291000013025 CON;HDR,MA,15P*2,ACES,88107-3000 291000020206 CON;HDR,MA,2P*1,1.25MM,H2.57,R/A 291000010209 CON;HDR,MA,2P*1,1.25MM,H4.2,ST,S 291000000203 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM 291000020204 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM 291000010303 CON;HDR,MA,3P*1,1.25MM,H4.2,ST,S 331040004024 CON;HDR,MA,4P*1,H=5.9,R/A,USB,DI 291000010619 CON;HDR,MA,6P,ACES,87151-0607,SM 291000256843 CON;IC CARD,68P,UP,ST ANDOFF 0.0 331000004009 CON;IEEE1394,MA,4P*1,0.8MM,R/A 331870007007 CON;MINI DIN,7P,R/A,W/GROUND,330 291000811008 CON;PHONE JACK,2 IN 1,7.0MM,ALLT 331910002006 CON;POWER JACK,2P,20VDC,5A,DIP 331840010008 CON;ST EREO JACK,10P,W/SPDIF,R/A, 291000920605 CON;ST EREO JACK,6P,W9.5,33184000 331000008033 CON;USB,FM,H15.64,R/A,4P*2,2522A 345677000018 CONDUCTIVE TAPE;LCD,LYNX 331000007025 CONNECT OR;7 PIN,DIP,ALLTOP,C1034 441681730031 CONTACT PLATE ASSY;W4L27T0.15,FU 441674800032 CONTACT PLATE ASSY;W4L27T0.15,S342503100004 CONTACT PLATE;W4L27,1/2R,1/2T,75 342502900001 CONTACT PLATE;W4L27T0.15,7068 342503100002 CONTACT PLATE;W4L63,1/2R,1/4T,75 CON1 J707 J706 J4 J6 J718 J704 J709 PJ701 J720 J719,J721 J701

Price(US)

J716 J1 J2 J3,J7,J705,J715 J710 J2

Part Number Description

340680900004 COVER ASSY;8050 340680900010 COVER ASSY;HDD,8050 340680900012 COVER ASSY;LCD,8050 340680900029 COVER ASSY;MINIPCI,8050 344680900002 cover;battery,8050 344680900015 COVER;CPU,8050 344680900016 COVER;DDR,8050 344680900049 COVER;HINGE,L,8050 344680900011 COVER;HINGE,R,8050 344680900010 COVER;REAR,L,8050 344680900009 COVER;REAR,R,8050 272625470401 CP;47P*4 ,8P,50V ,10%,1206,NPO,S 323767340001 DDR SODIMM MODULE;DDR333,256MB,M 331660020005 DIMM SOCKET;DDR SODIMM 200P, CA0 288111544001 DIODE; 1SR-154-400 400V 1.0A 288110355001 DIODE;1SS355,80V,100mA,SOD-23,SM 288100140007 DIODE;B140,40V,1A,SMA,DIODES,SMT 288100340008 DIODE;B340LA,40V,3A,SMA,DIODES,S 288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 288100054001 DIODE;BAT54,30V,200mA,SOT-23 288100054002 DIODE;BAT54C,SCHOTTKY DIODE,SOT2 288100070006 DIODE;BAV70LT1,70V,225MW,SOT -23, 288100099012 DIODE;BAV99LT1,70V,450MA,SOT-23, 288100056017 DIODE;BAW56LT1,70V,215MA,SOT-23, 288105515001 DIODE;BZV55-C15,ZENER,5%,SOD-80,

Price(US)

CP2

J712 D1 D2 PD706 PD713,PD714,PD718 D24,D7,PD5 D10,D11,D15,D16,D2 D22,PD4 D12,D18,PD702,PD704 PD2,PD3 D704,D715,PD1,PD6,PD7,PD705 PD709

132

8050 N/B Maintenance

9. Spare Part List(4)

Part Number Description

288104148001 DIODE;RLS4148,200MA,500MW,MELF,S 288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT 288101040006 DIODE;SBM1040,10A,SCHOTTKY,POWER 288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM 288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM 344680900048 DUMMY CARD;PCMCIA,8050 523468090014 DVD MULTI ASSY;KME,UJDA-815,8050 272601107506 EC;100U ,6.3V,M,9.3*3.6,-55~105' 227680900003 END CAP;NORMAL,L/R,8050 481680900002 F/W ASSY;KBD CTRL,8050 481680900005 F/W ASSY;SYS/VGA BIOS,8050,INT EG 273000150002 FERRIET CHIP;120OHM/100MHZ,2012, 273000610025 FERRIT E ARRAY;120OHM/100MHZ,ONLY 273000620001 FERRIT E ARRAY;600OHM/100MHZ,2520 273000130001 FERRIT E CHIP;120OHM/100MHZ,1608, 273000150013 FERRIT E CHIP;120OHM/100MHZ,2012, 273000130039 FERRIT E CHIP;130OHM/100MHZ,1608, 273000130015 FERRIT E CHIP;220OHM/100MHZ,1608, 273000130006 FERRIT E CHIP;600OHM/100MHZ,.2A,1 342672400007 FINGER;EMI GROUNDING SMD FINGER 335152000085 FUSE; 128 DC-7A/50V 139 only UC 295000010028 FUSE;0.14A/60V,POLY SWIT CH,PTC,S 295000010048 FUSE;0.5A/15V,POLY SWITCH,SMD 295000010114 FUSE;FAST,1.75A,63VDC,1206,SMT,P 295000100004 FUSE;FAST,1A,63V,1206,THIN FILM U16 U15 L41,L732,L735,L737 FA2 L49,L51,L740,L83 L19,L20,L38,L42,L43,L45,L56,L7 L15,L17,L18,L25,L46,L47,L54,L6 L10,L11,L12,L36,L37,L7,L9 L58,L59,L60 L13,L14,L16,L50,L52,L53,L55,L5 TP45,TP48,TP50 F1 F2 F701 F1 F3 C466,C474,C489,C951

Price(US)

D17,D19,D21,D27,D703 PD701 PD703 D13 ZD3,ZD4

Part Number Description

295000010140 FUSE;FAST,2A,63VDC,1206,SMT ,0433 295000010141 FUSE;FAST,3A,32VDC,1206,SMT ,0433 335152000097 FUSE;LR4-73X,POLY SWITCH,PWR 295000010163 FUSE;NORMAL,7A/24VDC,0433007,120 347105015007 GASKET;1,05,015,007 347105030025 GASKET;1,05,030,025 347105035020 GASKET;1,05,035,020 347105040015 GASKET;1,05,040,015 347108030008 GASKET;1,08,030,008 347110003010 GASKET;1,10,003,010 347110010010 GASKET;1,10,010,010 523402379038 HD DRIVE,40GB,2.5",MHT2040AT,FUJ 523468090002 HDD ASSY;40GB,MHT2040AT,FUJITSU, 451680900031 HDD ME KIT ;8050 340680900013 HEATSINK ASSY;8050 451680900092 HEATSINK ASSY;MPT,8050 451680900091 HEATSINK ASSY;UNP,8050 451999900002 HEATSINK OPTION;8050 343677100001 HEATSINK;NORTHBRIDGE,BANIAS,LYNX 342680900006 HINGE;L,8050 342680900005 HINGE;R,8050 340680900011 HOUSEING ASSY;LCD,8050 340680900005 HOUSING ASSY;8050 451680900071 HOUSING KIT ;8050 344680900003 housing;battery,8050

Price(US)

F1 PF703

PF1,PF2,PF702

133

8050 N/B Maintenance

9. Spare Part List(5)

Part Number Description

291000614793 IC SOCKET ;UPGA479M,479P,MOLEX 324180786389 IC,CPU,BANIAS,1.6GHZ,MICRO-FCPGA 282574008005 IC;74AHC08,QUAD 2-I/P AND,TSSOP, 282574014004 IC;74AHC14,HEX INVERT ER,TSSOP,14 282574132001 IC;74AHCT 1G32,SINGLE OR GAT ,SOT2 284500522001 IC;855GME GMCH,NORTH BRIDGE,BGA, 284507460002 IC;ADT7460,TEMPERATURE MTR,QSOP, 284500655003 IC;ALC655,AUDIO CODEC,LQFP,48P,S 286301117021 IC;AMS1117,VOL REGULATOR,1A,SOT286303107001 IC;AMS3107C,3.3V,1%,VOL REGULATO 286002040001 IC;BQ2040,GAS GAUGE,SO,16P,SMT 286300710002 IC;CB710,CARDBUS/CARD READER,LFG 284507011001 IC;CH7011A,TV ENCODER,LQFP,64P 286302211006 IC;CP2211,POWER DISTRI SW,REV.C1 283467540001 IC;EEPROM,M24C02-WMN6T,2K,SO8,SM 283467540002 IC;EEPROM,M93C46-WMN6T,64*16 BIT 283467530001 IC;EEPROM,S24CC02A,2K,SO8,SMT,ON 283450040001 IC;FLASH,512*8,FWH,M50FW040K1,PL 283449004001 IC;FLASH,512*8,FWH/LPC,PM49FL004 283467490001 IC;FLASH,512K*8,FWH,SST49LF004A, 283467490002 IC;FLASH,512K*8,FWH,W39V040FAP,P 284582801044 IC;FW82801DBM,ICH4-M,BGA,421P 286369229301 IC;G692L293T,RESET CIRCUIT,2.93V 286300690001 IC;GMT 690B,RESET CIRCUIT ,2.93V,S 284595081201 IC;ICS950812,CK408 CLOCK GEN,TSS U715 U21 U10 U712 U9 U703 U17 U714 U706 U726 U6 U13 IC1 U727 U2 U728 IC2 U722,U723

Price(US)

U713

Part Number Description

286104871002 IC;LM4871LD,AUDIO AMP,4Ohm,2.5W, 286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P 286100822002 IC;LMV822,OP AMP,DUAL,CMOS,MSOP, 286302951015 IC;LP2951ACM,VOLTAGE REGULATOR,S 286303728002 IC;LTC3728LX,PWM CTRL,LTC,5X5 QF 286303734001 IC;LTC3734,PWM CONTROLLER,32-QFN 286104173001 IC;MAX4173F,I-SENSE AMP,SOT23,6P 286301414001 IC;MM1414,PROTECTION,T SOP-20A,PR 281101015001 IC;MP1015EM-Z,CCFL CT RL,TSSOP20, 286309167001 IC;RT9167-47CB,200MA LDO REGULAT 286309701001 IC;RT9701,POWER DISTRI SW,SOT23284508100009 IC;RTL8100CL,LAN CONTROLLER,LQFP 286300812002 IC;S-812C,DECECTOR,SOT-89,PRC 286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT 2 286300594001 IC;TL594C,PWM CONTROL,SO,16P 286100212001 IC;TPA0212,AMPLIFIER,T SSOP,24P,S 284506307001 IC;VT6307L,PCI-1394,2PORT,LQFP,1 284583950002 IC;W83L950D-Ver.C,LPC_KBC,LQFP,8 273000990054 INDUCTOR;10UH,D124C,+/-20%,TOKO, 273000990184 INDUCTOR;3.0UH,30%,CDRH5D28,H3.0 273000990186 INDUCTOR;3.0UH,30%,CDRH6D28,H2.8 273000990185 INDUCTOR;3.9UH,30%,CDRH8D43,H4.5 273000990021 INDUCTOR;33uH,CDRH124,SUMIDA,SMT 273000990127 INDUCTOR;IHLP5050CE-01-0.68uH,VI 346503100005 INSULAT OR;5,BAT TERY ASSY,7521Li

Price(US)

U725 PU5 U19 U11 PU14,PU15,PU2,PU703 PU3 PU1 IC4 U1 U18 U701,U705 U719 IC3 PQ11 PU7 U524 U724

PL702,PL703 PL717 PL709,PL713,PL714 PL706,PL707,PL715 PL710 PL711

134

8050 N/B Maintenance

9. Spare Part List(6)

Part Number Description

346503200202 INSULAT OR;BAT T ASSY,ONE ROUND,BL 346681800004 INSULAT OR;BAT T,ASSY,L129W15T 0.25 346680900002 INSULAT OR;CARD READER,8050 346680900010 INSULAT OR;DDR,MINIPCI,8050 346677300001 INSULAT OR;FIBER,UL94V-0,D=17.5mm 346680900005 INSULAT OR;INVERTER,LCD,8050 346680900017 INSULAT OR;L16W8.5T0.05MM,DIALAMY 346680900001 INSULAT OR;MB,8050 346680900007 INSULAT OR;PCB,ASSY,L105,W12T1.0 346680900009 INSULAT OR;PCMCIA,8050 361400003003 JET-MELT ADHESIVES;3478-Q,5/8in* 531020237777 KBD;88,UI,K011818A1,8050,BK 451680900001 LABEL KIT;N-B,8050 242600000145 LABEL;10*10,BLANK,COMMON 242600000145 LABEL;10*10,BLANK,COMMON 242600000439 LABEL;25*6,HI-TEMP,COMMON 242600000439 LABEL;25*6,HI-TEMP,COMMON 242600000378 LABEL;27*7MM,HI-TEMP 260'C 242668300028 LABEL;32*7MM,POLYESTER FILM,HOPE 624200010140 LABEL;5*20,BLANK,COMMON 624200010140 LABEL;5*20,BLANK,COMMON 242600000232 LABEL;6*6MM,GAL,BLANK,COMMON 242680900001 LABEL;AGENCY-GLOBAL,8050 242679900005 LABEL;BAR CODE,(25*10MM)*12pcs,8 242600000157 LABEL;BAR CODE,125*65,COMMON

Price(US)

Part Number Description

242680900005 LABEL;BAT T,11.1V/4.0AH,LI,PANSON 242600000433 LABEL;BLANK,11*5MM,COMMON 242669900009 LABEL;BLANK,60*80MM,7170 242600000452 LABEL;BLANK,7MM*7MM,PRC 242600000452 LABEL;BLANK,7MM*7MM,PRC 242669600005 LABEL;LOT NUMBER,RACE 242600000001 LABEL;PAL,20*5MM,COMMON 242600000315 LABEL;RED ARROW HEAD,PRC 441680900031 LCD ASSY;SAMSUNG,XGA,15.4",LTN15 451680900051 LCD ME KIT;SAMSUNG,15.4",8050 413000020388 LCD;LTN154X1-L02,TFT15.4",XGA,SA 294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190 294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190 294011200034 LED;GREEN,H.8,0603,19-21VGC/TR,S 294011200034 LED;GREEN,H.8,0603,19-21VGC/TR,S 294011200016 LED;GREEN,H0.8,0603,CL-190G,SMT 294011200043 LED;RE/GR,H0.8,L1.9,W1.6,19-22SR 294011200043 LED;RE/GR,H0.8,L1.9,W1.6,19-22SR 416268090001 LT PF;SAMSUNG,15.4",LTN154WX,805 526268090006 LTX;8050/5ADB/40K/9UI9/B5D3A/XL 339115000046 MICROPHONE;-60dB+-2dB,D6.0*H2.7, 291000251246 MINIPCI SOCKET;124P,R/A,0.8MM,H= 346680900011 MYLAR;COVER,LCD,8050 461680900006 PACKING KIT;N-B BOX,8050 227680900002 PAD;LCD/KB,8050

Price(US)

LED4,LED5 LED3,LED6 D32,D33,D34,D35,D36,D37,D38 LED1 LED2

MIC1 J713

135

8050 N/B Maintenance

9. Spare Part List(7)

Part Number Description

224670830002 PALLET ;1250*1080*130,7521N 221673150001 PART ITION;AK BOX,8060 221600050218 PART ITION;BATTERY,MARLIN,CAIMAN, 221673150004 PART ITION;PALLET,8060 221600050219 PART ITION;TOP/BTM,BATTERY,MARLIN 412681300001 PCB ASSY;D/A BD,DA-1A08-A,PWR 412678800001 PCB ASSY;FAX MODEM 56K,1456VQL4A 412673400008 PCB ASSY;MINI-PCI,T YPE IIIB,INTE 316680900003 PCB;PWA-8050 Card Reader_Transit 316680900001 PCB;PWA-8050 M BD 316680900006 PCB;PWA-8050/BATT ,PR AND GA BD 316681300001 PCB;PWA-INVERTER BD (DA-1A08-A); 222670820003 PE BAG;L560*W345,7521N 222503220001 PE BUBBLE BAG;BATTERY,GRAMPUS 273000150033 PHASEOUT;FERRITE CHIP,120OHM/100 411680900011 PWA;PWA-8050,MOT HER BD,INTERGRAT 411680900013 PWA;PWA-8050,MOT HER BD,SMT,INTER 411680900012 PWA;PWA-8050,MOT HER BD,T /U,INTER 411680900008 PWA;PWA-8050-CARD READER TRANSIT 411681300001 PWA;PWA-INVERTER BD,DA-1A08-A,PW 411681300004 PWA;PWA-INVERTER BD,SMT BOT,DA-1 411681300003 PWA;PWA-INVERTER BD,SMT TOP,DA-1 411681300002 PWA;PWA-INVERTER BD,SMT ,DA-1A08411681710001 PWA-PWA-BATT BD;LI,4.4Ah,2P3S,BL 411681710002 PWA-PWA-BATT BD;SMT ,BL3244G095/8 L743,L746 R0E R0B R01

Price(US)

Part Number Description

332810000034 PWR CORD;250V/2.5A,2P,BLK,EU,175 271046017301 RES;.001,2W,5%,2512,CYNTEC,SMT 271045087101 RES;.008 ,1W ,1% ,2512,SMT 271045107101 RES;.01 ,1W ,1% ,2512,SMT 271034127101 RES;.012,1/2W,1%,2010,WSL2010,VI 271586026101 RES;.02 ,2W,1%,2512,SMT 271002000301 RES;0 ,1/10W,5% ,0805,SMT 271061000002 RES;0 ,1/16W,0402,SMT 271071000002 RES;0 ,1/16W,5% ,0603,SMT 271012000301 RES;0 ,1/8W,5% ,1206,SMT 271044100101 RES;0.010,1.5W, 1%,2512,SMT;PWR 271045507103 RES;0.050,1W, 1%,2512,SMT, only 271061010101 RES;1,1/16W,1%,0402,SMT 271061135101 RES;1.3M,1/16W,1%,0402,SMT 271061152501 RES;1.5K ,1/16W,5% ,0402,SMT 271071152302 RES;1.5K ,1/16W,5% ,0603,SMT 271071152302 RES;1.5K ,1/16W,5% ,0603,SMT 271061196212 RES;1.96K,1/16W,1%,0402,SMT 271061100501 RES;10 ,1/16W,5% ,0402,SMT 271061100102 RES;10,1/16W,1%,0402,SMT 271061102312 RES;10.2K,1/16W,1% ,0402,SMT 271061101103 RES;100 ,1/16W,1% ,0402,SMT 271071101301 RES;100 ,1/16W,5% ,0603,SMT 271061104102 RES;100K ,1/16W,1% ,0402,SMT 271071104101 RES;100K ,1/16W,1% ,0603,SMT

Price(US)

PR740 PR742 PR701 PR707,PR711,PR719,PR732,PR73 PR22 L62,L65,L73,L88,R1,R123,R26,R2 PR103,PR104,PR11,PR111,PR120 L69,L719,L728,L744,L747,L751,L PR86 R6 R24A,R24B,R24C PR18 PR16,R1158 R1084,R798 R17 R19 PR710 PR1,R1000,R1001,R1009,R1010,R PR37,PR38,PR5 R496,R502 R1092,R1117,R1202,R208,R257,R R11,R12,R14,R15,R16,R20,R21 PR10,PR112,PR114,PR12,PR30,P R18,R22,R23,R9

136

8050 N/B Maintenance

9. Spare Part List(8)

Part Number Description

271061104501 RES;100K ,1/16W,5% ,0402,SMT 271071104302 RES;100K ,1/16W,5% ,0603,SMT 271061107411 RES;107K,1/16W,1%,0402,SMT 271061103102 RES;10K ,1/16W,1% ,0402,SMT 271061103501 RES;10K ,1/16W,5% ,0402,SMT 271071103302 RES;10K ,1/16W,5% ,0603,SMT 271071103302 RES;10K ,1/16W,5% ,0603,SMT 271061106501 RES;10M ,1/16W,5% ,0402,SMT 271061118211 RES;11.8K,1/16W,1%,0402,SMT 271061127212 RES;12.7K,1/16W,1%,0402,SMT 271061124312 RES;124K,1/16W,1%,0402,SMT 271071127011 RES;127 ,1/16W,1% ,0603,SMT 271071127011 RES;127 ,1/16W,1% ,0603,SMT 271061133311 RES;13.3K,1/16W,1%,0402,SMT 271061137371 RES;13.7K,1/16W,.1%,0402,SMT 271061133101 RES;13.7K,1/16W,1%,0402,SMT 271071131101 RES;130 ,1/16W,1% ,0603,SMT 271071141102 RES;140 ,1/16W,1% ,0603,SMT 271061151102 RES;150 ,1/16W, 1%,0402,SMT 271061153102 RES;15K ,1/16W,1% ,0402,SMT 271061152302 RES;15K ,1/16W,5% ,0402,SMT 271061180101 RES;18.2 ,1/16W,1% ,0402,SMT 271061184302 RES;180K ,1/16W, 5%,0402,SMT 271061183102 RES;18K,1/16W,1%,0402,SMT 271061196213 RES;19.6K,1/16W,1%,0402,SMT

Price(US)

PR69,PR703,PR720,PR83,PR89,R R7 PR35 PR102,PR119,PR4,PR47,PR724,P R1007,R1098,R11,R1103,R1115,R R2 R5,R7,R8 R296,R938 PR116 PR17 PR79 R14A R163 PR19,PR29 PR74 PR96 R911 R37 R220,R446,R791,R850,R884,R912 PR105,PR107,PR122,PR727,PR72 R1008 R838 R1140,R288 PR718,R462,R507 PR36,PR97,PR99

Part Number Description

271061102105 RES;1K ,1/16W,1% ,0402,SMT 271061102303 RES;1K ,1/16W,5% ,0402,SMT 271071102302 RES;1K ,1/16W,5% ,0603,SMT 271061105501 RES;1M ,1/16W,5% ,0402,SMT 271071105301 RES;1M ,1/16W,5% ,0603,SMT 271061222501 RES;2.2K ,1/16W,5% ,0402,SMT 271061222101 RES;2.2K,1/16W,1%,0402,SMT 271061232111 RES;2.32K,1/16W,1%,0402,SMT 271061249211 RES;2.49K,1/16W,1% ,0402,SMT 271061272102 RES;2.7K ,1/16W,1% ,0402,SMT 271061205212 RES;20.5K,1/16W,1%,0402,SMT 271071201301 RES;200 ,1/16W,5% ,0603,SMT 271061201101 RES;200 ,1/16W, 1%,0402,SMT 271061204102 RES;200K ,1/16W,1% ,0402,SMT 271061203701 RES;20K ,1/16W,.1%,0402,SMT 271061203102 RES;20K ,1/16W,1% ,0402,SMT 271061220501 RES;22 ,1/16W,5% ,0402,SMT 271061220102 RES;22,1/16W,1% ,0402,SMT 271061221312 RES;22.1K,1/16W,1% ,0402,SMT 271071221211 RES;22.1K,1/16W,1% ,0603,SMT 271061221313 RES;220 ,1/16W, 5%,0402,SMT 271061224501 RES;220K ,1/16W,5% ,0402,SMT 271071224301 RES;220K ,1/16W,5% ,0603,SMT 271061226311 RES;226K,1/16W,1%,0402,SMT 271061223102 RES;22K,1/16W,1% ,0402,SMT

Price(US)

PR121,PR53,R1006,R141,R328,R5 R1136,R1147,R155,R181,R21,R25 R11 PR106,PR115,PR123,PR26,PR27,P R10,R3 R315,R318 PR6 PR39 PR77 R448,R449 PR113 R1A,R1B R280 PR54,PR55 PR75 PR117,PR21,PR41,PR722,PR726,R R1120,R1131,R306,R329,R424,R4 R253 R463,R479,R509,R510 R1122 R552,R555,R556,R557 R251 R1 PR71 R325,R520

137

8050 N/B Maintenance

9. Spare Part List(9)

Part Number Description

271061249212 RES;24.9K,1/16W,1%,0402,SMT 271061249312 RES;249K,1/16W,1%,0402,SMT 271061270102 RES;27.4 ,1/16W, 1%,0402,SMT 271071274811 RES;27.4 ,1/16W,1% ,0603,SMT 271072287011 RES;287 ,1/10W,1% ,0603,SMT 271061202102 RES;2K ,1/16W,1% ,0402,SMT 271071202301 RES;2K ,1/16W,5% ,0603,SMT 271061332312 RES;3.3K,1/16W,5% ,0402,SMT 271071362101 RES;3.6K ,1/16W,1% ,0603,SMT 271061301112 RES;301 ,1/16W,1% ,0402,SMT 271071301311 RES;301K ,1/16W,1% ,0603,SMT 271061330501 RES;33 ,1/16W,5% ,0402,SMT 271061331304 RES;330 ,1/16W,5% ,0402,SMT 271071331301 RES;330 ,1/16W,5% ,0603,SMT 271071331301 RES;330 ,1/16W,5% ,0603,SMT 271071331301 RES;330 ,1/16W,5% ,0603,SMT 271061333501 RES;33K ,1/16W,5% ,0402,SMT 271071374812 RES;37.4 ,1/16W,1% ,0603,SMT 271061390501 RES;39, 1/16W, 5%,0402,SMT 271061391103 RES;390,1/16W,1% ,0402,SMT 271061412111 RES;4.12K,1/16W,1%,0402,SMT 271071432111 RES;4.32K,1/16W,1% ,0603,SMT 271061442212 RES;4.42K,1/16W,1% ,0402,SMT 271071478101 RES;4.7 ,1/16W,1% ,0603,SMT 271002472301 RES;4.7K ,1/10W,5% ,0805,SMT

Price(US)

PR98 PR729,PR76 R133,R213,R291 R792,R839 R914 PR101,PR124,PR46,PR725,PR731 R12 PR70 R1110 R793,R855 R13,R3 R1213,R816,R817,R818,R824,R82 R1073,R1089,R301,R49,R54 R16,R21,R22 R18,R20,R23 C14 PR45,R701,R706 R898 R225 R876 PR58 R10 R1127,R1130 PR109,PR110,PR2,PR3,PR708,PR PR704,PR706

Part Number Description

271061472501 RES;4.7K ,1/16W,5% ,0402,SMT 271071472302 RES;4.7K ,1/16W,5% ,0603,SMT 271061499212 RES;4.99K,1/16W,1% ,0402,SMT 271061402011 RES;40.2 ,1/16W,1% ,0402,SMT 271071432211 RES;43.2K,1/16W,1% ,0603,SMT 271061432212 RES;43.2K,1/16W,1%,0402,SMT 271061471501 RES;470 ,1/16W,5% ,0402,SMT 271072474101 RES;470K ,1/10W,1% ,0603,SMT 271061474501 RES;470K ,1/16W,5% ,0402,SMT 271061473501 RES;47K ,1/16W,5% ,0402,SMT 271071487811 RES;48.7 ,1/16W,1% ,0603,SMT 271071487011 RES;487 ,1/16W,1% ,0603,SMT,MUS 271061499012 RES;49.9 ,1/16W,1% ,0402,SMT 271061499411 RES;499K ,1/16W,1% ,0402,SMT 271071499311 RES;499K ,1/16W,1% ,0603,SMT 271061562102 RES;5.6K ,1/16W, 1%,0402,SMT 271061510303 RES;51, 1/16W, 5%,0402,SMT 271061549011 RES;54.9 ,1/16W,1% ,0402,SMT 271061560501 RES;56 ,1/16W,5% ,0402,SMT 271061562212 RES;56.2K,1/16W,1%,0402,SMT 271071563101 RES;56K ,1/16W,1% ,0603,SMT 271061576411 RES;576K ,1/16W,1% ,0402,SMT 271061590411 RES;590K,1/16W,1%,0402,SMT 271061619211 RES;6.19K,1/16W,1% ,0402,SMT 271061634211 RES;6.34K,1/16W,1% ,0402,SMT

Price(US)

R10,R1081,R1132,R1154,R1200,R PR87,PR88 PR20,R1148 R832 R1 PR118,PR60,R1187,R1189,R1205, R1085,R553,R554,R558 R4 PR702,R373 R442,R443,R702,R708,R929,R940 R900 R883 R1082,R1086,R1087,R1090,R209, PR43,PR716 R17 R1099,R542 R224,R228,R238,R243,R289 R1141,R1142,R1143,R1144,R142, R198,R264,R269,R273,R856,R936 PR15 R6 PR28 PR65 PR81 R1145

138

8050 N/B Maintenance

9. Spare Part List(10)

Part Number Description

271061649212 RES;6.49K,1/16W,1% ,0402,SMT 271061682501 RES;6.8K ,1/16W,5% ,0402,SMT 271061604011 RES;60.4 ,1/16W,1% ,0402,SMT 271002604011 RES;604 ,1/10W,1% ,0805,SMT 271061634214 RES;63.4K,1/16W,1%,0402,SMT 271071681813 RES;68.1,1/16W,1%,0603,SMT 271061681501 RES;680 ,1/16W,5% ,0402,SMT 271071684101 RES;680K ,1/16W,1% ,0603,SMT 271061752102 RES;7.5K,1/16W,1%,0402,SMT 271061750501 RES;75 ,1/16W,5% ,0402,SMT 271061753101 RES;75,1/16W,1%,0402,SMT 271071753301 RES;75K ,1/16W,5% ,0603,SMT 271071822102 RES;8.2K ,1/16W,1% ,0603,SMT 271061822501 RES;8.2K ,1/16W,5% ,0402,SMT 271061806311 RES;80.6K,1/16W,1% ,0402,SMT 451680900151 ROM ME KIT;8050 271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT 271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT 271621103302 RP;10K*8 ,10P,1/32W,5% ,1206,SMT 271611220301 RP;22*4 ,8P ,1/16W,5% ,0612,SMT 271621472302 RP;4.7K*8,10P,1/32W,5% ,1206,SMT 271571560302 RP;56*8 ,16P,1/16W,5% ,1606,SMT 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT 345677300001 RUBBER;SILICONE RUBBER,T =1.5mm,D 371102010252 SCREW;M2L2.5,K-HEAD(+),NIB/NLK RP26,RP27 RP719 RP46 RP45 RP44 RP29,RP30,RP31,RP32,RP33,RP3 RP2

Price(US)

PR721 R537,R538,R546,R547 R923,R924 R945,R946 PR42 R903 R214 R5 PR84 R152,R271,R277,R46,R930 R144,R145,R334,R340,R784 R8 R14B R1004,R1005,R1074,R1119,R1228 PR63,PR66

Part Number Description

371102010252 SCREW;M2L2.5,K-HEAD(+),NIB/NLK 340680900008 SHIELDING ASSY;COVER,8050 340680900026 SHIELDING ASSY;HDD,8050 333050000117 SHRINK TUBE;UL,600V,105'C,ID2.5* 342677000014 SMT NUT;A40M20-50,EMI STOP,LYNX 342680900001 SMT NUT;A40M20-62,EMI STOP,8050 361400003021 SOLDER CREAM;NOCLEAN,P4020870980 361200003047 SOLDER PASTE;NO CLEAN,RMA,CK3000 365350000003 SOLDER WIRE;0.8MM,SN43/PB43/BI14 600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC 600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC 600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC 341680900001 SPC SCREW;#4-1/4,8050 370102010502 SPC-SCREW;M2 L5,NIB,K-HD,t0.8,NL 370102611601 SPC-SCREW;M2.6*L16,NIB,K-HD 370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK 370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK 370102010201 SPC-SCREW;M2L2,NIW,K-HD,t=0.8,NL 370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK 370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK 370102010303 SPC-SCREW;M2L3,NIW,K-HD(+),NYLOK 370102010409 SPC-SCREW;M2L4,K-HD(t0.3),NIB/NL 370102010409 SPC-SCREW;M2L4,K-HD(t0.3),NIB/NL

Price(US)

MTG701,MTG702 MTG703,MTG704

139

8050 N/B Maintenance

9. Spare Part List(11)

Part Number Description

370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3 340680900002 SPEAKER ASSY;L,8050 340680900003 SPEAKER ASSY;R,8050 340680900001 SPEAKER ASSY;WOOFER,8050 226600030332 SPONGE;320*290*10,CAIMAN,PWR 346677000016 SPONGE;RTC,LYNX 341677000002 SPRING;SCREW,HEAT SINK,LYNX 523408610018 SUPER COMBO DRIVE;UJ-815B,PANASO 297140200003 SW;COVER SWITCH,0.1A,30V,4P,T -ME 297004010001 SW;PUSH BUTTOM,5P,SPST,12VDC,50m 225600000061 TAPE;ADHENSIVE,DOUBLE-FACE,W20,U 225600000054 TAPE;INSULATING,POLYEST ER FILM,1 310111103029 THERMIST OR;10K,1%,BN35-3H103F,18 442680900051 TOUCHPAD MODULE;SYNAPTICS,TM42PU 288227002006 TRANS;2N7002LT1,N-CHANNEL FET ,ES 288204406001 TRANS;AO4406,N-MOS,.0165OHM,SO8 288204407001 TRANS;AO4407,P-MOS,.01OHM,SO8,SM 288204409001 TRANS;AO4409,P-MOSFET,SO-8P,MSL, 288204410010 TRANS;AO4410,N-MOSFET,ID=18A,0.0 288204900001 TRANS;AO4900,DUAL N-MOSFET WITH 288204914001 TRANS;AO4914,DUAL N-MOSFET ,WITH 288200144008 TRANS;DTA144EKA,PNP,SMT 288204435003 TRANS;FDS4435,P-MOSFET ,35mOHM,SO 288200301001 TRANS;FDV301N,N-CHANNEL,SOT23 288202222019 TRANS;MMBT2222ALT 1,NPN,TO236AB,O PQ1,PQ12,PQ14,PQ16,PQ17,PQ1 PU10,PU9 PQ701,PQ704,PQ707 Q3,Q5 PU11,PU12,PU13 PU4,PU6,PU702,PU705,PU707,PU PU701 Q1 Q9,U704,U707 Q42 PQ15 RT1 SW1 SW2,SW4,SW5

Price(US)

Part Number Description

288203904022 TRANS;MMBT3904L,NPN,Tr35NS,TO236 288221371002 TRANS;MUN2137T1,PNP,SMT,ON 288202215001 TRANS;MUN2215T1,N-MOSFET ,SC59,SM 288202237002 TRANS;MUN2237T1,NPN,SOT -23,SMT ,O 288202240001 TRANS;MUN2240T1,NPN,SOT -23,ON 288202301001 TRANS;SI2301DS,P-MOSFET,SOT -23 288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO 273001050069 TRANSFORMER;10/100 BASE,NS0013,S 332110020165 WIRE ;#20AWG,UL1007,L=160mm,RED, 332110020173 WIRE ;#20AWG,UL1007,L=256mm,BLAC 332110026151 WIRE ;#26AWG,UL1007,L=142mm,YELL 332110026150 WIRE ;#26AWG,UL1007,L=208mm,BLUE 422677000008 WIRE ASSY;BATT T O MB,FOR LYNX,MO 340680900028 WIRE ASSY;INVERTER,8050 422674300071 WIRE ASSY;MDC,E-NOTE 422680900003 WIRE CABLE;SAM LT N154X1,8050 340680900027 WLEN ASSY;CABLE,8050 273001050160 XFMR;CI8.5,25T/2150T,300mH,ONLY 273001050039 XSFORMER;10/100 BASE,LF-H80P,SMT 274011431414 XT AL;14.318MHZ,32PF,50PPM,8*4.5, 274012457406 XT AL;24.576MHZ,16PF,50PPM,8*4.5, 274012500415 XT AL;25MHZ,20PF,30PPM,8.0*4.5,SM 274013276103 XT AL;32.768KHZ,20PPM,12.5PF,CM20 274010800405 XT AL;8Mhz,30PPM,16PF,8*4.5,2P,SM

Price(US)

PQ10,PQ9,Q20,Q708,Q718 PQ13,Q711 Q719,Q720 PQ24,Q47 Q12,Q23,Q26,Q27,Q29,Q31,Q32,Q Q13,Q14,Q24,Q43,Q48,Q51 U7

CN1 CN4 CN3 CN2 J710

T1 U717 X701,X703 X707 X706 X704 X1

P/N: 526268090006

140

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

REVISION PCI DEVICE INTERRUPT PCI_INTE# PCI_INTB# / PCI_INTC# PCI_INTG# REQ/GNT PCI_REQ3# / PCI_GNT3# PCI_REQ0# / PCI_GNT0# PCI_REQ1# / PCI_GNT1# PCI_REQ2# / PCI_GNT2# IDSEL AD18 R0A AD20 R00

TAPEOUT DAY 2003/8/26 2003/10/09 1.

HISTORY

8050 R01

PROJECT CODE- G095 PRODUCT CODE- 6809

D

LAN CARDBUS / CARDREADER IEEE1394

CHANGE CARDBUS/CARD READER CONTROLLER FROM R5C592 TO CB710 USE IEEE1394 CONTROLLER VT6307 INSTEAD OF R5C592 ADD SPDIF FUNCTION CHANGE CARDBUS CONNENTOR PLACEMENT FORM COMPONENT SIDE TO SOLDER SIDE CHANGE MDC AND MINIPCI CONNECTORS PLACEMENT FROM SOLDER SIDE TO COMPONENT SIDE CHANGE LVDS ROUTING FAR AWAY POWER SWITCHING SIGNALS CHANGE TV CONNECTOR CHANGE BATTERY CONNECTOR EXCHANGE TV CONNECTOR PIN 6 AND PIN 7 ADD SPREAD SPECTRUM CIRCUIT BUT RESERVE ADD POWER CONSUMPTION SAVING CIRCUIT BUT RESERVE

PCB P/N 316680900001 ASSY P/N 411680900011

2. AD21 3. AD17 4.

C

PAGE 1 TITLE PAGE 2 CPU- BANIAS(1/2) PAGE 3 CPU-BANIAS(2/2) PAGE 4 NB-MONTARA-GME(1/2) PAGE 5 NB-MONTARA-GME(2/2) PAGE 6 DDR-DIMM PAGE 7 VGA-M10(1/4) PAGE 8 VGA-M10(2/4) PAGE 9 VGA-M10 (3/4) PAGE10 VGA-M10(4/4) PAGE11 CLOCK SYNTHERIZER/TV ENCODER PAGE12 CRT/LCD PAGE13 SOUTHBRIDGE-ICH4-M(1/2) PAGE14 SOUTHBRIDGE-ICH4-M(2/2) PAGE15 CDROM/HDD/USB CONNECTOR PAGE16 LAN RTL8100CL PAGE17 R5C811/841 PAGE18 IEEE1394 PAGE19 MINI-PCI PAGE20 AUDIO CODEC(ALC655) PAGE21 AUDIO AMPLIFIER/SUBWOOFER PAGE22 KBC(W83L950D) PAGE23 TOUCHP_PAD/FWH/LED PAGE24 PULL HIGH PAGE25 PERPHERIAL PAGE26 +2.5VS_DDR_P/+1.25V_DDR_P PAGE27 +3VS_P/+5VS_P PAGE28 +1.5V_P/+1.05V_P PAGE29 +1.8V_P/1.35V_P PAGE30 +1.2V/1.0V_M10 PAGE31 CPUCORE PAGE32 ADAPTER/VMAIN PAGE33 CHARGER/DISCHARGER

MINIPCI

PCI_INTD#

D

5.

EMI

TP42 TOUCHPAD_METAL10 TP43 TOUCHPAD_METAL10 TP44 TOUCHPAD_METAL10 TP45 TP46 TP3 TOUCHPAD_METAL10 TOUCHPAD_METAL10

6.

R0B

TOUCHPAD_METAL5

2003/11/07

1. 2.

1

1

1

1

1

R01

2003/12/16

1. 2.

GND TP47 TOUCHPAD_METAL10

GND TP48 TOUCHPAD_METAL10

GND TP50 TOUCHPAD_METAL10

GND TP51

GND TP52

GND

1

3.

TP4 TOUCHPAD_METAL5

TOUCHPAD_METAL10 TOUCHPAD_METAL10

1

1

1

1

1

GND

GND

GND

GND

GND

GND

1

C

MDC

342677000014 MTG702 MTG/ID1.2/OD4.6 342677000014 MTG701 MTG/ID1.2/OD4.6

CARDREADER

MTG704 MTG/ID1.2/OD4.6 MTG703 MTG/ID1.2/OD4.6 +3V JS702 1 2 GND 50V 1 +/-20% 1 C1007 +5V

EC

C1008 50V 1 +/-20% GND 2 0402 1000P +1.35V TP722

ESD

TP723 TOUCHPAD_METAL10

2 0402 1000P C1006 +2.5V_M10

1

1

SHORT-SMT4 GND GND +3V 50V 1 +/-20% AGND C357 +5V 50V 1 +/-20% GND

1

TOUCHPAD_METAL10

1

2 0402 1000P GND_USB 1394_GND

2 0402 1000P

MTG1 ID3.0/OD11 MTG118NRD433_3016B 3 2 1

MTG2 ID3.0/OD11 MTG118-RD433-N-30X16 3 2 1

MTG4 ID3.0/OD11 MTG118-RD433-N-30X16 3 2 1

MTG7 ID3.0/OD11 MTG118NRD433_3016A 3 2 1

MTG8 ID3.0/OD11 MTG118NRD433_3016A 3 2 1

8050N

TP58 RD080_051/NA TP59 RD080_051/NA

B

B

4 5 6 7 8 9 10 11

16 15 14 13 12

4 5 6 7 8 9 10 11

16 15 14 13 12

4 5 6 7 8 9 10 11

16 15 14 13 12

4 5 6 7 8 9 10 11

16 15 14 13 12

4 5 6 7 8 9 10 11

16 15 14 13 12

1

1 GND GND FD2 FIDUCIAL-MARK 1 FD4 FIDUCIAL-MARK

CHAGND

GND

GND

GND_45

GND

CPU

MTG9 ID3.0/OD11 MTG118-RD433-N-30X16 3 2 1 MTG11 ID3.0/OD11 MTG118NRD433_3016A 3 2 1 MTG13 ID3.0/OD11 MTG118-RD433-N-30X16 3 2 1 MTG14 ID3.0/OD11 MTG118NRD433_3016B 3 2 1 MTG24 ID5.3/OD7.5 MTG27 ID5.3/OD7.5 MTG28 ID5.3/OD7.5 MTG12 ID5.3/OD7.5 MTG32 ID5.3/OD7.5

4 5 6 7 8 9 10 11

16 15 14 13 12

4 5 6 7 8 9 10 11

16 15 14 13 12

4 5 6 7 8 9 10 11

16 15 14 13 12

4 5 6 7 8 9 10 11

16 15 14 13 12

1

1

1

1

1

FD1 FIDUCIAL-MARK FD3 FIDUCIAL-MARK

GND

GND

GND

GND

GND 1 1 1 1 FD701 FIDUCIAL-MARK 1

GND

GND_45

GND

CAGND

MTG10 ID2.8/OD11

MTG22 ID2.8/OD11

MTG5 ID3.0/OD9.0

MTG31 ID3.0/OD8.0/CP7.5X9.5 FD703 FIDUCIAL-MARK FD704 FIDUCIAL-MARK FD702 FIDUCIAL-MARK

MTG6 ID3.0/OD9.0 MTG118-RD354-N-30X12 3 2 1

MTG3 ID3.0/OD9.0 MTG118-RD354-N-30X12 3 2 1

MTG15 ID3.0/OD9.0 MTG118-RD354-N-30X12 3 2 1

1

1

1

1

1

1

GND 12 11 10

GND

GND

GND

A

A

4 5 6 7 8 9

12 11 10

4 5 6 7 8 9

12 11 10

4 5 6 7 8 9

DRAWN DESIGN CHECK ISSUES

GND GND 1394_GND Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

1

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 1 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

VCC : PROCESSOR CORE POWER SUPPLY. VCCA : ISOLATE POWER FOR INTERNAL PLL. VCCP : PROCESSOR I/O POWER SUPPLY. VCCQ : QUIET POWER SUPPLY FOR ON DIE COMP CKT.

4 HA#[3..31] HA#[3..31] U713A HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 4 4 4 4 4 4 4 +VCCP 4 4 4 4 4 HRS#[0..2] 13 14 4 13 31 PM_PS R292 13 13 13 HADS# HADSTB#0 HADSTB#1 HBR0# HBPRI# HBNR# HLOCK# R264 56 1 HHIT# HHITM# HDEFER# HTRDY# HRS#[0..2] HBR0# P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 R2 P3 T2 P1 T1 N2 U3 AE5 N4 J3 L1 J2 A4 K3 K4 L4 M3 H1 K1 L2 C2 D3 C19 A7 A6 E1 A3 B4 E4 B17 C6 B7 D1 D4 B5 B11 A16 A15 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# REQ0# REQ1# REQ2# REQ3# REQ4# ADS# ADSTB0# ADSTB1# BR0# BPRI# BNR# LOCK# IERR# HIT# HITM# DEFER# TRDY# RS0# RS1# RS2# A20M# FERR# DPWR# DBR# SLP# PSI# IGNNE# SMI# PWRGOOD PROCHOT# STPCLK# DPSLP# LINT0 LINT1 INIT# RESET# ITP_CLK0 ITP_CLK1 BANIAS BGA479_SKT3 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# DBSY# DRDY# THERMDA THERMDC THERMTRIP# A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 H23 G25 L23 M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26 C23 K24 W25 AE24 C22 L24 W24 AE25 M2 H2 B18 A18 C17 CPU_THERMDA CPU_THERMDC HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 HDSTBN#[0..3] HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#[0..3] HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HDBSY# HDRDY# 4 4 HDSTBN#[0..3] 4 HD#[0..63] HD#[0..63] 4 U713B +VCCP 1 11 HCLK_CPU 11 HCLK_CPU# HBPM#0 HBPM#1 R242 0 R237 0 +VCCP 1 B15 B14 C8 B8 2 0402 A9 2 0402 C9 HTCLK HTDI HTDO HTMS HTRST# HPREQ# HPRDY# A13 C12 A12 C11 B13 B10 A10 AD26 E26 G1 AC1 P25 P26 AB2 AB1 AF7 BCLK0 BCLK1 BPM0# BPM1# BPM2# BPM3# TCK TDI TDO TMS TRST# PREQ# PRDY# GTLREF0 GTLREF1 GTLREF2 GTLREF3 COMP0 COMP1 COMP2 COMP3 RSVD_0 RSVD_2 RSVD_3 TEST1 TEST2 TEST3 DINV0# DINV1# DINV2# DINV3# VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 D6 D8 D18 D20 D22 E5 E7 E9 E17 E19 E21 F6 F8 F18 F20 F22 G5 G21 H6 H22 J5 J21 K22 U5 V6 V22 W5 W21 Y6 Y22 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC9 AC11 AC13 AC15 AC17 AC19 AD8 AD10 AD12 AD14 AD16 AD18 AE9 +VCC_CORE

CPU-BANIAS (1/2)

+VCC_CORE 1

D

R289 51 0402 5% 2 HBR0# +VCCP 1

R198 56 0402 5% HPROCHOT# 2

1 1

D

R141 1K 0402 1% 2

R301 330 0402 5% 2 HPWRGD

Close to CPU as possible. < 0.5"

1 1 1 C165 220P 0402 10% 50V C160 1U 0402 +80-20% 10V 2 R134 2K 0402 1%

HCOMP0 HCOMP1 HCOMP2 HCOMP3

2

4

HREQ#[0..4]

HREQ#[0..4]

GND

HCOMP1 & HCOMP3 should be route with 5 mil width

CPU_TEST1 CPU_TEST2 CPU_TEST3 4 HDINV#[0..3] HDINV#[0..3] HDINV#0 HDINV#1 HDINV#2 HDINV#3

2

C14 C3 C5 F23 C16 D25 J26 T24 AD20

C

C

2 0402 5%

+VCC_CORE AE11 AE13 AE15 AE17 AE19 AF8 AF10 AF12 AF14 AF16 AF18 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 BANIAS BGA479_SKT3

HRS#0 HRS#1 HRS#2 HA20M# HDBR# HSLP# HPSI# HIGNNE# HSMI# HPWRGD HPROCHOT# HSTPCLK# HDPSLP# HINTR HNMI HINIT#

HA20M# HFERR# HDPWR# HSLP# 1 2 0/NA5% HIGNNE# HSMI# HPWRGD

22 HPROCHOT#

HDSTBP#[0..3] 4

13 4,13 13 13 13,23 4

HSTPCLK# HDPSLP# HINTR HNMI HINIT# HCPURST#

CPU_THERMDA 22 CPU_THERMDC 22 CPU_THRMTRIP_OUT# 14 +3V +VCC_CORE +VCCP HDBR# 1 R246 10K/NA R229 51/NA 0402 5% 2 2 0402 5%

B

B

11 CLK_ITP_CPU 11 CLK_ITP_CPU#

HCOMP0 & HCOMP2 should be route with 18 mil width

1 R133 27.4 1 R142 54.9 1 R291 27.4 1 R300 54.9 GND 2 0402 2 0402 2 0402 2 0402 HCOMP0 1% HCOMP1 1% HCOMP2 1% HCOMP3 1%

1

1

1

1

1

1

1

R224 51 0402 5% HPREQ# HPRDY# HBPM#1 HBPM#0 HTDO HTMS HTDI 4 HCPURST# HTRST# HTCLK 1 2 2

R228 51 0402 5% 2

R238 51 0402 5% 2

R243 51 0402 5%

R219 51/NA 0402 5% 2 2

R225 39 0402 1% 2

R220 150 0402 1%

1

+VCCP

HA20M#

R213 27.4 0402 1%

R214 680 0402 5% 2

1 R294 200/NA 1 R265 200/NA HINTR 1 R293 200/NA HNMI 1 R302 200/NA HSMI# 1 R268 200/NA HSTPCLK# 1 R249 200/NA HDPSLP# 1 R247 200/NA HSLP# 1 R248 200/NA HINIT# 1 R256 200/NA HIGNNE#

2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402

5% 5% 5% 5% 5% 5% 5% GND 5%

1 R255 1K/NA 1 R143 1K/NA 1 R204 1K/NA

2 CPU_TEST1 0402 5% 2 CPU_TEST2 0402 5% 2 CPU_TEST3 0402 5%

2

1

Close to CPU as possible.

5%

GND

GND

Don't overlay by CHOKE or vibrating signals.

PLACEMENT MAX. 3" FROM CPU.

Place close to CPU socket within 2".

A A

+1.8V

+1.5V 1 2 1 1 1 1 1

+VCCA

1

1

R124 0/NA 1 R123 0

0805 2

C322 2.2U 0603 +/-10%

C323 2.2U 0603 +/-10%

C151 2.2U 0603 +/-10%

C161 2.2U 0603 +/-10%

C162 0.1U 0402 10%

C163 0.1U 0402 10%

C316 0.1U 0402 10%

1 C317 0.1U 0402 10% Title 2

2

2

2

2

2

2

0805 GND

2

1.8V, 0.6A, 10uF and 10nF each VCCA pin. 1.5V for future support.

8050 MOTHER B/D

Size C Date: Document Number PCB 316680900001/ASSY 411680900011 Sheet 2 of 34

1

Rev R01

Monday, December 29, 2003

5

4

3

2

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

CPU-BANIAS (2/2)

+VCCP

1.05V, 2.4A

1 1 1 1 1 1 C189 10U 0805 6.3V C203 10U 0805 6.3V 2

U713C +VCCP

1 C256 10U 0805 6.3V

2

2

2

2

2

D

+VCCQ

D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L5 L21 M6 M22 N5 N21 P6 P22 R5 R21 T6 T22 U21 P23 W4

VCCP_0 VCCP_1 VCCP_2 VCCP_3 VCCP_4 VCCP_5 VCCP_6 VCCP_7 VCCP_8 VCCP_9 VCCP_10 VCCP_11 VCCP_12 VCCP_13 VCCP_14 VCCP_15 VCCP_16 VCCP_17 VCCP_18 VCCP_19 VCCP_20 VCCP_21 VCCP_22 VCCP_23 VCCP_24 VCCQ0 VCCQ1 VCCA0 VCCA1 VCCA2 VCCA3 VID0 VID1 VID2 VID3 VID4 VID5

+VCCA

F26 B1 N1 AC26 E2 F2 F3 G3 G4 H4

VID0 VID1 VID2 VID3 VID4 31 VID[0..4] VID[0..4] CPUVID5

C

1

1

1

1

GND

BANIAS BGA479_SKT3

GND

1

1

1

1

2

2

C264 10U 0805 6.3V

C198 10U 0805 6.3V

C249 10U 0805 6.3V

C240 10U 0805 6.3V

1

R299 R298

RP28 1 8 VID0 4.7K*4/NA 7 VID1 2 1206 3 6 VID2 4 5 VID3 1 4.7K/NA 2 0402 VID4 1 4.7K/NA 2 0402 VID5

C1004 + 220U/NA + 7343 4V

C1005 220U/NA 7343 4V

C155 10U 0805 6.3V

C156 10U 0805 6.3V

C157 10U 0805 6.3V

C158 10U 0805 6.3V

1

1 R885 54.9 1 R899 54.9

2 0402 2 0402

AE7 1% AF6 1%

VCCSENSE VSSENSE

VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191

AB19 AB21 AB23 AB26 AC2 AC5 AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24 AD1 AD4 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25 AE3 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26 AF2 AF5 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24

GND

0.844V ~ 1.356V, 32A

+VCC_CORE

2

(1.05V)

U713D

+5V

VID 5 0 0 0 0 0 0 0

B

VID 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC-Core 1.708 1.692 1.676 1.660 1.644 1.628 1.612 1.596 1.580 1.564 1.548 1.532 1.516 1.500 1.484 1.468 1.452 1.436 1.420 1.404 1.388 1.372 1.356 1.340 1.324 1.308 1.292 1.276 1.260 1.244 1.228 1.212 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCC-Core 1.196 1.180 1.164 1.148 1.132 1.116 1.100 1.084

1

1

1

1

1

1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C186 0.1U 0402 10% 16V

C195 0.1U 0402 10% 16V

C248 0.1U 0402 10% 16V

C235 0.1U 0402 10% 16V

C222 0.1U 0402 10% 16V

C204 0.1U 0402 10% 16V

1

4

3

2

A2 A5 A8 A11 A14 A17 A20 A23 A26 B3 B6 B9 B12 B16 B19 B22 B25 C1 C4 C7 C10 C13 C15 C18 C21 C24 D2 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6

VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 BANIAS BGA479_SKT3

VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145

J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23 T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24 AA1 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17

C257 10U 0805 6.3V

C220 10U 0805 6.3V

C187 10U 0805 6.3V

C188 10U 0805 6.3V

D

1

1

1

1

1

1

C226 10U 0805 6.3V

C209 10U 0805 6.3V

C193 10U 0805 6.3V

C199 10U 0805 6.3V

C214 10U 0805 6.3V

C230 10U 0805 6.3V

1 C241 10U 0805 6.3V C279 10U 0805 6.3V 1 C296 10U 0805 6.3V C177 10U 0805 6.3V 1 C183 10U 0805 6.3V 2 2 2

2

2

2

2

2

1

1

1

C180 10U 0805 6.3V

C267 10U 0805 6.3V

C250 10U 0805 6.3V

1

C190 10U 0805 6.3V

2

2

2

GND +VCC_CORE 1 1

C320 10U 0805 6.3V

C321 10U 0805 6.3V

1

1

2

1

C192 10U 0805 6.3V

C179 10U 0805 6.3V

C270 10U 0805 6.3V

2

2

2

2

2

1

1

1

1

1

C312 10U 0805 6.3V

C807 10U 0805 6.3V

C168 10U 0805 6.3V

C173 10U 0805 6.3V

C175 10U 0805 6.3V

2

2

2

2

2

GND +VCC_CORE

+VCC_CORE

2

1

2

1

2

C

C831 10U 0805 6.3V

1

1

2

2

2

2

2 2

C254 10U 0805 6.3V

2

2

2

GND GND +VCC_CORE

2

C185 0.1U 0402 10% 16V

2

2

2

2

2

2

+VCC_CORE

GND

1

1

1

1

1

1

GND 2

C268 0.1U 0402 10% 16V

C251 0.1U 0402 10% 16V

C280 0.1U 0402 10% 16V

C191 0.1U 0402 10% 16V

C178 0.1U 0402 10% 16V

C236 0.1U 0402 10% 16V

1 C200 0.1U 0402 10% 16V

B

2

2

2

2

2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

+VCCP

GND

1.068

1 1 1 1 1 1 1 1 R193 1 0 Q16 2 2 C319 0.1U 0402 10% 16V C318 0.1U 0402 10% 16V C181 0.1U 0402 10% 16V C266 0.1U 0402 10% 16V C259 0.1U 0402 10% 16V C182 0.1U 0402 10% 16V C242 0.1U 0402 10% 16V C194 0.1U 0402 10% 16V 1 C196 0.1U 0402 10% 16V GND 1 C231 10U 0805 6.3V C258 10U 0805 6.3V GND GND 2 2

1.052 1.036 1.020

CPUVID5 S 2N7002/NA D VID5 D S VID5 31

2

2

2

2

2

2

1.004

G 2

0.988 0.972 0.956 0.940 0.924

D 1 +1.5V 2 13,24 B/CB#

R400 10K/NA 0402 5% +VCCP +VCCP 1 120Z/100M 2012 L41 2 1 1 C237 10U 0805 6.3V C201 0.1U 0402 10% 16V 1 C265 0.1U 0402 10% 16V +VCCQ 1 C768 + 150U 7343 6.3V 1

R401 1K/NA 0402 5% D14

Q28 SI2301DS/NA

GND D S 3 S D

0.908 0.892 0.876 0.860 0.844

11,13,31 STOP_CPU# G

1

2

1

2

2

D Q45 S 2N7002/NA S

BAT54/NA

GND

0.828 0.812 0.796 0.780 0.764 0.748 0.732 0.716 0.700

Title

1 B/CB# GPIO16 Banias CPU

G

0 Celeron Banias CPU

A

A

0 0 0 0 0 0

power on default = 1

POWER CONSUMPTION SAVING CIRCUIT

8050 MOTHER B/D

Size C Date: Document Number PCB 316680900001/ASSY 411680900011 Sheet 3 of 34

1

2

2

2

2

2

G Rev R01 Monday, December 29, 2003

5

4

3

2

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

NB-MONTARA-GME(1/2)

U714A 2 HA#[3..31] HA#[3..31] HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HREQ#[0..4] HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 2 HADSTB#0 2 HADSTB#1 HXRCOMP HXSWING HYRCOMP HYSWING

C

AGPBUS

AGP_AD[0..31] 855_DVOBHSYNC 855_DVOBVSYNC 855_DVOBD1 855_DVOBD0 855_DVOBD3 855_DVOBD2 855_DVOBD5 855_DVOBD4 855_DVOBD6 855_DVOBD9 855_DVOBD8 855_DVOBD11 855_DVOBD10 855_DVOBCCLKINT 855_DVOBFLDSTL 855_MDDCCDATA 855_DVOCVSYNC 855_DVOCHSYNC 855_DVOCBLANK# 855_DVOCD0 855_DVOCD1 855_DVOCD2 855_DVOCD3 855_DVOCD4 855_DVOCD7 855_DVOCD6 855_DVOCD9 855_DVOCD8 855_DVOCD11 855_DVOCD10 855_DVOBCINTR# 855_DVOCFLDSTL AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 AGP_AD[0..31] 7,24

U714B P23 T25 T28 R27 U23 U24 R24 U28 V28 U27 T27 V27 U25 V26 Y24 V25 V23 W25 Y25 AA27 W24 W23 W27 Y27 AA28 W28 AB27 Y26 AB28 R28 P25 R23 R25 T23 T26 AA26 B20 B18 H28 K28 K27 D26 E21 E18 J28 C27 E22 D18 J25 E25 B25 G19 L28 M25 N24 M28 N28 N27 P27 M23 N25 P28 M26 N23 P26 M27 F15 J11 HA[3]# HA[4]# HA[5]# HA[6]# HA[7]# HA[8]# HA[9]# HA[10]# HA[11]# HA[12]# HA[13]# HA[14]# HA[15]# HA[16]# HA[17]# HA[18]# HA[19]# HA[20]# HA[21]# HA[22]# HA[23]# HA[24]# HA[25]# HA[26]# HA[27]# HA[28]# HA[29]# HA[30]# HA[31]# HREQ[0]# HREQ[1]# HREQ[2]# HREQ[3]# HREQ[4]# HADSTB[0]# HADSTB[1]# HXRCOMP HXSWING HYRCOMP HYSWING HDSTBP[0]# HDSTBP[1]# HDSTBP[2]# HDSTBP[3]# HDSTBN[0]# HDSTBN[1]# HDSTBN[2]# HDSTBN[3]# DINV[0]# DINV[1]# DINV[2]# DINV[3]# ADS# HTRDY# DRDY# DEFER# HITM# HIT# HLOCK# BREQ0# BNR# BPRI# DBSY# RS[0]# RS[1]# RS[2]# CPURST# PWROK 855GM/GME BGA707_25 HD[0]# HD[1]# HD[2]# HD[3]# HD[4]# HD[5]# HD[6]# HD[7]# HD[8]# HD[9]# HD[10]# HD[11]# HD[12]# HD[13]# HD[14]# HD[15]# HD[16]# HD[17]# HD[18]# HD[19]# HD[20]# HD[21]# HD[22]# HD[23]# HD24]# HD[25]# HD[26]# HD[27]# HD[28]# HD[29]# HD[30]# HD[31]# HD[32]# HD[33]# HD[34]# HD[35]# HD[36]# HD[37]# HD[38]# HD[39]# HD[40]# HD[41]# HD[42]# HD[43]# HD[44]# HD[45]# HD[46]# HD[47]# HD[48]# HD[49]# HD[50]# HD[51]# HD[52]# HD[53]# HD[54]# HD[55]# HD[56]# HD[57]# HD[58]# HD[59]# HD[60]# HD[61]# HD[62]# HD[63]# HDVREF[0] HDVREF[1] HDVREF[2] K22 H27 K25 L24 J27 G28 L27 L23 L25 J24 H25 K23 G27 K26 J23 H26 F25 F26 B27 H23 E27 G25 F28 D27 G24 C28 B26 G22 C26 E26 G23 B28 B21 G21 C24 C23 D22 C25 E24 D24 G20 E23 B22 B23 F23 F21 C20 C21 G18 E19 E20 G17 D20 F19 C19 C17 F17 B19 G16 E16 C16 E17 D16 C18 K21 J21 J17 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63

HD#[0..63]

HD#[0..63]

2

CHECK

+1.5V 1

D

855_ADDID0 855_ADDID1 855_ADDID2 855_ADDID3 855_ADDID4 855_ADDID5 855_ADDID6 855_ADDID7 7,13,24 AGPBUSY# 11 HCLK_MCH 11 HCLK_MCH# 2,13 HDPSLP# 2 855_DPMS 2 HDPWR# 0402 11 48M_DREFCLK

E5 F5 E3 E2 G5 F4 G6 F6

ADDID[0] ADDID[1] ADDID[2] ADDID[3] ADDID[4] ADDID[5] ADDID[6] ADDID[7] AGPBUSY# BCLK BCLK# DPMS DPSLP# DPWR# DREFCLK IYAM[0] IYAM[1] IYAM[2] IYAM[3] IYAP[0] IYAP[1] IYAP[2] IYAP[3] IYBM[0] IYBM[1] IYBM[2] IYBM[3] IYBP[0] IYBP[1] IYBP[2] IYBP[3] ICLKAM ICLKAP ICLKBM ICLKBP EXTTS_0 GCLKIN GVREF

DVOBCLK DVOBCLK# DVOBD[0] DVOBD[1] DVOBD[2] DVOBD[3] DVOBD[4] DVOBD[5] DVOBD[6] DVOBD[7] DVOBD[8] DVOBD[9] DVOBD[10] DVOBD[11] DVOBCCLKINT DVOBCINTR# DVOBFLDSTL DVOBBLANK# DVOBHSYNC DVOBVSYNC DVOCCLK DVOCCLK# DVOCD[0] DVOCD[1] DVOCD[2] DVOCD[3] DVOCD[4] DVOCD[5] DVOCD[6] DVOCD[7] DVOCD[8] DVOCD[9] DVOCD[10] DVOCD[11] DVODETECT DVORCOMP DVOCFLDSTL DVOCBLANK# DVOCHSYNC DVOCVSYNC LCLKCTLA LCLKCTLB LIBG MDDCCLK MDDCDATA MDVICLK MDVIDATA MI2CCLK MI2CDATA PANELBKLTCTL PANELBKLTEN PANELVDDEN PSWING RCVENIN# RCVENOUT#

P3 P4 R3 R5 R6 R4 P6 P5 N5 P2 N2 N3 M1 M5 M3 G2 M2 L2 T6 T5 J3 J2 K5 K1 K3 K2 J6 J5 H2 H1 H3 H4 H6 G3 L7 D1 H5 L3 K6 L5 H9 C6

855_DVOBCLK 855_DVOBCLK# 855_DVOBD0 855_DVOBD1 855_DVOBD2 855_DVOBD3 855_DVOBD4 855_DVOBD5 855_DVOBD6 855_DVOBD7 855_DVOBD8 855_DVOBD9 855_DVOBD10 855_DVOBD11 855_DVOBCCLKINT 855_DVOBCINTR# 855_DVOBFLDSTL 855_DVOBBLANK# 855_DVOBHSYNC 855_DVOBVSYNC 855_DVOCCLK 855_DVOCCLK# 855_DVOCD0 855_DVOCD1 855_DVOCD2 855_DVOCD3 855_DVOCD4 855_DVOCD5 855_DVOCD6 855_DVOCD7 855_DVOCD8 855_DVOCD9 855_DVOCD10 855_DVOCD11

D 2

R155 1K 0402 5% 1 0 R156 D S Q15 2N7002

F7 AE29 AD29 855_DPMS D5 Y23 AA22 B7 IYAM0 IYAM1 IYAM2 IYAM3 IYAP0 IYAP1 IYAP2 IYAP3 IYBM0 IYBM1 IYBM2 IYBM3 IYBP0 IYBP1 IYBP2 IYBP3 G14 E15 C15 C13 F14 E14 C14 B13 H12 E12 C12 G11 G12 E11 C11 G10

855_DVODETECT 855_MDDCCLK 855_MI2CDATA 855_MDVICLK 855_MI2CCLK 855_MDVIDATA 855_DVOBCLK 855_DVOCCLK 855_DVOBCLK# 855_DVOCCLK# 855_DVOBD7 855_DVOBBLANK# 5,7 GCBE2# 855_DVOCD5 855_ADDID0 855_ADDID1 855_ADDID2 855_ADDID3 855_ADDID4 855_ADDID5 855_ADDID6 855_ADDID7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 GSBSTB# GSBSTB GWBF# GRBF# GST0 GST1 GST2 GGNT# GREQ#

AGP_PAR AGP_STOP# AGP_DEVSEL# AGP_TRDY# AGP_IRDY# AGP_FRAME# AGP_ADSTB0 AGP_ADSTB1 AGP_ADSTB0# AGP_ADSTB1# AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3 AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 AGP_SBSTBS AGP_SBSTBF AGP_WBF# AGP_RBF# AGP_ST0 AGP_ST1 AGP_ST2 AGP_GNT# AGP_REQ#

7 7 7 7 7 7 7 7 7 7 7 7 5,7 7 7 7 7 7 7 7 7 7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7

D

13

SUSCLK

G S

1 R857 2 100K/NA 0402

GND

GND

2 HREQ#[0..4]

TP38 TP26 TP21 TP32 TP31 TP22 TP20 TP36

1 1 1 1 1 1 1 1

WHEN USE INTEGRATE VGA ADD R798 DEL R857 R1104

TP27 TP30 +3V 7 AGP_VREF 11 66M_MCH 11 DVOVREF R835 1 0/NA 0402 5% 14 HUB_HI[0..10] 2

ICLKAM D14 ICLKAP E13 1 ICLKBM E10 1 ICLKBP F10 0402 1 R166 2 D6 10K 5%Y3 DVOVREF F1

855_DVODETECT R832 0402 1 40.2 2 855_DVOCFLDSTL 855_DVOCBLANK# 855_DVOCHSYNC 855_DVOCVSYNC 1

GND

855_MDDCCLK 855_MDDCCDATA 855_MDVICLK 855_MDVIDATA 855_MI2CDATA 855_MI2CCLK

0402 R235 1 0402 R236 1 0402 R227 1 0402 R226 1 0402 1 R1103 0402 1 R216

2 10K 2 10K 2 10K 2 10K

+1.5V +1.5V

C

2 HDSTBP#[0..3]

HDSTBP#[0..3] HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HDSTBN#[0..3] HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDINV#[0..3] HDINV#0 HDINV#1 HDINV#2 HDINV#3 2 2 2 2 2 2 2 2 2 2 2 HADS# HTRDY# HDRDY# HDEFER# HHITM# HHIT# HLOCK# HBR0# HBNR# HBPRI# HDBSY# HRS#[0..2]

HUB_HI[0..10] HUB_HI0 HUB_HI1 HUB_HI2 HUB_HI3 HUB_HI4 HUB_HI5 HUB_HI6 HUB_HI7 HUB_HI8 HUB_HI9 HUB_HI10 U7 U4 U3 V3 W2 W6 V6 W7 T3 V5 V4 W3 V2 HUB_MCH_VREF HUB_RCOMP W1 T2 AD28 E8 HL[0] HL[1] HL[2] HL[3] HL[4] HL[5] HL[6] HL[7] HL[8] HL[9] HL[10] HLSTB HLSTB# HLVREF HLRCOMP RSTIN# REFSET DDCADATA DDCACLK DDCPCLK DDCPDATA RED RED# GEEN GREEN# BLUE BLUE# HSYNC VSYNC DREFSSCLK

2 10K +1.5V 2 10K +1.5V

2

2 HDSTBN#[0..3]

0402 R210 1 0402 R799 1

2 10K/NA +3V 2 10K/NA 2 GND

R1104 100K/NA 0402 5%

A10 R798 1 1.5K 0402 5% P7 T7 N7 M6 K7 N6 G8 F8 A5 U2 AC16 AC15

GND

WHEN USE INTEGRATE VGA DEL R206

R206 855_DVODETECT 1 1K/NA 0402 5% 2 +1.5V

2 HDINV#[0..3]

+VCCP 1

14 HUB_STB 14 HUB_STB# R209 49.9 0402 1%

855_MDDCCLK 855_MDDCCDATA 855_MDVICLK 855_MDVIDATA 855_MI2CCLK 855_MI2CDATA

HDVREF 1 1 1

1

2

13 MCH_PCIRST#

REFSET

R202 1 0402 R203 1 0402 R801 1 0402

2 0/NA 2 0 2 0 R279 2 0/NA

BLADJ ENABKL_NB FPVDEN

12,22 12 12

+1.5V

WHEN USE INTEGRATE VGA ADD R181

R175 1 R177 1 R170 1 R168 1 R184 1 R172 1 R189 1 R182 1 0402 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 2 855_ADDID0 855_ADDID1 855_ADDID2 855_ADDID3 855_ADDID4 855_ADDID5 855_ADDID6 855_ADDID7 330/NA 330/NA 330/NA 330/NA 330/NA 330/NA 330/NA 1K 1 1 1 1 1 1 1 1 R174 R176 R169 R167 R183 R171 R188 R181 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 GND

2 HRS#[0..2]

HRS#0 HRS#1 HRS#2 1 0402 R217 2 0

HAVREF HCCVREF

Y22 Y28

HAVREF HCCVREF

C215 0.1U 0402 +80-20% 50V

C217 0.1U 0402 +80-20% 50V

R208 C216 100 0.1U 0402 0402 +80-20% 1% 50V 2

2

2

2

+3V

855_DDDA 855_DDCK R790 1 10K R800 1 10K

G9 B6 2 0402 B4 2 0402 C5 A7 A8 C8 D8 C9 D9 H10 J9 2 0 B17

MCH_PSWING RCVENIN# 1 0402 RCVENOUT#

+1.5V 855_RED 1 GND NC_0 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 AJ29 AH29 B29 A29 AJ28 A28 AA9 AJ4 AJ2 A2 AH1 B1

2 HCPURST# 12,13,17,25,31 PWROK

8.2K/NA 8.2K/NA 8.2K/NA 8.2K/NA 8.2K/NA 8.2K/NA 8.2K/NA 8.2K/NA R59 1K 0402 5% DVOVREF

Maximum length less than 0.5" from pin to voltage divider.

855_GREEN 855_BLUE

ADD ID : 0x7Fh

2

B

+1.35V R898 1 37.4 0603 1% 2 HUB_RCOMP

1

855_HSYNC 855_VSYNC

RDDP recommend 1K ohm resistor

M10-P CONNECT TO NB

WHEN USE INTEGRATE VGA DEL ALL RESISTOR

IYAM0 IYAP0 IYAM1 IYAP1 IYAM2 IYAP2 IYAM3 IYAP3 R349 1 R350 1 R353 1 R357 1 R1176 1 R1177 1 R1178 1 R1179 1 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 R153 R154 R158 R159 R794 R795 R796 R797 1 1 1 1 1 1 1 1 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 12 12 12 12 12 12 12 12 TXOUT0-_ATI TXOUT0+_ATI TXOUT1-_ATI TXOUT1+_ATI TXOUT2-_ATI TXOUT2+_ATI TXOUT3-_ATI TXOUT3+_ATI 7 7 7 7 7 7 7 7

B

HXRCOMP & HYRCOMP should be route with 18 mil width

Less than 0.5"

+1.35V 1

W/

SSC

12 855_CRT_DDDA 12 855_CRT_DDCK 12 855_CRT_RED 12 855_CRT_GREEN 12 855_CRT_BLUE HUB_MCH_VREF

11 66M_DEFSSCLK

R789 1 0402

CHANGE TO 0402

1

1

1

1

1

1

C810 0.1U 0402 +80-20% 50V GND GND

1 2 R839 27.4

HYRCOMP CHANGE TO 0402

R918 100 0402 1% 2

C844 0.1U 0402 +80-20% 50V

1

DVOVREF 1

CHANGE TO 0402

C843 0.01U/NA 0402 +80-20% 50V

C775 33P/NA 0402 +/-10% 25V

C170 33P/NA 0402 +/-10% 25V

1

1 2 R792 27.4

HXRCOMP

2

C169 33P/NA 0402 +/-10% 25V

R784 75 0402 1% 2

R145 75 0402 1% 2

1

Place near to GMCH.

CHANGE TO 0402 R914 287 0603 1% 1/10W

855_CRT_DDDA R331 1 0 855_CRT_DDCK R1166 1 0 855_CRT_RED 855_CRT_GREEN 855_CRT_BLUE

2 0402 2 0402

855GM/GME GND BGA707_25 855_DDDA 855_DDCK 855_RED R1167 1 0 2 0402 R343 1 0 2 0402 855_GREEN R344 1 0 2 0402 855_BLUE R144 75 0402 1%

R64 1K 0402 5% 2 GND

2

Non SSC

12 855_CRT_HSYNC 12 855_CRT_VSYNC 855_CRT_HSYNC 855_CRT_VSYNC 0402GND R345 1 0 2 855_HSYNC R348 1 0 2 855_VSYNC 0402 GND +1.35V 1

NB CONNECT TO TV ENCORDER

WHEN USE INTEGRATE VGA ADD ALL RESISTOR

R903 68.1 0603 1% 855_DVOCCLK 855_DVOCCLK# 855_DVOBCCLKINT 855_DVOBCINTR# 855_MI2CCLK 855_MI2CDATA 855_DVOCFLDSTL 855_DVOCHSYNC 855_DVOCVSYNC 855_DVOCD0 855_DVOCD1 855_DVOCD2 855_DVOCD3 855_DVOCD4 855_DVOCD5 855_DVOCD6 855_DVOCD7 855_DVOCD8 855_DVOCD9 855_DVOCD10 855_DVOCD11 R114 R128 R147 R117 R162 R113 R150 R125 R157 R146 R111 R112 R126 R127 R148 R129 R149 R130 R115 R131 R116 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 0402 DVOCCLK DVOCCLK# POUT/DET# DVOBCINTR# MI2CCLK MI2CDATA DVOCFLDSTL DVOCHSYNC DVOCVSYNC 11 11 11 11 11 11 11 11 11 DVOCD[0..11] 11 R361 1 0 R363 1 0

TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXOUT3TXOUT3+

2

2

2

2

GND

2

2

2 0402 2 0402 R160 1 0/NA R161 1 0/NA

ICLKAM ICLKAP 2 0402 2 0402 TXCLK-_ATI TXCLK+_ATI 7 7

Maximum length less than 0.5" from pin to voltage divider.

+VCCP (1.05V) 1 +VCCP 1

Less than 0.5"

+VCCP 1

+VCCP 1

MCH_PSWING 1 1

2

TXCLKTXCLK+

12 12

A

A

R258 49.9 0402 1% HAVREF 1 1 HCCVREF 1 1 2 2 1 1

R902 49.9 0402 1% HXSWING 1 2 1

R793 301 0402 1% HYSWING 1 1 2

R855 301 0402 1%

C836 0.1U 0402 +80-20% 50V

R910 C837 100 1U/NA 0402 0402 +80-20% 1% 10V 2

1

C287 0.1U 0402 +80-20% 50V

R257 C286 100 1U/NA 0402 0402 +80-20% 1% 10V 2

C840 0.1U 0402 +80-20% 50V

R913 C842 100 1U 0402 0402 +80-20% 1% 10V 2

C784 0.1U 0402 +80-20% 50V

R791 150 0402 1%

C815 0.1U 0402 +80-20% 50V

R850 150 0402 1%

GND REFSET 1 127 1% 2 R163

0402DVOCD0 0402DVOCD1 0402DVOCD2 0402DVOCD3 0402DVOCD4 0402DVOCD5 0402DVOCD6 0402DVOCD7 0402DVOCD8 0402DVOCD9 0402DVOCD10 0402DVOCD11

2

2

DVOCD[0..11]

2

2

2

2

2

2

2

2

Title

GND

GND

GND

GND

8050 MOTHER B/D

Size C Date: Document Number PCB 316680900001/ASSY 411680900011 Sheet

1

GND

Rev R01 of 34

Monday, December 29, 2003

4

5

4

3

2

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

6 NB_MA0 6 NB_MA3

NB_MA0 NB_MA3

NB_MONTARA-GME(2/2)

+1.35V U714D U714C NB_MD[0..63] SDQ[0] SDQ[1] SDQ[2] SDQ[3] SDQ[4] SDQ[5] SDQ[6] SDQ[7] SDQ[8] SDQ[9] SDQ[10] SDQ[11] SDQ[12] SDQ[13] SDQ[14] SDQ[15] SDQ[16] SDQ[17] SDQ[18] SDQ[19] SDQ[20] SDQ[21] SDQ[22] SDQ[23] SDQ[24] SDQ[25] SDQ[26] SDQ[27] SDQ[28] SDQ[29] SDQ[30] SDQ[31] SDQ[32] SDQ[33] SDQ[34] SDQ[35] SDQ[36] SDQ[37] SDQ[38] SDQ[39] SDQ[40] SDQ[41] SDQ[42] SDQ[43] SDQ[44] SDQ[45] SDQ[46] SDQ[47] SDQ[48] SDQ[49] SDQ[50] SDQ[51] SDQ[52] SDQ[53] SDQ[54] SDQ[55] SDQ[56] SDQ[57] SDQ[58] SDQ[59] SDQ[60] SDQ[61] SDQ[62] SDQ[63] SDQ[64] SDQ[65] SDQ[66] SDQ[67] SDQ[68] SDQ[69] SDQ[70] SDQ[71] SDQS[0] SDQS[1] SDQS[2] SDQS[3] SDQS[4] SDQS[5] SDQS[6] SDQS[7] SDQS[8] SDM[0] SDM[1] SDM[2] SDM[3] SDM[4] SDM[5] SDM[6] SDM[7] SDM[8] AF2 AE3 AF4 AH2 AD3 AE2 AG4 AH3 AD6 AG5 AG7 AE8 AF5 AH4 AF7 AH6 AF8 AG8 AH9 AG10 AH7 AD9 AF10 AE11 AH10 AH11 AG13 AF14 AG11 AD12 AF13 AH13 AH16 AG17 AF19 AE20 AD18 AE18 AH18 AG19 AH20 AG20 AF22 AH22 AF20 AH19 AH21 AG22 AE23 AH23 AE24 AH25 AG23 AF23 AF25 AG25 AH26 AE26 AG28 AF28 AG26 AF26 AE27 AD27 AG14 AE14 AE17 AG16 AH14 AE15 AF16 AF17 AG2 AH5 AH8 AE12 AH17 AE21 AH24 AH27 AD15 AE5 AE6 AE9 AH12 AD19 AD21 AD24 AH28 AH15 NB_MD0 NB_MD1 NB_MD2 NB_MD3 NB_MD4 NB_MD5 NB_MD6 NB_MD7 NB_MD8 NB_MD9 NB_MD10 NB_MD11 NB_MD12 NB_MD13 NB_MD14 NB_MD15 NB_MD16 NB_MD17 NB_MD18 NB_MD19 NB_MD20 NB_MD21 NB_MD22 NB_MD23 NB_MD24 NB_MD25 NB_MD26 NB_MD27 NB_MD28 NB_MD29 NB_MD30 NB_MD31 NB_MD32 NB_MD33 NB_MD34 NB_MD35 NB_MD36 NB_MD37 NB_MD38 NB_MD39 NB_MD40 NB_MD41 NB_MD42 NB_MD43 NB_MD44 NB_MD45 NB_MD46 NB_MD47 NB_MD48 NB_MD49 NB_MD50 NB_MD51 NB_MD52 NB_MD53 NB_MD54 NB_MD55 NB_MD56 NB_MD57 NB_MD58 NB_MD59 NB_MD60 NB_MD61 NB_MD62 NB_MD63 NB_CB0 NB_CB1 NB_CB2 NB_CB3 NB_CB4 NB_CB5 NB_CB6 NB_CB7 NB_DQS0 NB_DQS1 NB_DQS2 NB_DQS3 NB_DQS4 NB_DQS5 NB_DQS6 NB_DQS7 NB_DQS8 NB_DM[0..8] NB_DM0 NB_DM1 NB_DM2 NB_DM3 NB_DM4 NB_DM5 NB_DM6 NB_DM7 NB_DM8 +2.5VS_DDR U714E VCCSM_0 VCCSM_1 VCCSM_2 VCCSM_3 VCCSM_4 VCCSM_5 VCCSM_6 VCCSM_7 VCCSM_8 VCCSM_9 VCCSM_10 VCCSM_11 VCCSM_12 VCCSM_13 VCCSM_14 VCCSM_15 VCCSM_16 VCCSM_17 VCCSM_18 VCCSM_19 VCCSM_20 VCCSM_21 VCCSM_22 VCCSM_23 VCCSM_24 VCCSM_25 VCCSM_26 VCCSM_27 VCCSM_28 VCCSM_29 VCCSM_30 VCCSM_31 VCCSM_32 VCCSM_33 VCCSM_34 VCCSM_35 VCCSM_36 VCCTXLVDS_0 VCCTXLVDS_1 VCCTXLVDS_2 VCCTXLVDS_3 VTTHF_0 VTTHF_1 VTTHF_2 VTTHF_3 VTTHF_4 VTTLF_0 VTTLF_1 VTTLF_2 VTTLF_3 VTTLF_4 VTTLF_5 VTTLF_6 VTTLF_7 VTTLF_8 VTTLF_9 VTTLF_10 VTTLF_11 VTTLF_12 VTTLF_13 VTTLF_14 VTTLF_15 VTTLF_16 VTTLF_17 VTTLF_18 VTTLF_19 VTTLF_20 AG29 AF29 AC29 AF27 AJ25 AF24 AB22 AJ21 AF21 AB20 AF18 AB18 AJ17 AB16 AF15 AB14 AJ13 AA13 AF12 AB12 AA11 AB10 AJ9 AF9 Y9 AB8 AA8 Y7 AF6 AB6 AA6 AJ5 Y4 AF3 AB3 AG1 AC1 A12 D10 B10 F9 V29 M29 H29 A24 A22 AB29 Y29 K29 F29 A26 V22 T22 P22 M22 H22 U21 R21 N21 L21 H20 A20 J19 H18 A18 H16 G15 1 1 1 C202 0.1U 0402 +80-20% 50V C271 C252 10U 0.1U 0402 16V +80-20% 1206 50V 2 AA29 W29 U29 N29 L29 J29 G29 E29 C29 AE28 AC28 E28 D28 AJ27 AG27 AC27 F27 A27 AJ26 AB26 W26 R26 N26 L26 J26 G26 AE25 AA25 D25 A25 AG24 AA24 V24 T24 P24 M24 K24 H24 F24 B24 AJ23 AC23 AA23 D23 A23 AE22 W22 U22 R22 N22 L22 J22 F22 C22 AG21 AB21 AA21 Y21 V21 T21 P21 M21 H21 D21 A21 AJ20 AC20 AA20 J20 F20 AE19 AB19 H19 D19 A19 AJ18 AG18 AA18 J18 F18 AC17 AB17 U17 R17 N17 H17 D17 A17 AE16 AA16 T16 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 855GM/GME BGA707_25 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_126 VSS_125 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 P16 J16 F16 AG15 AB15 U15 R15 N15 H15 D15 AC14 AA14 T14 P14 J14 AE13 AB13 U13 R13 N13 H13 F13 D13 A13 AJ12 AG12 AA12 J12 AJ11 AC11 AB11 H11 F11 D11 AJ10 AE10 AA10 C10 AG9 AB9 W9 U9 T9 R9 N9 L9 E9 AC8 Y8 V8 T8 P8 K8 H8 AJ7 AE7 AA7 R7 M7 J7 G7 E7 C7 AG6 Y6 L6 Y5 U5 B5 AE4 AC4 AA4 W4 T4 N4 K4 G4 D4 AJ3 AG3 R2 AJ1 AE1 AA1 U1 L1 G1 C1 J10 U26 1 1 1 C302 0.1U 0402 +80-20% 50V C325 10U 0805 6.3V 10% 1 2 NB_MA0 SMA1 SMA2 NB_MA3 SMA4 SMA5 NB_MA6 NB_MA7 NB_MA8 NB_MA9 NB_MA10 NB_MA11 NB_MA12 SMAB1 SMAB2 SMAB4 SMAB5 AC18 AD14 AD13 AD17 AD11 AC13 AD8 AD7 AC6 AC5 AC19 AD5 AB5 AD16 AC12 AF11 AD10 AD25 AC24 AC21 AD22 AD20 AD23 AD26 AC22 AC25 AC7 AB7 AC9 AC10 AB2 AA2 AC26 AB25 AC3 AD4 AC2 AD2 AB23 AB24 AA3 AB4 AJ19 AJ22 AJ24 NB_MD[0..63] 6 1 1 C243 10U 0805 6.3V 10% C282 0.1U 0402 +80-20% 50V 1 C293 0.1U 0402 +80-20% 50V SMA[0] SMA[1] SMA[2] SMA[3] SMA[4] SMA[5] SMA[6] SMA[7] SMA[8] SMA[9] SMA[10] SMA[11] SMA[12] SMAB[1] SMAB[2] SMAB[4] SMAB[5] SWE# SCAS# SRAS# SBA[0] SBA[1] SCS[0]# SCS[1]# SCS[2]# SCS[3]# SCKE[0] SCKE[1] SCKE[2] SCKE[3] SCK[0] SCK[0]# SCK[1] SCK[1]# SCK[2] SCK[2]# SCK[3] SCK[3]# SCK[4] SCK[4]# SCK[5] SCK[5]# SMVSWINGH SMVSWINGL SMVREF_0 SMRCOMP W21 AA19 AA17 T17 P17 U16 R16 N16 AA15 T15 P15 J15 U14 R14 N14 H14 T13 P13 V9 W8 U8 V7 U6 W5 Y1 V1 P9 M9 K9 R8 N8 M8 L8 J8 H7 E6 M4 J4 E4 N1 J1 E1 B15 B14 J13 G13 B9 A9 AF1 AD1 A4 A3 AJ8 AJ6 A6 B16 Y2 D29 A11 B11 B8 VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCCHL_0 VCCHL_1 VCCHL_2 VCCHL_3 VCCHL_4 VCCHL_5 VCCHL_6 VCCHL_7 VCCDVO_0 VCCDVO_1 VCCDVO_2 VCCDVO_3 VCCDVO_4 VCCDVO_5 VCCDVO_6 VCCDVO_7 VCCDVO_8 VCCDVO_9 VCCDVO_10 VCCDVO_11 VCCDVO_12 VCCDVO_13 VCCDVO_14 VCCDVO_15 VCCDLVDS_0 VCCDLVDS_1 VCCDLVDS_2 VCCDLVDS_3 VCCADAC_0 VCCADAC_1 VCCASM_0 VCCASM_1 VCCGPIO_0 VCCGPIO_1 VCCQSM_0 VCCQSM_1 VCCADPLLA VCCADPLLB VCCAGPLL VCCAHPLL VCCALVDS VSSALVDS VSSADAC 855GM/GME BGA707_25 2 C290 0.1U 0402 +80-20% 50V GND 1 1 C309 0.1U 0402 +80-20% 50V GND 1 1 C303 0.1U 0402 +80-20% 50V GND 1 1 C291 0.1U 0402 +80-20% 50V GND C300 0.1U 0402 +80-20% 50V 1 C314 10U 0805 6.3V 10% C299 0.1U 0402 +80-20% 50V 1 C281 10U 0805 6.3V 10% C301 0.1U 0402 +80-20% 50V C324 10U 0805 6.3V 10% 2 2 2 2 2

6 SMA[1..2] 6 SMA[4..5] 6 6 6 6 6 6 6 NB_MA12 6 SMAB[1..2] 6 SMAB[4..5]

SMA[1..2] SMA[4..5] NB_MA6 NB_MA7 NB_MA8 NB_MA9 NB_MA10 NB_MA11 SMAB[1..2] SMAB[4..5]

1

1

1

D

C288 0.1U 0402 +80-20% 50V

C218 0.1U 0402 +80-20% 50V

C255 0.1U 0402 +80-20% 50V

1 C273 0.1U 0402 +80-20% 50V

D

2

2

2

2

2

2

GND

+1.35V 1 1 C272 10U 0805 6.3V 10% C247 0.1U 0402 +80-20% 50V 1 C276 0.1U 0402 +80-20% 50V

2

2

2

2

6 NB_BA0 6 NB_BA1 6 CS#0 6 CS#1 6 CS#2 6 CS#3 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 CKE0 CKE1 CKE2 CKE3 NB_CLK_DDR0 NB_CLK_DDR0# NB_CLK_DDR1 NB_CLK_DDR1# NB_CLK_DDR2 NB_CLK_DDR2# NB_CLK_DDR3 NB_CLK_DDR3# NB_CLK_DDR4 NB_CLK_DDR4# NB_CLK_DDR5 NB_CLK_DDR5# MCH_SMVSWINGH MCH_SMVSWINGL +1.25V_DDR

GND +1.5V 1 1 C234 10U 0805 6.3V 10% GND C232 0.1U 0402 +80-20% 50V 1 C205 0.1U 0402 +80-20% 50V

2

2

2

2

2

2

VCCTXLVDS

+1.5V 1 1 C263 10U 0805 6.3V 10% GND C184 0.1U 0402 +80-20% 50V 1 C197 0.1U 0402 +80-20% 50V

C

VTTHF_0 VTTHF_1 VTTHF_2 VTTHF_3 VTTHF_4

2

2

2

2

2

6 NB_WE# 6 NB_CAS# 6 NB_RAS#

2

C

VCCADAC VCCASM VCCGPIO VCCQSM VCCADPLLA VCCADPLLB

1 C328 MCH_SMRCOMP 0.1U 0402 +80-20% 50V GND TP40 TP35 TP703 TP41 TP25 1 1 1 1 1

AB1

2

F12 D12 B12 AA5 D7

RSVD_0 RSVD_1 RSVD_2 RSVD_3 RSVD_4

NB_CB[0..7]

NB_CB[0..7]

6

VCCAGPLL VCCAHPLL +1.5V 1 L714 120Z/100M 2 1 C777 0.1U 0402 +80-20% 50V 1 VCCALVDS C343 0.01U 0402 +80-20% 50V

+VCCP

7 GCBE2# 7 GST0 7 GST1 7 GST2 7 GSBSTB 7 GSBSTB# 7 GRBF# 7 GWBF# 7 GGNT# 7 GREQ#

B

L4 C4 C3 C2 F2 F3 D3 D2 B2 B3

RSVD_5 GST[0] GST[1] GST[2] RSVD_6 RSVD_7 RSVD_8 RSVD_9 RSVD_10 RSVD_11

NB_DQS[0..8]

1 2

NB_DQS[0..8]

6

C238 10U 16V 1206

2

2

GND

VSSADAC

2

GND

NB_DM[0..8]

6 +1.5V 1 L717 120Z/100M 2 1 1 VCCADAC +1.35V 1 L727 120Z/100M 2 1 1 1 C852 10U 16V 1206 C850 10U 16V 1206 1 VCCASM

B

C779 0.1U 0402 +80-20% 50V GND

C786 0.01U 0402 +80-20%VSSADAC 50V

C851 10U 0805 6.3V 10%

C848 0.01U 0402 +80-20% 50V

2

2

2

2

2

2

GND GND

GND

855GM/GME BGA707_25

+1.35V

1 L720 120Z/100M

2 1

VCCAHPLL

+1.35V 1 L45 120Z/100M

2 1

VCCAGPLL

+3V 1 L715 120Z/100M

2 1 C783 10U 0805 6.3V 10% GND 1

VCCGPIO C776 0.01U 0402 +80-20% 50V

C808 0.1U 0402 +80-20% 50V GND

C297 0.1U 0402 +80-20% 50V GND

2

2

VTTHF_0 VTTHF_1 VTTHF_2 VTTHF_3

+1.5V 1

+1.5V 1

R822 1K 0402 5% 2 2

R806 1K/NA 0402 5% +2.5VS_DDR GST0 GST1 1

Place within 0.5" with 15-mil wide.

+2.5VS_DDR +2.5VS_DDR

+1.35V

1 L38 120Z/100M

2 1 1 C166 10U 16V 1206

VCCADPLLA C171 0.01U 0402 +80-20% 50V

+1.35V

1 L713 120Z/100M

2 1 C772 10U 16V 1206 1

VCCADPLLB C785 0.01U 0402 +80-20% 50V

VTTHF_4

0.1U 50V 0.1U 50V 0.1U 50V 0.1U 50V 0.1U 50V

1 1 1 1 1

2 2 2 2 2

0402 +80-20% 0402 +80-20% 0402 +80-20% 0402 +80-20% 0402 +80-20%

C832 C818 C814 C780 C781

2

2

GND

2

2

2

1

1

CHANGE TO 0402 R945 604 0603 1%

CHANGE TO 0402 R942 150 0402 1%

1

A

R923 60.4 0402 1% MCH_SMVSWINGH 1 1 2

Clock config bit GST[1,0] PSB/Sys Mem Core/GFX Core(CL/CH) 00(def): 400/266/200(133/200) 01 10 : 400/200/200(100/200) : 400/200/133(100/133)

CHANGE TO 0402

MCH_SMVSWINGL 1 R941 150 0402 1%

C847 0.1U 0402 +80-20% 50V MCH_SMRCOMP

GND

GND

A

2

+2.5VS_DDR +2.5VS_DDR 1 2 L42 120Z/100M VCCTXLVDS 1 1 1 +2.5V_M10 C176 0.01U 0402 +80-20% 50V 1 VCCQSM 1 1 C859 0.01U 0402 +80-20% 50V

2

1

1

2

C857 0.1U 0402 +80-20% 50V

CHANGE TO 0402 2

R946 604 0603 1%

C858 0.1U 0402 +80-20% 50V

R924 60.4 0402 1% 2

1

C846 0.1U/NA 0402 +80-20% 50V

1 L729 120Z/100M 2 L730 120Z/100M/NA

2 C860 4.7U 0603 6.3V +80-20%

C174 10U 16V 1206

2

2

2

GND

GND

GND

C227 10U 0805 6.3V 10%

2

2

Title

2

2

2

2

2

8050 MOTHER B/D

Size C Date: Document Number PCB 316680900001/ASSY 411680900011 Sheet 5 of 34

1

GND

5 4 3 2

GND

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

5 NB_MD[0..63]

D

C

NB_MD[0..63] NB_MD0 R1062 1 NB_MD1 R1061 1 NB_MD2 R1059 1 NB_MD3 R1058 1 NB_MD4 R1001 1 NB_MD5 R1000 1 NB_MD6 R998 1 NB_MD7 R997 1 NB_MD8 R1057 1 NB_MD9 R1056 1 NB_MD10R1054 1 NB_MD11R1053 1 NB_MD12R996 1 NB_MD13R995 1 NB_MD14R993 1 NB_MD15R992 1 NB_MD16R1052 1 NB_MD17R1051 1 NB_MD18R1049 1 NB_MD19R1048 1 NB_MD20R991 1 NB_MD21R990 1 NB_MD22R988 1 NB_MD23R987 1 NB_MD24R1047 1 NB_MD25R1046 1 NB_MD26R1044 1 NB_MD27R1043 1 NB_MD28R986 1 NB_MD29R985 1 NB_MD30R983 1 NB_MD31R982 1 NB_MD32R1028 1 NB_MD33R1027 1 NB_MD34R1025 1 NB_MD35R1024 1 NB_MD36R967 1 NB_MD37R966 1 NB_MD38R964 1 NB_MD39R963 1 NB_MD40R1023 1 NB_MD41R1022 1 NB_MD42R1020 1 NB_MD43R1019 1 NB_MD44R962 1 NB_MD45R961 1 NB_MD46R959 1 NB_MD47R958 1 NB_MD48R1018 1 NB_MD49R1017 1 NB_MD50R1015 1 NB_MD51R1014 1 NB_MD52R957 1 NB_MD53R956 1 NB_MD54R954 1 NB_MD55R953 1 NB_MD56R1013 1 NB_MD57R1012 1 NB_MD58R1010 1 NB_MD59R1009 1 NB_MD60R952 1 NB_MD61R951 1 NB_MD62R949 1 NB_MD63R948 1 NB_DQS[0..7] NB_DQS0 NB_DQS1 NB_DQS2 NB_DQS3 NB_DQS4 NB_DQS5 NB_DQS6 NB_DQS7 NB_DM[0..7] NB_DM0 NB_DM1 NB_DM2 NB_DM3 NB_DM4 NB_DM5 NB_DM6 NB_DM7 NB_CB[0..7] NB_CB0 NB_CB1 NB_CB2 NB_CB3 NB_CB4 NB_CB5 NB_CB6 NB_CB7 R999 R994 R989 R984 R965 R960 R955 R950 1 1 1 1 1 1 1 1 R1060 1 R1055 1 R1050 1 R1045 1 R1026 1 R1021 1 R1016 1 R1011 1

10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402

MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 MCB0 MCB1 MCB2 MCB3 MCB4 MCB5 MCB6 MCB7

NB_DQS[0..7]

NB_DM[0..7]

MD0 MD4 MD1 MD5 DQS0 DM0 MD2 MD6 MD3 MD7 MD8 MD12 MD9 MD13 DQS1 DM1 MD10 MD14 MD11 MD15 MD16 MD20 MD17 MD21 DQS2 DM2 MD18 MD22 MD19 MD23 MD24 MD28 MD25 MD29 DQS3 DM3 MD26 MD30 MD27 MD31 MD32 MD36 MD33 MD37 DQS4 DM4 MD34 MD38 MD35 MD39 MD40 MD44 MD41 MD45 DQS5 DM5 MD42 MD46 MD43 MD47 MD48 MD52 MD49 MD53 DQS6 DM6 MD50 MD54 MD51 MD55 MD56 MD60 MD57 MD61 DQS7 DM7 MD58 MD62 MD59 MD63

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

RP43 56*8 RPX8

RP42 56*8 RPX8

RP41 56*8 RPX8

RP40 56*8 RPX8

RP39 56*8 RPX8

1

1

1

1

RP33 56*8 RPX8

RP32 56*8 RPX8

RP31 56*8 RPX8

RP30 56*8 RPX8

1

1

1

1

C433 0.01U 0402 +80-20% 50V

C430 0.01U 0402 +80-20% 50V

C428 0.01U 0402 +80-20% 50V

C425 0.01U 0402 +80-20% 50V

1

RP29 56*8 RPX8

16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9

+1.25V_DDR

DDR -SODIMM

+2.5VS_DDR +DDR_VREF J711 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 0.6MM/200P/H9.2 QUASAR CA0145-200N01 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 0.6MM/200P/H5.2 QUASAR CA0115-200N01 +2.5VS_DDR +DDR_VREF J712 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

MD0 MD1 DQS0 MD2 MD3 MD8 MD9 DQS1 MD10 MD11 CLK_DDR0 CLK_DDR0#

MD4 MD5 DM0 MD6 MD7 MD12 MD13 DM1 MD14 MD15

MD0 MD1 DQS0 MD2 MD3 MD8 MD9 DQS1 MD10 MD11 CLK_DDR3 CLK_DDR3#

MD4 MD5 DM0 MD6 MD7 MD12 MD13 DM1 MD14 MD15

D

MD16 MD17 DQS2 MD18 MD19 MD24 +2.5VS_DDR MD25 DQS3 C868 0.1U 0402 +80-20% 50V C331 0.1U 0402 +80-20% 50V C347 0.1U 0402 +80-20% 50V C369 0.1U 0402 +80-20% 50V 1 MD26 MD27 MCB0 MCB1 DQS8 MCB2 MCB3 CLK_DDR2 CLK_DDR2# GND CKE1 MA12 MA9 MA7 SMA5 MA3 SMA1 MA10 BA0 WE# CS#0 MD32 MD33 DQS4 MD34 MD35 MD40 MD41 DQS5 1 1 1 1

MD20 MD21 DM2 MD22 MD23 MD28 MD29 DM3 MD30 MD31 MCB4 MCB5 DM8 MCB6 MCB7

MD16 MD17 DQS2 MD18 MD19 MD24 MD25 DQS3 MD26 MD27 MCB0 MCB1 DQS8 MCB2 MCB3 CKE1_S1 CLK_DDR5 CLK_DDR5#

MD20 MD21 DM2 MD22 MD23 MD28 MD29 DM3 MD30 MD31 MCB4 MCB5 DM8 MCB6 MCB7 CKE0_S1

C

2

2

2

1

1

C333 0.1U 0402 +80-20% 50V

C349 0.1U 0402 +80-20% 50V

1

2

C350 0.1U 0402 +80-20% 50V

C332 0.1U 0402 +80-20% 50V

2

2

2

2

CKE0 MA11 MA8 MA6 SMA4 SMA2 MA0 BA1 RAS# CAS# CS#1 MD36 MD37 DM4 MD38 MD39 MD44 MD45 DM5 MD46 MD47 CLK_DDR1# CLK_DDR1 MD52 MD53 DM6 MD54 MD55 MD60 MD61 DM7 MD62 MD63

CKE3 CS#0_S1 NB_MA12 NB_MA9 NB_MA7 SMAB5 NB_MA3 SMAB1 NB_MA10 NB_BA0 NB_WE# CS#2 MD32 MD33 DQS4 MD34 MD35 MD40 MD41 DQS5 MD42 MD43

CKE2 NB_MA11 NB_MA8 NB_MA6 SMAB4 SMAB2 NB_MA0 NB_BA1 NB_RAS# NB_CAS# CS#3 CS#1_S1 MD36 MD37 DM4 MD38 MD39 MD44 MD45 DM5 MD46 MD47 CLK_DDR4# CLK_DDR4 MD52 MD53 DM6 MD54 MD55 MD60 MD61 DM7 MD62 MD63 +3V

B

+1.25V_DDR

1

C427 0.01U 0402 +80-20% 50V

C434 0.01U 0402 +80-20% 50V

C431 0.01U 0402 +80-20% 50V

C429 0.01U 0402 +80-20% 50V

C426 0.01U 0402 +80-20% 50V C432 0.01U 0402 +80-20% 50V

2

2

2

2

2

2

2

2

GND

NB_CB[0..7]

2

2

2

2

5 5 5 5 5 5 5 5 5 5 5 5 5 5

NB_MA0 NB_MA3 NB_MA6 NB_MA7 NB_MA8 NB_MA9 NB_MA10 NB_MA11 NB_MA12 NB_WE# NB_CAS# NB_RAS# NB_BA0 NB_BA1

NB_MA0 R972 1 NB_MA3 R1033 1 NB_MA6 R973 1 NB_MA7 R1034 1 NB_MA8 R974 1 NB_MA9 R1035 1 NB_MA10 R1032 1 NB_MA11 R975 1 NB_MA12 R1036 1 NB_WE# R1030 1 NB_CAS#R969 1 NB_RAS#R970 1 NB_BA0 R1031 1 NB_BA1 R971 1 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

5 NB_DM8 5 NB_DQS8

SMA1 SMA2 SMA4 SMA5 SMAB1 SMAB2 SMAB4 SMAB5 CKE0 CKE1 CKE2 CKE3 CS#0 CS#1 CS#2 CS#3 R979 1 10 R1040 1 10

MA0 MA3 MA6 MA7 MA8 MA9 MA10 MA11 MA12 WE# CAS# RAS# BA0 BA1 SMA1 SMA2 SMA4 SMA5 SMAB1 SMAB2 SMAB4 SMAB5 CKE0 CKE1 CKE2 CKE3 CS#0 CS#1 CS#2 CS#3 DM8 2 0402 DQS8 2 0402

SMAB4 SMAB2 SMA5 SMA2 NB_MA12 NB_MA11 NB_MA8 NB_MA9 NB_BA0 NB_WE# NB_CAS# NB_RAS# CS#1 CS#2 CS#3 CS#0 MCB3 MCB7 CKE1 CKE0 CKE2 CKE3 SMAB5 SMA4 NB_MA7 NB_MA6 NB_MA3 SMA1 SMAB1 NB_MA10 NB_MA0 NB_BA1

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

RP36 56*8 RPX8

RP34 56*8 RPX8

RP37 56*8 RPX8

RP35 56*8 RPX8

16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9

1

1

1

1

2

B

R1042 1 R1041 1 R1039 1 R1038 1 R981 1 R980 1 R978 1 R977 1

MCB1 MCB0 MCB4 MCB5 DQS8 DM8 MCB6 MCB2

1 2 3 4 5 6 7 8

RP38 56*8 RPX8

16 15 14 13 12 11 10 9

+2.5VS_DDR MD42 MD43 1 1 1 1 C348 1U 0402 +80-20% 10V C334 0.1U 0402 +80-20% 50V C371 1U 0402 +80-20% 10V C370 0.1U 0402 +80-20% 50V C353 0.1U 0402 +80-20% 50V C335 0.1U 0402 +80-20% 50V C352 0.1U 0402 +80-20% 50V 1 C351 0.1U 0402 +80-20% 50V 1 C372 0.1U 0402 +80-20% 50V C336 1U 0402 +80-20% 10V

2

2

MD48 MD49 DQS6 MD50 MD51 MD56 MD57 DQS7 MD58 MD59

MD48 MD49 DQS6 MD50 MD51 MD56 MD57 DQS7 MD58 MD59 SMBDATA SMBCLK +3V

2

2

2

2

GND

2

11,14 SMBDATA 11,14 SMBCLK +3V 5 5 5 5 5 5 5 5 5 5 5 5 +1.25V_DDR 1 1 NB_CLK_DDR0 NB_CLK_DDR0# NB_CLK_DDR1 NB_CLK_DDR1# NB_CLK_DDR2 NB_CLK_DDR2# NB_CLK_DDR3 NB_CLK_DDR3# NB_CLK_DDR4 NB_CLK_DDR4# NB_CLK_DDR5 NB_CLK_DDR5# R338 R337 R319 R320 R336 R335 R354 R352 R359 R360 R351 R347 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 2 2 2 2 2 2 2 2 2 2 2 2 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% CLK_DDR0 CLK_DDR0# CLK_DDR1 CLK_DDR1# CLK_DDR2 CLK_DDR2# CLK_DDR3 CLK_DDR3# CLK_DDR4 CLK_DDR4# CLK_DDR5 CLK_DDR5#

SMBDATA SMBCLK

GND

GND +1.25V_DDR

1

1

1

1

+2.5VS_DDR 1 1 1 1

A

1

1

1

1

1

1

R976 1 0 0402 2 R1037 1 0 0402 2 R1029 1 0 0402 2 R968 1 0 0402 2

5% 5% 5% 5%

CKE0_S1 CKE1_S1 CS#0_S1 CS#1_S1

C387 0.01U 0402 +80-20% 50V C394 0.01U 0402 +80-20% 50V C404 0.01U 0402 +80-20% 50V

C388 0.01U 0402 +80-20% 50V C397 0.01U 0402 +80-20% 50V C405 0.01U 0402 +80-20% 50V

C389 0.01U 0402 +80-20% 50V C400 0.01U 0402 +80-20% 50V C406 0.01U 0402 +80-20% 50V

C390 0.01U 0402 +80-20% 50V C403 0.01U 0402 +80-20% 50V C412 0.01U 0402 +80-20% 50V

C392 0.01U 0402 +80-20% 50V C409 0.01U 0402 +80-20% 50V C407 0.01U 0402 +80-20% 50V

C391 0.01U 0402 +80-20% 50V C408 0.01U 0402 +80-20% 50V C414 0.01U 0402 +80-20% 50V

C393 0.01U 0402 +80-20% 50V C411 0.01U 0402 +80-20% 50V C420 0.01U 0402 +80-20% 50V

C396 0.01U 0402 +80-20% 50V C416 0.01U 0402 +80-20% 50V C402 0.01U 0402 +80-20% 50V

C395 0.01U 0402 +80-20% 50V C413 0.01U 0402 +80-20% 50V C410 0.01U 0402 +80-20% 50V

C398 0.01U 0402 +80-20% 50V C417 0.01U 0402 +80-20% 50V C421 0.01U 0402 +80-20% 50V

C399 0.01U 0402 +80-20% 50V C418 0.01U 0402 +80-20% 50V C419 0.01U 0402 +80-20% 50V

C401 0.01U 0402 +80-20% 50V C415 0.01U 0402 +80-20% 50V

1

1

1

1

1

1

1

R340 75 0402 1% 1 2

1

C436 10U 0805 6.3V 10%

C437 10U 0805 6.3V 10%

C422 0.1U 0402 +80-20% 50V

C423 0.1U 0402 +80-20% 50V

1 C424 0.1U 0402 +80-20% 50V

A

+1.25V_DDR

2

2

2

2

1

C337 0.01U 0402 +80-20% 50V

C346 0.1U 0402 +80-20% 50V 1

+DDR_VREF

GND

2

2

2

2

2

2

2

2

2

2

2

2

2

1

1

1

1

1

1

1

1

2

R334 75 0402 1% 2

2

2

2

2

2

2

1

1

1

1

1

1

C386 0.01U 0402 +80-20% 50V

C366 0.1U 0402 +80-20% 50V

C338 0.1U 0402 +80-20% 50V

1

C384 0.1U 0402 +80-20% 50V Title

2

2

2

2

2

2

1

1

1

1

1

2

2

2

2

GND Size C Date:

2

8050 MOTHER B/D

Document Number PCB 316680900001/ASSY 411680900011 Sheet 6 of 34

1

2

2

2

2

2

2

GND

3

Rev R01

2

2

2

2

2

GND

5 4

2

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

+3V M10_GPIO0 R743 1 10K/NA 2 0402 R742 1 10K/NA 2 0402 M10_GPIO1 AGP_VDDQ GND AGP MODE 1 R744 1 10K/NA 2 0402 R739 1 10K/NA 2 0402 M10_GPIO2 R738 1 10K/NA 2 0402 R737 1 10K/NA 2 0402 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 ROMCS# ZV_LCDDATA0 ZV_LCDDATA1 ZV_LCDDATA2 ZV_LCDDATA3 ZV_LCDDATA4 ZV_LCDDATA5 ZV_LCDDATA6 ZV_LCDDATA7 ZV_LCDDATA8 ZV_LCDDATA9 ZV_LCDDATA10 ZV_LCDDATA11 ZV_LCDDATA12 ZV_LCDDATA13 ZV_LCDDATA14 ZV_LCDDATA15 ZV_LCDDATA16 ZV_LCDDATA17 ZV_LCDDATA18 ZV_LCDDATA19 ZV_LCDDATA20 ZV_LCDDATA21 ZV_LCDDATA22 ZV_LCDDATA23 ZV_LCDCNTL0 ZV_LCDCNTL1 ZV_LCDCNTL2 ZV_LCDCNTL3 TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P TXCLK_LN TXCLK_LP TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P TXCLK_UN TXCLK_UP DIGON BLON TX0M TX0P TX1M TX1P TX2M TX2P TXCM TXCP DDC2CLK DDC2DATA HPD1 DDC3CLK DDC3DATA SSIN SSOUT R G B HSYNC VSYNC RSET X1 X2 R776 1 1M/NA 2 0402 5% GND AGP_VDDQ 1 1 X702 2 1 13 R775 1 R774 1 0/NA 2 0402 0/NA 2 0402 R102 1 0402 R100 1 1K/NA 2 5% 0/NA 2 0402 AH28 AJ29 AH27 AG26 XTALIN XTALOUT DDC1DATA DDC1CLK TESTEN SUS_STAT# MOBILITY-M10-P/NA BGA644_64_1MM R101 2 20K/NA 0402 1% ATI_CRT_RED ATI_CRT_GREEN ATI_CRT_BLUE 1 1 1 AUXWIN AF26 1 TEST_MCLK TEST_YCLK AJ5 AH5 AJ4 AK4 AH4 AF4 AJ3 AK3 AH3 AJ2 AH2 AH1 AG3 AG1 AG2 AF3 AF2 AF5 AH6 AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 R77 AF8 R78 AE9 R76 AF9 R405 AG10R406 AF10 R407 AJ10 1 AK102 AJ11 3 AH114 AK16 AH16 AH17 AJ16 AH18 AJ17 AK19 AH19 AK18 AJ18 AG16 AF16 AG17 AF17 AF18 AE18 AH20 AG20 AF19 AG19 AE12 AG12 AJ13 AH14 AJ14 AH15 AJ15 AK15 AH13 AK13 AE13 AE14 AF12 AK27 AJ27 AJ26 AG25 AH25 AH26 B6 E8 AF25 AF24 R104 2 +3V R786 2 620/NA C774 0603 0.1U/NA 0402 5% 10% 16V 1 1 1 M10_GPIO0 M10_GPIO1 M10_GPIO2 M10_GPIO3 M10_GPIO4 M10_GPIO5 M10_GPIO6 M10_GPIO7 M10_GPIO8 M10_GPIO9 M10_GPIO10 M10_GPIO11 M10_GPIO12 M10_GPIO13 M10_GPIO14 OSC_SPREAD GND PANEL_ID0 PANEL_ID1 PANEL_ID2 PANEL_ID3 1 1 1 C69 0.01U/NA 0402 +80-20% 50V 1 1 1 TP53 TP54 TP55 C734 0.01U/NA 0402 +80-20% 50V C733 0.01U/NA 0402 +80-20% 50V 1 C68 0.01U/NA 0402 +80-20% 50V 12,14,24 12,14,24 12,14,24 12,14,24 GND R82 R58 0402 1 10K/NA 2 ZV11 1 10K/NA 2 ZV12 0402 M10_GPIO3 +3VS R734 1 10K/NA 2 0402 R733 1 10K/NA 2 0402 M10_GPIO13 M10_GPIO10 M10_GPIO7 M10_GPIO14 RP715 1 2 3 4 5 10K*8/NA 1206 10 9 8 7 6 M10_GPIO11 M10_GPIO12 M10_GPIO9 M10_GPIO8

ATI M10-P(1/4)

R779

1.02K

Bus configuration straps 1.5V, AGP4X, ID=16

M10_GPIO4 M10_GPIO5 M10_GPIO6 R61 1 10K/NA 2 0402 R57 1 10K/NA 2 0402 R735 1 10K/NA 2 0402

R777

1.02K

AGP2.0(4X).75V R120 1.02K/NA 0402 1%

D

AGP3.0(8X).35V

324

100

4,24 AGP_AD[0..31]

AGP_AD[0..31] AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 H29 H28 J29 J28 K29 K28 L29 L28 N28 P29 P28 R29 R28 T29 T28 U29 N25 R26 P25 R27 R25 T25 T26 U25 V27 W26 W25 Y26 Y25 AA26 AA25 AA27 N29 U28 P26 U26 AG30 AG28 AF28 AD26 M25 N26 V29 V28 W29 W28 AE26 AC26 AH30 AH29 AE29 M28 V25 AB29 AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 AGP_ST0 AGP_ST1 AGP_ST2 AD28 AD29 AC28 AC29 AA28 AA29 Y28 Y29 AF29 AD27 AE28 AB28 M29 V26 C145 1 0402 2 0.1U/NA 50V +80-20% R762 1 0603 2 AK21 715/NA5% ATI_TV_CRMA AJ23 ATI_TV_LUMA AJ22 ATI_TV_COMP AK22 AJ24 AK24 AG23 AG24 M26 M27 AC25

D

U710A AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE#0 C/BE#1 C/BE#2 C/BE#3 PCICLK RST# REQ# GNT# PAR STOP# DEVSEL# TRDY# IRDY# FRAME# INTA# WBF# STP_AGP# AGP_BUSY# RBF# AD_STBF0 AD_STBF1 SB_STBF SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 ST0 ST1 ST2 SB_STBS AD_STBS0 AD_STBS1 AGPREF AGPTEST AGP8X_DET# R2SET C_R Y_G COMP_B H2SYNC V2SYNC

2

1

AGP_VREF 1 R110 1.02K/NA 0402 1% 1 C149 0.01U/NA 0402 50V 10% 2 2 C146 10U/NA 0805 6.3V 10%

14

For MEM_ID

U703A GND SW_1.5V/1.25V 30 ZV13 R66 R67 74AHC14_V TSSOP14 2

GND +3V 1 10K/NA 2 0402 1 10K/NA 2 0402 GND

2

1

GND

7

R83 R62

1 1K/NA 1 1K/NA SW701 1 2

2 0402 2 0402 4 3 +3V R748 1 1K/NA R749 1 1K/NA 2 0402 2 0402 +3V

HDS402/NA SW_HDS402

ZV11 0

ZV12 0 0 1 1

ZV13

64M Samsung Infineon EtroTech Hynix EtroTech H230904RAT309A K4D263238E-GL36 HYB25D128323CL3.6 EM6A9320B1-3.6M

C

2

2

2

2

4,5 AGP_CBE#[0..3]

C

AGP_CBE#[0..3] AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3

Reserve

64M

GND

FOR M10

GND C773 1 0402

AGP MODE M9+

R794 49.9R

M10

AGP_VDDQ R119 1 2

40R

5% 2 0402 2 22P/NA R778 1 50V +/-10% 33/NA R779 1 0/NA 5% 2 0402 11 66M_AGP R105 22/NA 2 1 13 ATI_PCIRST# 0402 5% 5 AGP_REQ# 5 AGP_GNT# 4 AGP_PAR 4 AGP_STOP# 4 AGP_DEVSEL# 4 AGP_TRDY# 4 AGP_IRDY# 4 AGP_FRAME# R122 5% 1 0/NA 2 0402 13,24 PCI_INTA# R118 5% 1 0/NA 2 0402 5 AGP_WBF# STP_AGP# AGPBUSY#

TP1 1 TP2 1 5% 1 33/NA 2 0402 5% 1 33/NA 2 0402 10K/NA 0402 1 2 ZV11 1 0/NA 2 0402 2 5% ZV12 1 0/NA 0402 2 5% ZV13 1 0/NA 0402 5% RP718 8 0*4/NA 7 1206 6 5

1

I2C_DAT I2C_CLK +3V 1 R72 2.21K/NA 0402 1% 2 2 1 R79 2.21K/NA 0402 1% +3V GND 4 4 4 4 4 4 4 4 4 4

Reserve 64M Reserve 64M Reserve 128M

0 1

AGPTEST

40.2/NA 1% 0402

13,24 STP_AGP# 4,13,24 AGPBUSY# 5 AGP_RBF# 4 AGP_ADSTB0 4 AGP_ADSTB1 5 AGP_SBSTBF 4 AGP_SBA[0..7]

AGP_SBA[0..7]

5 5 5

B

AGP_ST0 AGP_ST1 AGP_ST2

+3V 4

5 AGP_SBSTBS 4 AGP_ADSTB0# 4 AGP_ADSTB1# AGP_VREF AGPTEST R140 1 47K/NA 2 0402 5% R121 1 10K/NA 2 0402 5% 715 ohm is recommanded for R2SET. GND AGP_VREF

1 1 1 1 1 1 1 1 1 1 R752 DIGON 1 0/NA 0402 2 5% BLON 1 0/NA ENABKL 2 R85 0402 5% 1 R86 10K/NA 0402 5% 2

TXOUT0-_ATI TXOUT0+_ATI TXOUT1-_ATI TXOUT1+_ATI TXOUT2-_ATI TXOUT2+_ATI TXOUT3-_ATI TXOUT3+_ATI TXCLK-_ATI TXCLK+_ATI TP8 TP7 TP6 TP10 TP9 TP11 TP13 TP15 TP12 TP14

LVDS CH1

LVDS CH2

ENAVDD ENABKL

12 12

B

GND

11 ATI_TV_CRMA 11 ATI_TV_LUMA 11 ATI_TV_COMP

GND R84 1 100K/NA 2 0402 5% ATI_CRT_RED ATI_CRT_RED 12 ATI_CRT_GREEN GND ATI_CRT_GREEN 12 ATI_CRT_BLUE ATI_CRT_BLUE 12 ATI_CRT_HSYNC 12 ATI_CRT_VSYNC 12 R764 1 2 0603 499/NA 1% GND GND ATI_CRT_DDDA 12 ATI_CRT_DDCK 12

+3V 1

+3V 1 L711 120Z/100M/NA 2012 R765 8.2K/NA 0402 5% 2 1 C757 1U/NA 0402 +80-20% 10V 1 C755 0.1U/NA 0402 10% 16V 2 2

+3V

REF_OUT 1 1 1 1

R770 1 R773 1

0/NA 2 0402 0/NA 2 0402

TP702

1

AK25 AJ25

+3V 2 1 R771 0/NA 0402 5% U711 1 2 3 4 XIN/CLKIN VDD XOUT REF PD# MODOUT LF VSS 8 7 6 5 X1 X2 2

C123 1000P/NA 0402 +/-20% 50V

C110 10U/NA 0805 6.3V 10%

C128 0.01U/NA 0402 +80-20% 50V 2

C72 0.1U/NA 0402 +80-20% 50V

2

2

2

GND SB_SUSST#

GND GND R772 1 150/NA 2 0402 1% 1 GND 2

REF_OUT OSC_SPREAD R777 180/NA 0603 1%

10K/NA 0402 5%

A

C126 1000P/NA 0402 +/-20% 50V

C122 10U/NA 0805 6.3V 10%

C120 0.01U/NA 0402 +80-20% 50V 2

C131 0.1U/NA 0402 +80-20% 50V

27MHZ/NA C765 TXC8X4.5 22P/NA 0402 +/-10% 50V

C766 22P/NA 0402 +/-10% 50V USE 22P 5%

1

1

1

1

P2779A/NA C770 270P/NA SO8 0402 +/-10% 50V

2

2

A

2

2

GND

GND

GND

GND

GND

+3V 1 1 1

2

2

2

1

GND

C761 47P/NA 0402 +/-10% 25V

C760 47P/NA 0402 +/-10% 25V

C759 47P/NA 0402 +/-10% 25V

R768 75/NA 0402 5% 2

R769 75/NA 0402 5% 2

R767 75/NA 0402 5% Title

2

2

2

2

8050 MOTHER B/D

GND GND Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 7 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

ATI M10-P(2/4)

D

VGA_1.2/1.0

+1.8V AGP_VDDQ U710D L39 1 120Z/100M/NA 2 2012

D

VDD_CORE1.8 1 C167 10U/NA 0805 6.3V 10% C152 0.1U/NA 0402 +80-20% 50V 1 C153 0.1U/NA 0402 +80-20% 50V VDD_PLL1.8 U710E A10 A16 A2 A22 A29 AA30 AB1 AB23 AB24 AB27 AB7 AB8 AC12 AC14 AC16 AC18 AC4 AD12 AD16 AD18 AD25 AD30 AE27 AG11 AG15 AG18 AG22 AG27 AG5 AG9 AJ1 AJ30 AK2 AK29 C1 C28 C3 C30 D12 D15 D18 D21 D24 D27 D4 D6 D9 F27 G12 G16 G18 G21 G24 G9 H12 H14 H16 H18 H21 H23 H27 H4 H8 H9 K1 K23 K24 K27 K30 K7 K8 L4 M16 M30 M7 M8 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 MOBILITY-M10-P/NA BGA644_64_1MM VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS1DI VSS2DI VSSRH0 VSSRH1 TXVSSR_0 TXVSSR_1 TXVSSR_2 LVSSR_0 LVSSR_1 LVSSR_2 LVSSR_3 LPVSS MPVSS PVSS TPVSS VSS_123 A2VSSN_0 A2VSSN_1 A2VSSQ AVSSN AVSSQ N15 N16 N23 N24 N27 P15 P16 P4 R12 R13 R14 R15 R16 R17 R18 R23 R24 R30 R7 R8 T1 T13 T14 T15 T16 T17 T18 T19 T27 U15 U16 U4 U8 V15 V16 V30 W15 W23 W24 W27 W7 W8 Y4 AE23 AE21 F19 M6 AG13 AG14 AH12 AE16 AE19 AF15 AF20 AJ19 A6 AJ28 AJ12 U23 AH22 AJ21 AF23 AH23 AD24 C763 0.1U/NA 0402 +80-20% 50V 1 C764 0.1U/NA 0402 +80-20% 50V VDD_PNLIO1.8 C86 0.1U/NA 0402 +80-20% 50V 1 C124 0.1U/NA 0402 +80-20% 50V VDD_PNLPLL1.8 C746 0.1U/NA 0402 +80-20% 50V 1 C747 0.1U/NA 0402 +80-20% 50V A2VDDQ_1.8 1 2 2 2 2

C743 + 150U/NA 7343 2.5V 2

C88 0.1U/NA 0402 +80-20% 50V

C85 0.01U/NA 0402 +80-20% 50V

C100 C106 1000P/NA 0.01U/NA 0402 0402 +/-20% +80-20% 50V 50V 2 2

C109 0.1U/NA 0402 +80-20% 50V

C82 10U/NA 0805 6.3V 10%

C89 10U/NA 0805 6.3V 10%

C107 0.1U/NA 0402 +80-20% 50V

C91 0.01U/NA 0402 +80-20% 50V 2

C101 1000P/NA 0402 +/-20% 50V

VDD_CORE

GND

1

1

GND VDD_CORE VGA_1.2/1.0 1.8V for M9 , 1.5V for M10

C99 1000P/NA 0402 +/-20% 50V

C117 0.01U/NA 0402 +80-20% 50V

1

C

C111 0.1U/NA 0402 +80-20% 50V

C119 0.1U/NA 0402 +80-20% 50V

C80 0.1U/NA 0402 +80-20% 50V

C83 0.1U/NA 0402 +80-20% 50V

AC13 AC15 AC17 AD13 AD15 M12 M13 M14 M17 M18 M19 N12 N13 N14 N17 N18 N19 P12 P13 P14 P17 P18 P19 U12 U13 U14 U17 U18 U19 V12 V13 V14 V17 V18 V19 W12 W13 W14 W17 W18 W19 AC11 AC20 H11 H20 L23 P8 Y23 Y8 M15 R19 T12 W16 D13 D19 N4 T4 AB4 D10 D25 E4 F18 N6 AE24 AE22 AF13 AF14 AE15 AF21

VDDC_0 VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32 VDDC_33 VDDC_34 VDDC_35 VDDC_36 VDDC_37 VDDC_38 VDDC_39 VDDC_40 VDDC15_0 VDDC15_1 VDDC15_2 VDDC15_3 VDDC15_4 VDDC15_5 VDDC15_6 VDDC15_7 VDDCI_0 VDDCI_1 VDDCI_2 VDDCI_3 VDDR1_53 VDDR1_54 VDDR1_55 VDDR1_56 VSS_119 VSS_120 VSS_121 VSS_122 VDDRH0 VDDRH1 VDD1DI VDD2DI TXVDDR_0 TXVDDR_1 LVDDR_18_0 LVDDR_18_1 LVDDR_25_0 LVDDR_25_1 LPVDD MPVDD PVDD TPVDD A2VDD_0 A2VDD_1 A2VDDQ AVDD MOBILITY-M10-P/NA BGA644_64_1MM

VDD_CORE1.5 1 L28 120Z/100M/NA 2012 2

1

1

C87 1000P/NA 0402 +/-20% 50V

C77 0.01U/NA 0402 +80-20% 50V 2 1

1

R94 1 0805

0/NA 2

C79 10U/NA 0805 6.3V 10%

C97 1000P/NA 0402 +/-20% 50V

C96 0.01U/NA 0402 +80-20% 50V

C113 0.1U/NA 0402 VDD_MEM_IO +80-20% 50V

GND

VDD_MCLK2.5 VDDDI_1.8

B

VDD_PNLIO1.8

VDDP_0 VDDP_1 VDDP_2 VDDP_3 VDDP_4 VDDP_5 VDDP_6 VDDP_7 VDDP_8 VDDP_9 VDDP_10 VDDP_11 VDDP_12 VDDP_13 VDDP_14 VDDP_15 VDDP_16 VDDP_17 VDDP_18 VDDP_19 VDDP_20 VDDR1_0 VDDR1_1 VDDR1_2 VDDR1_3 VDDR1_4 VDDR1_5 VDDR1_6 VDDR1_7 VDDR1_8 VDDR1_9 VDDR1_10 VDDR1_11 VDDR1_12 VDDR1_13 VDDR1_14 VDDR1_15 VDDR1_16 VDDR1_17 VDDR1_18 VDDR1_19 VDDR1_20 VDDR1_21 VDDR1_22 VDDR1_23 VDDR1_24 VDDR1_25 VDDR1_26 VDDR1_27 VDDR1_28 VDDR1_29 VDDR1_30 VDDR1_31 VDDR1_32 VDDR1_33 VDDR1_34 VDDR1_35 VDDR1_36 VDDR1_37 VDDR1_38 VDDR1_39 VDDR1_40 VDDR1_41 VDDR1_42 VDDR1_43 VDDR1_44 VDDR1_45 VDDR1_46 VDDR1_47 VDDR1_48 VDDR1_49 VDDR1_50 VDDR1_51 VDDR1_52 VDDR3_0 VDDR3_1 VDDR3_2 VDDR3_3 VDDR3_4 VDDR3_5 VDDR3_6 VDDR3_7 VDDR4_0 VDDR4_1 VDDR4_2 VDDR4_3 VDDR4_4

AA23 AA24 AB30 AC23 AC27 AE30 AF27 J30 M23 M24 N30 P23 P27 T23 T24 T30 U27 V23 V24 W30 Y27 A15 A21 A28 A3 A9 AA1 AA4 AA7 AA8 AD4 B1 B30 D11 D14 D17 D20 D23 D26 D5 D8 E27 F4 G10 G13 G15 G19 G22 G27 G7 H10 H13 H15 H17 H19 H22 J1 J23 J24 J4 J7 J8 L27 L8 M4 N7 N8 R1 R4 T7 T8 V4 V7 V8 AC19 AC21 AC22 AC8 AD19 AD21 AD22 AD7 AC10 AC9 AD10 AD9 AG7

1

1

1

1

1

1

1

2

1

1

2012

C762 10U/NA 0805 6.3V 10%

2

GND

L29 1

120Z/100M/NA 2 1 2012 C98 10U/NA 0805 6.3V 10% 1 C739 10U/NA 0805 6.3V 10% 1 2 1 2

1

1

1

1

2

2

2

2

1

VDD_MEM_IO 1 1 1 1 L710 1 C758 10U/NA 0805 6.3V 10% L32 1 120Z/100M/NA 2 2012 1

1

1

1

1

C108 1000P/NA 0402 +/-20% 50V

C95 0.01U/NA 0402 +80-20% 50V

C125 0.1U/NA 0402 +80-20% 50V

2

2

2

2

GND

120Z/100M/NA 2 2012 1 C127 10U/NA 0805 6.3V 10% C129 0.1U/NA 0402 +80-20% 50V C130 0.1U/NA 0402 +80-20% 50V

2

2

2

2

2

2

2

1

C114 10U/NA 0805 6.3V 10%

C164 10U/NA 0805 6.3V 10%

C769 0.1U/NA 0402 +80-20% 50V

C132 0.01U/NA 0402 +80-20% 50V 2

C147 1000P/NA 0402 +/-20% 50V

C767 0.1U/NA 0402 +80-20% 50V

1

1

1

1

1

L712 1

120Z/100M/NA 2

2

2

2

2

2

2

2

2

2

C

C81 0.1U/NA 0402 +80-20% 50V

2

2

2

2

2

L34 1

120Z/100M/NA 2 1 1 2012 C138 10U/NA 0805 6.3V 10% C136 0.1U/NA 0402 +80-20% 50V 1 C137 0.01U/NA 0402 +80-20% 50V

2

AVDD_1.8

GND

VDD_MEM_IO 2

2

GND 1 C74 1000P/NA 0402 +/-20% 50V 1 C60 0.01U/NA 0402 +80-20% 50V 2

1

1

2012 C58 0.01U/NA 0402 +80-20% 50V L709 1 120Z/100M/NA 2 1

C141 10U/NA 0805 6.3V 10%

C139 0.1U/NA 0402 +80-20% 50V

1

C90 0.1U/NA C78 0402 10U/NA +80-20% 0805 50V 6.3V 10% 1 2

L35 1

120Z/100M/NA 2 C140 0.1U/NA 0402 +80-20% 50V

2

2

2

VDDDI_1.8

1

1

1

1

2

2

2

2

2

2

2

2

2

1

VDD_MEM_IO

2012

1

1

1

1

C75 0.1U/NA 0402 +80-20% 50V

C76 1000P/NA 0402 +/-20% 50V

C66 0.01U/NA 0402 +80-20% 50V

C118 0.1U/NA 0402 +80-20% 50V

1

C736 10U/NA 0805 6.3V 10%

C738 0.1U/NA 0402 +80-20% 50V

1

GND

VDD_MEMPLL1.8 C737 0.1U/NA 0402 +80-20% 50V

2

2

2

C84 10U/NA 0805 6.3V 10%

GND

+2.5V_M10 L31 1 120Z/100M/NA 2 2012

2

2

2

2

2

B

VDD_DAC2.5 1 C112 10U/NA 0805 6.3V 10% C116 0.1U/NA 0402 +80-20% 50V 1 C115 0.1U/NA 0402 +80-20% 50V 2

+3V GND

2

1

CONNECT LVDDR_25 TO 1.8V FOR M9 VDD_PNLIO2.5 , TO 2.5V FOR M10 VDD_MEMPLL1.8 VDD_PLL1.8 VDD_PNLPLL1.8 VDD_DAC2.5

AE17 AE20 AJ20 A7 AK28 AK12 AG21 AH21 AF22 AH24

2

1

1

R55 0/NA 0805 1 2

C55 10U/NA 0805 6.3V 10%

C44 1000P/NA 0402 +/-20% 50V GND

L30 1

120Z/100M/NA 2 1 1 2012 C92 10U/NA 0805 6.3V 10% C103 0.1U/NA 0402 +80-20% 50V 1 C102 0.1U/NA 0402 +80-20% 50V

2

VDD_PNLIO2.5

2

2

2

VDD_MEM_IO GND L26 1 120Z/100M/NA 2 2012 GND

A2VDDQ_1.8 AVDD_1.8

2

VDD_MCLK2.5 1 C50 10U/NA 0805 6.3V 10% C54 0.1U/NA 0402 +80-20% 50V 1 C105 0.1U/NA 0402 +80-20% 50V 2

2

1

+2.5V_M10 L27 1 L24 1

A

VDD_MEM_IO 120Z/100M/NA 2 2012 120Z/100M/NA 2 2012 GND

+1.5V

A

+1.8V L705 1 120Z/100M/NA 2 2012

L40 1

120Z/100M/NA 2 2012 L33 120Z/100M/NA 2 1 1 C121 10U/NA 0805 6.3V 10% C134 0.1U/NA 0402 +80-20% 50V 1 C135 0.1U/NA 0402 +80-20% 50V

2

AGP_VDDQ

1

2012

VDD_CORE1.5

Title

2

2

2

8050 MOTHER B/D

Size C Document Number PCB 316680900001/ASSY 411680900011 Sheet 8 of 34

1

Rev R01

GND Date:

5 4 3 2

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

U710B MEMA_MD0 MEMA_MD1 MEMA_MD2 MEMA_MD3 MEMA_MD4 MEMA_MD5 MEMA_MD6 MEMA_MD7 MEMA_MD8 MEMA_MD9 MEMA_MD10 MEMA_MD11 MEMA_MD12 MEMA_MD13 MEMA_MD14 MEMA_MD15 MEMA_MD16 MEMA_MD17 MEMA_MD18 MEMA_MD19 MEMA_MD20 MEMA_MD21 MEMA_MD22 MEMA_MD23 MEMA_MD24 MEMA_MD25 MEMA_MD26 MEMA_MD27 MEMA_MD28 MEMA_MD29 MEMA_MD30 MEMA_MD31 MEMA_MD32 MEMA_MD33 MEMA_MD34 MEMA_MD35 MEMA_MD36 MEMA_MD37 MEMA_MD38 MEMA_MD39 MEMA_MD40 MEMA_MD41 MEMA_MD42 MEMA_MD43 MEMA_MD44 MEMA_MD45 MEMA_MD46 MEMA_MD47 MEMA_MD48 MEMA_MD49 MEMA_MD50 MEMA_MD51 MEMA_MD52 MEMA_MD53 MEMA_MD54 MEMA_MD55 MEMA_MD56 MEMA_MD57 MEMA_MD58 MEMA_MD59 MEMA_MD60 MEMA_MD61 MEMA_MD62 MEMA_MD63 L25 L26 K25 K26 J26 H25 H26 G26 G30 D29 D28 E28 E29 G29 G28 F28 G25 F26 E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10 C9 B9 B10 E13 E12 E10 F12 F11 E9 F9 F8 DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQA9 DQA10 DQA11 DQA12 DQA13 DQA14 DQA15 DQA16 DQA17 DQA18 DQA19 DQA20 DQA21 DQA22 DQA23 DQA24 DQA25 DQA26 DQA27 DQA28 DQA29 DQA30 DQA31 DQA32 DQA33 DQA34 DQA35 DQA36 DQA37 DQA38 DQA39 DQA40 DQA41 DQA42 DQA43 DQA44 DQA45 DQA46 DQA47 DQA48 DQA49 DQA50 DQA51 DQA52 DQA53 DQA54 DQA55 DQA56 DQA57 DQA58 DQA59 DQA60 DQA61 DQA62 DQA63 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 RASA# CASA# WEA# CSA0# CSA1# CKEA CLKA0 CLKA0# CLKA1 CLKA1# DIMA_0 DIMA_1 PLLTEST RSTB_MSK VREFG DVOVMODE DMINUS DPLUS DBI_LO DBI_HI MOBILITY-M10-P/NA BGA644_64_1MM U710C MEMB_MD0 MEMB_MD1 MEMB_MD2 MEMB_MD3 MEMB_MD4 MEMB_MD5 MEMB_MD6 MEMB_MD7 MEMB_MD8 MEMB_MD9 MEMB_MD10 MEMB_MD11 MEMB_MD12 MEMB_MD13 MEMB_MD14 MEMB_MD15 MEMB_MD16 MEMB_MD17 MEMB_MD18 MEMB_MD19 MEMB_MD20 MEMB_MD21 MEMB_MD22 MEMB_MD23 MEMB_MD24 MEMB_MD25 MEMB_MD26 MEMB_MD27 MEMB_MD28 MEMB_MD29 MEMB_MD30 MEMB_MD31 MEMB_MD32 MEMB_MD33 MEMB_MD34 MEMB_MD35 MEMB_MD36 MEMB_MD37 MEMB_MD38 MEMB_MD39 MEMB_MD40 MEMB_MD41 MEMB_MD42 MEMB_MD43 MEMB_MD44 MEMB_MD45 MEMB_MD46 MEMB_MD47 MEMB_MD48 MEMB_MD49 MEMB_MD50 MEMB_MD51 MEMB_MD52 MEMB_MD53 MEMB_MD54 MEMB_MD55 MEMB_MD56 MEMB_MD57 MEMB_MD58 MEMB_MD59 MEMB_MD60 MEMB_MD61 MEMB_MD62 MEMB_MD63 D7 F7 E7 G6 G5 F5 E5 C4 B5 C5 A4 B4 C2 D3 D1 D2 G4 H6 H5 J6 K5 K4 L6 L5 G2 F3 H2 E2 F2 J3 F1 H3 U6 U5 U3 V6 W5 W4 Y6 Y5 U2 V2 V1 V3 W3 Y2 Y3 AA2 AA6 AA5 AB6 AB5 AD6 AD5 AE5 AE4 AB2 AB3 AC2 AC3 AD3 AE1 AE2 AE3 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQB9 DQB10 DQB11 DQB12 DQB13 DQB14 DQB15 DQB16 DQB17 DQB18 DQB19 DQB20 DQB21 DQB22 DQB23 DQB24 DQB25 DQB26 DQB27 DQB28 DQB29 DQB30 DQB31 DQB32 DQB33 DQB34 DQB35 DQB36 DQB37 DQB38 DQB39 DQB40 DQB41 DQB42 DQB43 DQB44 DQB45 DQB46 DQB47 DQB48 DQB49 DQB50 DQB51 DQB52 DQB53 DQB54 DQB55 DQB56 DQB57 DQB58 DQB59 DQB60 DQB61 DQB62 DQB63 MOBILITY-M10-P/NA BGA644_64_1MM MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 MAB14 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 RASB# CASB# WEB# CSB0# CSB1# CKEB CLKB0 CLKB0# CLKB1 CLKB1# DIMB_0 DIMB_1 MVREFD MVREFS MEMVMODE0 MEMVMODE1 MEMTEST N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2 E6 B2 J5 G3 W6 W2 AC6 AD2 F6 B3 K6 G1 V5 W1 AC5 AD1 R2 T5 T6 R5 R6 R3 N1 N2 T2 T3 E3 AA3 MEMB_MA0 MEMB_MA1 MEMB_MA2 MEMB_MA3 MEMB_MA4 MEMB_MA5 MEMB_MA6 MEMB_MA7 MEMB_MA8 MEMB_MA9 MEMB_MA10 MEMB_MA11 MEMB_MA12 MEMB_MA13 MEMB_DQM#0 MEMB_DQM#1 MEMB_DQM#2 MEMB_DQM#3 MEMB_DQM#4 MEMB_DQM#5 MEMB_DQM#6 MEMB_DQM#7 MEMB_QSA0 MEMB_QSA1 MEMB_QSA2 MEMB_QSA3 MEMB_QSA4 MEMB_QSA5 MEMB_QSA6 MEMB_QSA7 MEMB_RAS# MEMB_CAS# MEMB_WE# MEMB_CS0# MEMB_CS1# MEMB_CKE R728 1 10/NA 2 0402 5% R727 1 10/NA 2 0402 5% R50 R51 DIMB_0 DIMB_1 5% 1 10/NA 2 0402 5% 1 10/NA 2 0402 R42 1 56/NA 2 0402 5% C41 1 0402 0402 5% 1 4.7K/NA 2 1 4.7K/NA 2 0402 5% E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19 J25 F29 E25 A27 F15 C15 C11 E11 J27 F30 F24 B27 E16 B16 B11 F10 MEMA_MA0 MEMA_MA1 MEMA_MA2 MEMA_MA3 MEMA_MA4 MEMA_MA5 MEMA_MA6 MEMA_MA7 MEMA_MA8 MEMA_MA9 MEMA_MA10 MEMA_MA11 MEMA_MA12 MEMA_MA13 MEMA_DQM#0 MEMA_DQM#1 MEMA_DQM#2 MEMA_DQM#3 MEMA_DQM#4 MEMA_DQM#5 MEMA_DQM#6 MEMA_DQM#7 MEMA_QSA0 MEMA_QSA1 MEMA_QSA2 MEMA_QSA3 MEMA_QSA4 MEMA_QSA5 MEMA_QSA6 MEMA_QSA7

ATI M10-P(3/4)

MEMA_MD0 MEMA_MD1 MEMA_MD2 MEMA_MD3 MEMA_MD4 MEMA_MD5 MEMA_MD6 MEMA_MD7 MEMA_MD8 MEMA_MD9 MEMA_MD10 MEMA_MD11 MEMA_MD12 MEMA_MD13 MEMA_MD14 MEMA_MD15 MEMA_MD16 MEMA_MD17 MEMA_MD18 MEMA_MD19 MEMA_MD20 MEMA_MD21 MEMA_MD22 MEMA_MD23 MEMA_MD24 MEMA_MD25 MEMA_MD26 MEMA_MD27 MEMA_MD28 MEMA_MD29 MEMA_MD30 MEMA_MD31 MEMA_MD32 MEMA_MD33 MEMA_MD34 MEMA_MD35 MEMA_MD36 MEMA_MD37 MEMA_MD38 MEMA_MD39 MEMA_MD40 MEMA_MD41 MEMA_MD42 MEMA_MD43 MEMA_MD44 MEMA_MD45 MEMA_MD46 MEMA_MD47 MEMA_MD48 MEMA_MD49 MEMA_MD50 MEMA_MD51 MEMA_MD52 MEMA_MD53 MEMA_MD54 MEMA_MD55 MEMA_MD56 MEMA_MD57 MEMA_MD58 MEMA_MD59 MEMA_MD60 MEMA_MD61 MEMA_MD62 MEMA_MD63 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RP23 24*4/NA 1206 RP24 24*4/NA 1206 RP18 24*4/NA 1206 RP20 24*4/NA 1206 RP19 24*4/NA 1206 RP17 24*4/NA 1206 RP21 24*4/NA 1206 RP22 24*4/NA 1206 RP706 24*4/NA 1206 RP709 24*4/NA 1206 RP716 24*4/NA 1206 RP713 24*4/NA 1206 RP714 24*4/NA 1206 RP717 24*4/NA 1206 RP708 24*4/NA 1206 RP705 24*4/NA 1206 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 VMDA0 VMDA1 VMDA2 VMDA3 VMDA4 VMDA5 VMDA6 VMDA7 VMDA8 VMDA9 VMDA10 VMDA11 VMDA12 VMDA13 VMDA14 VMDA15 VMDA16 VMDA17 VMDA18 VMDA19 VMDA20 VMDA21 VMDA22 VMDA23 VMDA24 VMDA25 VMDA26 VMDA27 VMDA28 VMDA29 VMDA30 VMDA31 VMDA32 VMDA33 VMDA34 VMDA35 VMDA36 VMDA37 VMDA38 VMDA39 VMDA40 VMDA41 VMDA42 VMDA43 VMDA44 VMDA45 VMDA46 VMDA47 VMDA48 VMDA49 VMDA50 VMDA51 VMDA52 VMDA53 VMDA54 VMDA55 VMDA56 VMDA57 VMDA58 VMDA59 VMDA60 VMDA61 VMDA62 VMDA63

VMDA[0..63]

VMDA[0..63]

10

VDQMA#[0..7] MEMA_DQM#0 MEMA_DQM#1 MEMA_DQM#2 MEMA_DQM#3 MEMA_DQM#4 MEMA_DQM#5 MEMA_DQM#6 MEMA_DQM#7 MEMA_QSA0 MEMA_QSA1 MEMA_QSA2 MEMA_QSA3 MEMA_QSA4 MEMA_QSA5 MEMA_QSA6 MEMA_QSA7 R108 R93 R92 R107 R719 R729 R730 R718 R109 R91 R90 R106 R720 R731 R732 R717 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 VDQMA#0 VDQMA#1 VDQMA#2 VDQMA#3 VDQMA#4 VDQMA#5 VDQMA#6 VDQMA#7 VQSA0 VQSA1 VQSA2 VQSA3 VQSA4 VQSA5 VQSA6 VQSA7

VDQMA#[0..7]

10

VQSA[0..7]

VQSA[0..7]

10

D

D

VMA[0..13] MEMA_MA12 MEMA_MA13 MEMA_MA0 MEMA_MA2 MEMA_MA1 MEMA_MA10 MEMA_MA3 MEMA_MA11 MEMA_MA4 MEMA_MA9 MEMA_MA6 MEMA_MA5 MEMA_MA7 MEMA_MA8 MEMA_CKE 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 RP15 0*8/NA RPX8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 VMA12 VMA13 VMA0 VMA2 VMA1 VMA10 VMA3 VMA11 VMA4 VMA9 VMA6 VMA5 VMA7 VMA8 VCKEA

VMA[0..13]

10

A19 MEMA_RAS# E18 MEMA_CAS# E19 MEMA_WE# E20 MEMA_CS0# F20 MEMA_CS1# B19 MEMA_CKE 5% B21 MEMA_CLK0 R761 1 10/NA 2 0402 5% C20 MEMA_CLK0# R759 1 10/NA 2 0402 5% C18 MEMA_CLK1 R757 1 10/NA 2 0402 5% 2 0402 A18 MEMA_CLK1# R755 1 10/NA DIMA_0 D30 DIMA_1 B13 AE25 AG29 AG4 AE10 AE11 AF11 AB26 AB25 R81 VGA_THERMDC VGA_THERMDA R98 R97 1 0/NA 2 0402 GND R787 1 0/NA 2 5% 0402G_DFS 1 TP17 GND R45 R44 1% 2 0402 1K/NA 1% 2 0402 1 1K/NA 1 +3V GND C751 1 2 470P/NA 0402 50V 10% R760 1 56/NA 2 R758 1 56/NA 2 0402 5% 0402 5% GND

RP14 0*8/NA RPX8

VCKEA

10

VCLKA0 VCLKA#0 VCLKA1 VCLKA#1 R756 1 56/NA 2 R754 1 56/NA 2 0402 5% 0402 5% C742 1 2 470P/NA 0402 50V 10%

VCLKA0 VCLKA#0 VCLKA1 VCLKA#1

10 10 10 10

C

GND

MEMA_CAS# MEMA_RAS# MEMA_CS0# MEMA_WE#

1 2 3 4

RP16 8 0*4/NA 7 1206 6 5

VCASA# VRASA# VCSA#0 VWEA#

VCASA# VRASA# VCSA#0 VWEA#

10 10 10 10

C

DIMA_0 R89 1 DIMA_1 R746 1 MEMA_CS1# R80 1

0/NA 2 0402 0/NA 2 0402 0/NA 2 0402

VDIMA_0 VDIMA_1 VCSA#1

VDIMA_0 VDIMA_1 VCSA#1

10 10 10

VGA_THERMDC 22 VGA_THERMDA 22 AGP_VDDQ

0/NA 2 5% 1 0402G_DFS 0/NA 2 5% 1 0402G_DFS

VMDB[0..63] MEMB_MD0 MEMB_MD1 MEMB_MD2 MEMB_MD3 MEMB_MD4 MEMB_MD5 MEMB_MD6 MEMB_MD7 MEMB_MD8 MEMB_MD9 MEMB_MD10 MEMB_MD11 MEMB_MD12 MEMB_MD13 MEMB_MD14 MEMB_MD15 MEMB_MD16 MEMB_MD17 MEMB_MD18 MEMB_MD19 MEMB_MD20 MEMB_MD21 MEMB_MD22 MEMB_MD23 MEMB_MD24 MEMB_MD25 MEMB_MD26 MEMB_MD27 MEMB_MD28 MEMB_MD29 MEMB_MD30 MEMB_MD31 MEMB_MD32 MEMB_MD33 MEMB_MD34 MEMB_MD35 MEMB_MD36 MEMB_MD37 MEMB_MD38 MEMB_MD39 MEMB_MD40 MEMB_MD41 MEMB_MD42 MEMB_MD43 MEMB_MD44 MEMB_MD45 MEMB_MD46 MEMB_MD47 MEMB_MD48 MEMB_MD49 MEMB_MD50 MEMB_MD51 MEMB_MD52 MEMB_MD53 MEMB_MD54 MEMB_MD55 MEMB_MD56 MEMB_MD57 MEMB_MD58 MEMB_MD59 MEMB_MD60 MEMB_MD61 MEMB_MD62 MEMB_MD63 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RP9 24*4/NA 1206 RP11 24*4/NA 1206 RP4 24*4/NA 1206 RP3 24*4/NA 1206 RP12 24*4/NA 1206 RP13 24*4/NA 1206 RP5 24*4/NA 1206 RP7 24*4/NA 1206 RP707 24*4/NA 1206 RP712 24*4/NA 1206 RP701 24*4/NA 1206 RP702 24*4/NA 1206 RP711 24*4/NA 1206 RP710 24*4/NA 1206 RP703 24*4/NA 1206 RP704 24*4/NA 1206 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 VMDB0 VMDB1 VMDB2 VMDB3 VMDB4 VMDB5 VMDB6 VMDB7 VMDB8 VMDB9 VMDB10 VMDB11 VMDB12 VMDB13 VMDB14 VMDB15 VMDB16 VMDB17 VMDB18 VMDB19 VMDB20 VMDB21 VMDB22 VMDB23 VMDB24 VMDB25 VMDB26 VMDB27 VMDB28 VMDB29 VMDB30 VMDB31 VMDB32 VMDB33 VMDB34 VMDB35 VMDB36 VMDB37 VMDB38 VMDB39 VMDB40 VMDB41 VMDB42 VMDB43 VMDB44 VMDB45 VMDB46 VMDB47 VMDB48 VMDB49 VMDB50 VMDB51 VMDB52 VMDB53 VMDB54 VMDB55 VMDB56 VMDB57 VMDB58 VMDB59 VMDB60 VMDB61 VMDB62 VMDB63

VMDB[0..63]

10

VDQMB#[0..7] MEMB_DQM#0 MEMB_DQM#1 MEMB_DQM#2 MEMB_DQM#3 MEMB_DQM#4 MEMB_DQM#5 MEMB_DQM#6 MEMB_DQM#7 MEMB_QSA0 MEMB_QSA1 MEMB_QSA2 MEMB_QSA3 MEMB_QSA4 MEMB_QSA5 MEMB_QSA6 MEMB_QSA7 R40 R29 R38 R35 R724 R710 R722 R716 R41 R30 R39 R33 R723 R709 R721 R715 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 24/NA 5% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 VDQMB#0 VDQMB#1 VDQMB#2 VDQMB#3 VDQMB#4 VDQMB#5 VDQMB#6 VDQMB#7 VQSB0 VQSB1 VQSB2 VQSB3 VQSB4 VQSB5 VQSB6 VQSB7 VMB[0..13] MEMB_MA12 MEMB_MA13 MEMB_MA0 MEMB_MA2 MEMB_MA1 MEMB_MA10 MEMB_MA3 MEMB_MA11 MEMB_MA4 MEMB_MA9 MEMB_MA6 MEMB_MA5 MEMB_MA7 MEMB_MA8 MEMB_CKE 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 RP8 0*8/NA RPX8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 VMB12 VMB13 VMB0 VMB2 VMB1 VMB10 VMB3 VMB11 VMB4 VMB9 VMB6 VMB5 VMB7 VMB8 VCKEB

VDQMB#[0..7]

10

VQSB[0..7]

VQSB[0..7]

10

B

B

VMB[0..13]

10

RP6 0*8/NA RPX8

C729 1 2 470P/NA 0402 50V 10% R726 1 56/NA 2 R725 1 56/NA 2 0402 5% 0402 5%

GND

VCKEB

10

VCLKB0 VCLKB#0 VCLKB1 VCLKB#1 R43 1 56/NA 2 0402 5% 2 470P/NA 50V 10%

VCLKB0 VCLKB#0 VCLKB1 VCLKB#1

10 10 10 10

MEMB_CAS# MEMB_RAS# MEMB_CS0# MEMB_WE# DIMB_0 DIMB_1 MEMB_CS1#

1 2 3 4

RP10 8 0*4/NA 7 1206 6 5 0/NA 2 0402 0/NA 2 0402 0/NA 2 0402

VCASB# VRASB# VCSB#0 VWEB# VDIMB_0 VDIMB_1 VCSB#1

VCASB# VRASB# VCSB#0 VWEB# VDIMB_0 VDIMB_1 VCSB#1

10 10 10 10 10 10 10

A

R31 1 R711 1 R36 1

A

GND

VDD_MEM_IO

B7 0/NA 2 5% B8 R747 1 0402G_DFS C6 C7 1 C8 1

R69 R74

1 R741 1K/NA 0402 1 R745 VDD_CORE1.8 1K/NA 0402 C735 1 0402 C731 1 10U/NA

R750 47/NA 0402 5% GND 2

R75 4.7K/NA 0402 5% 2 2

R70 4.7K/NA FOR 2.5V VDDR1 0402 MEMVMODE=1.8V 5% MEMVMODE1=GND FOR 1.8V VDDR1(ELPIDA) MEMVMODE=GND MEMVMODE1=1.8V

4

1 R740 2 1K/NA 0402 1% 2 VDD_MEM_IO 1% 1 R736 2 1K/NA 0402 1% 2 1% C732 1 2 0.1U/NA GND 0402 50V +80-20% 2 0.1U/NA GND 50V +80-20% C730 6.3V 6.3V 1 2 10U/NA 0805 10% 2 0805 10%

1

Title

8050 MOTHER B/D

Size C Date: Document Number PCB 316680900001/ASSY 411680900011 Sheet 9 of 34

1

Rev R01

GND

3 2

Monday, December 29, 2003

5

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

VMDA[0..63] VDQMA#[0..7] VQSA[0..7] VMA[0..13]

VMDA[0..63] VDQMA#[0..7] VQSA[0..7] VMA[0..13]

9 9 9 9 U3 M4 M5 L5 M6 M7 L8 M8 M9 M10 M3 L4 L7 K5 L6 A2 G11 G2 A11 L1 K1 K2 M1 L10 L11 M11 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP BA0 BA1 A9 A10 A11 DQM0 DQM1 DQM2 DQM3 RAS CAS WE CS CK CK# CKE VREF MCL NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 VSS/TH1 VSS/TH2 VSS/TH3 VSS/TH4 VSS/TH5 VSS/TH6 VSS/TH7 VSS/TH8 VSS/TH9 VSS/TH10 VSS/TH11 VSS/TH12 VSS/TH13 VSS/TH14 VSS/TH15 VSS/TH16 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 VSSQ_10 VSSQ_11 VSSQ_12 VSSQ_13 VSSQ_14 VSSQ_15 VSSQ_16 VSSQ_17 VSSQ_18 VSSQ_19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS0 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS1 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS3 A12/RFU1 BA2/RFU2 A6 B5 A5 A4 B1 C2 C1 D1 A1 J12 J11 H12 H11 F12 F11 E12 E11 G12 E2 E1 F2 F1 H2 H1 J1 J2 G1 D12 C12 C11 B12 A9 A8 B8 A7 A12 K8 L9 U709 M4 M5 L5 M6 M7 L8 M8 M9 M10 M3 L4 L7 K5 L6 A2 G11 G2 A11 L1 K1 K2 M1 L10 L11 M11 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP BA0 BA1 A9 A10 A11 DQM0 DQM1 DQM2 DQM3 RAS CAS WE CS CK CK# CKE VREF MCL NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 VSS/TH1 VSS/TH2 VSS/TH3 VSS/TH4 VSS/TH5 VSS/TH6 VSS/TH7 VSS/TH8 VSS/TH9 VSS/TH10 VSS/TH11 VSS/TH12 VSS/TH13 VSS/TH14 VSS/TH15 VSS/TH16 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 VSSQ_10 VSSQ_11 VSSQ_12 VSSQ_13 VSSQ_14 VSSQ_15 VSSQ_16 VSSQ_17 VSSQ_18 VSSQ_19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS0 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS1 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS3 A12/RFU1 BA2/RFU2 A6 B5 A5 A4 B1 C2 C1 D1 A1 J12 J11 H12 H11 F12 F11 E12 E11 G12 E2 E1 F2 F1 H2 H1 J1 J2 G1 D12 C12 C11 B12 A9 A8 B8 A7 A12 K8 L9 U1 M4 M5 L5 M6 M7 L8 M8 M9 M10 M3 L4 L7 K5 L6 A2 G11 G2 A11 L1 K1 K2 M1 L10 L11 M11 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP BA0 BA1 A9 A10 A11 DQM0 DQM1 DQM2 DQM3 RAS CAS WE CS CK CK# CKE VREF MCL NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 VSS/TH1 VSS/TH2 VSS/TH3 VSS/TH4 VSS/TH5 VSS/TH6 VSS/TH7 VSS/TH8 VSS/TH9 VSS/TH10 VSS/TH11 VSS/TH12 VSS/TH13 VSS/TH14 VSS/TH15 VSS/TH16 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 VSSQ_10 VSSQ_11 VSSQ_12 VSSQ_13 VSSQ_14 VSSQ_15 VSSQ_16 VSSQ_17 VSSQ_18 VSSQ_19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS0 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS1 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS3 A12/RFU1 BA2/RFU2

VRAM

VMDA0 VMDA1 VMDA2 VMDA3 VMDA4 VMDA5 VMDA6 VMDA7 VQSA0 VMDA8 VMDA9 VMDA10 VMDA11 VMDA12 VMDA13 VMDA14 VMDA15 VQSA1 VMDA16 VMDA17 VMDA18 VMDA19 VMDA20 VMDA21 VMDA22 VMDA23 VQSA2 VMDA24 VMDA25 VMDA26 VMDA27 VMDA28 VMDA29 VMDA30 VMDA31 VQSA3 VMA0 VMA1 VMA2 VMA3 VMA4 VMA5 VMA6 VMA7 VMA8 VMA12 VMA13 VMA9 VMA10 VMA11 VDQMA#4 VDQMA#5 VDQMA#6 VDQMA#7 VRASA# VCASA# VWEA# VCSA#0 VCLKA1 VCLKA#1 VCKEA VMDA32 VMDA33 VMDA34 VMDA35 VMDA36 VMDA37 VMDA38 VMDA39 VQSA4 VMDA40 VMDA41 VMDA42 VMDA43 VMDA44 VMDA45 VMDA46 VMDA47 VQSA5 VMDA48 VMDA49 VMDA50 VMDA51 VMDA52 VMDA53 VMDA54 VMDA55 VQSA6 VMDA56 VMDA57 VMDA58 VMDA59 VMDA60 VMDA61 VMDA62 VMDA63 VQSA7 VMB0 VMB1 VMB2 VMB3 VMB4 VMB5 VMB6 VMB7 VMB8 VMB12 VMB13 VMB9 VMB10 VMB11 VDQMB#0 VDQMB#1 VDQMB#2 VDQMB#3 VRASB# VCASB# VWEB# VCSB#0 VCLKB0 VCLKB#0 VCKEB

VMDB[0..63] VDQMB#[0..7] VQSB[0..7] VMB[0..13]

VMDB[0..63] VDQMB#[0..7] VQSB[0..7] VMB[0..13]

9 9 9 9 VMB0 VMB1 VMB2 VMB3 VMB4 VMB5 VMB6 VMB7 VMB8 VMB12 VMB13 VMB9 VMB10 VMB11 VDQMB#4 VDQMB#5 VDQMB#6 VDQMB#7 VRASB# VCASB# VWEB# VCSB#0 VCLKB1 VCLKB#1 VCKEB U708 M4 M5 L5 M6 M7 L8 M8 M9 M10 M3 L4 L7 K5 L6 A2 G11 G2 A11 L1 K1 K2 M1 L10 L11 M11 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP BA0 BA1 A9 A10 A11 DQM0 DQM1 DQM2 DQM3 RAS CAS WE CS CK CK# CKE VREF MCL NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 VSS/TH1 VSS/TH2 VSS/TH3 VSS/TH4 VSS/TH5 VSS/TH6 VSS/TH7 VSS/TH8 VSS/TH9 VSS/TH10 VSS/TH11 VSS/TH12 VSS/TH13 VSS/TH14 VSS/TH15 VSS/TH16 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 VSSQ_10 VSSQ_11 VSSQ_12 VSSQ_13 VSSQ_14 VSSQ_15 VSSQ_16 VSSQ_17 VSSQ_18 VSSQ_19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS0 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS1 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS3 A12/RFU1 BA2/RFU2 A6 B5 A5 A4 B1 C2 C1 D1 A1 J12 J11 H12 H11 F12 F11 E12 E11 G12 E2 E1 F2 F1 H2 H1 J1 J2 G1 D12 C12 C11 B12 A9 A8 B8 A7 A12 K8 L9

C

D

9 9 9 9 9 9 9

VRASA# VCASA# VWEA# VCSA#0 VCLKA0 VCLKA#0 VCKEA

VMA0 VMA1 VMA2 VMA3 VMA4 VMA5 VMA6 VMA7 VMA8 VMA12 VMA13 VMA9 VMA10 VMA11 VDQMA#0 VDQMA#1 VDQMA#2 VDQMA#3 VRASA# VCASA# VWEA# VCSA#0 VCLKA0 VCLKA#0 VCKEA

A6 B5 A5 A4 B1 C2 C1 D1 A1 J12 J11 H12 H11 F12 F11 E12 E11 G12 E2 E1 F2 F1 H2 H1 J1 J2 G1 D12 C12 C11 B12 A9 A8 B8 A7 A12 K8 L9

VMDB0 VMDB1 VMDB2 VMDB3 VMDB4 VMDB5 VMDB6 VMDB7 VQSB0 VMDB8 VMDB9 VMDB10 VMDB11 VMDB12 VMDB13 VMDB14 VMDB15 VQSB1 VMDB16 VMDB17 VMDB18 VMDB19 VMDB20 VMDB21 VMDB22 VMDB23 VQSB2 VMDB24 VMDB25 VMDB26 VMDB27 VMDB28 VMDB29 VMDB30 VMDB31 VQSB3

VMDB32 VMDB33 VMDB34 VMDB35 VMDB36 VMDB37 VMDB38 VMDB39 VQSB4 VMDB40 VMDB41 VMDB42 VMDB43 VMDB44 VMDB45 VMDB46 VMDB47 VQSB5 VMDB48 VMDB49 VMDB50 VMDB51 VMDB52 VMDB53 VMDB54 VMDB55 VQSB6 VMDB56 VMDB57 VMDB58 VMDB59 VMDB60 VMDB61 VMDB62 VMDB63 VQSB7

D

9 9 9 9 9 9 9

VRASA# VCASA# VWEA# VCSA#0 VCLKA1 VCLKA#1 VCKEA1

9 9 9 9 9 9 9

VRASB# VCASB# VWEB# VCSB#0 VCLKB0 VCLKB#0 VCKEB

9 9 9 9 9 9 9

VRASB# VCASB# VWEB# VCSB#0 VCLKB1 VCLKB#1 VCKEB

9

VDD_MEM_IOREF M12 L12 M2 B3 GND B10 G3 G10 K11 9 VDIMA_0 K12 L2 VCSA#1 L3 VCSA#1 G7 G8 H5 H6 H7 H8 G5 G6 E5 E6 E7 E8 F5 F6 F7 F8 D6 D7 D9 J5 J6 J7 J8 K4 K9 D4 C8 C9 C10 D5 D8 E4 E9 F4 F9 G4 G9 H4 H9 J4 J9 A3 C3 C4 C5 A10

9 9

VDD_MEM_IOREF M12 L12 M2 B3 GND B10 G3 G10 K11 VDIMA_1 K12 L2 VCSA#1 L3 VCSA#1 G7 G8 H5 H6 H7 H8 G5 G6 E5 E6 E7 E8 F5 F6 F7 F8 D6 D7 D9 J5 J6 J7 J8 K4 K9 D4 C8 C9 C10 D5 D8 E4 E9 F4 F9 G4 G9 H4 H9 J4 J9 A3 C3 C4 C5 A10

9 9

VDD_MEM_IOREF M12 L12 M2 B3 GND B10 G3 G10 K11 VDIMB_0 K12 L2 VCSB#1 L3 VCSB#1 G7 G8 H5 H6 H7 H8 G5 G6 E5 E6 E7 E8 F5 F6 F7 F8 D6 D7 D9 J5 J6 J7 J8 K4 K9 D4 C8 C9 C10 D5 D8 E4 E9 F4 F9 G4 G9 H4 H9 J4 J9 A3 C3 C4 C5 A10

9 9

VDD_MEM_IOREF M12 L12 M2 B3 GND B10 G3 G10 K11 VDIMB_1 K12 L2 VCSB#1 L3 VCSB#1 G7 G8 H5 H6 H7 H8 G5 G6 E5 E6 E7 E8 F5 F6 F7 F8 D6 D7 D9 J5 J6 J7 J8 K4 K9 D4 C8 C9 C10 D5 D8 E4 E9 F4 F9 G4 G9 H4 H9 J4 J9 A3 C3 C4 C5 A10

C

+2.5V_M10 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 C6 C7 D3 D10 K3 K6 K7 K10 VDD_MEM_IO B2 B4 B6 B7 B9 B11 D2 D11 E3 E10 F3 F10 H3 H10 J3 J10

+2.5V_M10 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 C6 C7 D3 D10 K3 K6 K7 K10 VDD_MEM_IO B2 B4 B6 B7 B9 B11 D2 D11 E3 E10 F3 F10 H3 H10 J3 J10

+2.5V_M10 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 C6 C7 D3 D10 K3 K6 K7 K10 VDD_MEM_IO B2 B4 B6 B7 B9 B11 D2 D11 E3 E10 F3 F10 H3 H10 J3 J10

+2.5V_M10 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 C6 C7 D3 D10 K3 K6 K7 K10 VDD_MEM_IO B2 B4 B6 B7 B9 B11 D2 D11 E3 E10 F3 F10 H3 H10 J3 J10

B

B

GND

HY5DU2832222F/NA BGA144F_08MM_1

GND

HY5DU2832222F/NA BGA144F_08MM_1

GND

HY5DU2832222F/NA BGA144F_08MM_1

GND

HY5DU2832222F/NA BGA144F_08MM_1

+2.5V_M10

+2.5V_M10

+2.5V_M10

+2.5V_M10

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

C750 10U/NA 0805 6.3V 10%

C753 1U/NA 0402 +80-20% 10V

C744 0.1U/NA 0402 10% 16V

C745 0.01U/NA 0402 +80-20% 50V

C59 10U/NA 0805 6.3V 10%

C62 1U/NA 0402 +80-20% 10V

C45 0.1U/NA 0402 10% 16V

C47 0.01U/NA 0402 +80-20% 50V

C724 10U/NA 0805 6.3V 10%

C723 1U/NA 0402 +80-20% 10V

C720 0.1U/NA 0402 10% 16V

C727 0.01U/NA 0402 +80-20% 50V

C32 10U/NA 0805 6.3V 10%

C28 1U/NA 0402 +80-20% 10V

C36 0.1U/NA 0402 10% 16V

1 C33 0.01U/NA 0402 +80-20% 50V GND 1 2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

GND VDD_MEM_IO VDD_MEM_IO

GND VDD_MEM_IO

GND VDD_MEM_IO

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

C756 10U/NA 0805 6.3V 10%

C748 1U/NA 0402 +80-20% 10V

C754 0.1U/NA 0402 10% 16V

C752 0.1U/NA 0402 10% 16V

C749 0.01U/NA 0402 +80-20% 50V

C49 10U/NA 0805 6.3V 10%

C48 1U/NA 0402 +80-20% 10V

C63 0.1U/NA 0402 10% 16V

C46 0.1U/NA 0402 10% 16V

C51 0.01U/NA 0402 +80-20% 50V

C716 10U/NA 0805 6.3V 10%

C721 1U/NA 0402 +80-20% 10V

C718 0.1U/NA 0402 10% 16V

C725 0.1U/NA 0402 10% 16V

C726 0.01U/NA 0402 +80-20% 50V

C37 10U/NA 0805 6.3V 10%

C30 1U/NA 0402 +80-20% 10V

C35 0.1U/NA 0402 10% 16V

C29 0.1U/NA 0402 10% 16V

1 C34 0.01U/NA 0402 +80-20% 50V GND 2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

GND VDD_MEM_IO 1

A

GND VDD_MEM_IO 1 VDD_MEM_IO 1

GND VDD_MEM_IO 1

2

A

R751 1K/NA 0402 1% VDD_MEM_IOREF 1 1 R753 1K/NA 0402 1% 2 2 2 1 1

R65 1K/NA 0402 1% VDD_MEM_IOREF 1 1 R60 1K/NA 0402 1% 2 2 1

R713 1K/NA 0402 1% VDD_MEM_IOREF 1 1 R712 1K/NA 0402 1% 2 1 2

R34 1K/NA 0402 1% VDD_MEM_IOREF 1 R32 1K/NA 0402 1% 2 1 C27 0.1U/NA 0402 10% 16V C25 10U/NA 0805 6.3V 10%

C741 0.1U/NA 0402 10% 16V

C740 10U/NA 0805 6.3V 10%

C65 0.1U/NA 0402 10% 16V

C57 10U/NA 0805 6.3V 10%

C719 0.1U/NA 0402 10% 16V

C722 10U/NA 0805 6.3V 10%

Title

2

2

2

2

2

2

2

2

8050 MOTHER B/D

Size C Date: Document Number PCB 316680900001/ASSY 411680900011 Sheet 10 of 34

1

GND

5

GND

4 3

GND

2

GND

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

FS2 X

FS1 0 0 1 1 0 0 1 1

FS0 0 1 0 1 0 1 0 1

CPU 166.66 100.00 200.00 133.33 Tristate TCLK/2 Reserved Reserved

3V66[5:0] 66.66 66.66 66.66 66.66 Tristate TCLK/2 Reserved Reserved

PCI* 33.33 33.33 33.33 33.33 Tristate TCLK/2

CLOCK SYNTHERIZER

Layout note: Place crystal within 500 mils of CLK Gen.

U712 2 X703 1 1 2 1 14.318MHZ TXC8X4.5 2 2 C794 27P 0402 5% 6,14 SMBDATA 6,14 SMBCLK FS0 FS1 FS2 3 29 30 54 55 40 C804 27P 0402 5% X1 X2 3V66_1/VCH_CLK SDATA SCLK FS0 FS1 FS2 *PD# PCI_STOP# CPU_STOP#* MULTSEL0* VTT_PWRGD# VDDREF VDD48 VDDA VDD3V66_0 VDD3V66_1 VDDCPU0 VDDCPU1 VDDPCI0 VDDPCI1 GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 ICS950810 TSSOP56 284595081201 REF CPUCLKT0 CPUCLKT1 CPUCLKT2 CPUCLKC0 CPUCLKC1 CPUCLKC2 PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK_F0 PCICLK_F1 PCICLK_F2 66MHZ_OUT0/3V66_2 66MHZ_OUT1/3V66_3 66MHZ_OUT2/3V66_4 3V66_0 66MHZ_IN/3V66_5 IREF 48MHZ_USB 48MHZ_DOT 39 38 35 56 52 49 45 51 48 44 10 11 12 13 16 17 18 5 6 7 21 22 23 33 24 2 42 1 R876 2 GND 390 0402 1% GND 1 R895 2 33 R877 2 33 R878 2 33 DEFSSCLK R859 1 1 R858 33 R861 33/NA 1 R872 33 1 R874 33 1 R862 33/NA 1 R873 33 1 R875 33 1 R825 33 1 R816 33 1 R826 33 1 R827 33 1 PCICK_1394 PCICK_KBC 33 0402 5% 1 0402 5% 1 0402 5% 1 C825 1 10P/NA 2 0402 5% 2 0402 5% 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 2 2 2 2 0402 0402 0402 0402 C796 10P 0402 +/-10% 50V C789 10P 0402 +/-10% 50V C797 10P 0402 +/-10% 50V C790 10P 0402 +/-10% 50V 1 1 1 1 2 0402 50V +/-10% GND 1 C834 1 10P/NA C833 1 10P/NA C830 1 10P/NA 2 0402 50V +/-10% 2 0402 50V +/-10% 2 0402 50V +/-10%

ITP_CPU# HCLK_CPU# HCLK_MCH# ITP_CPU HCLK_CPU HCLK_MCH

R871 R893 R891 R870 R892 R890

1 1 1 1 1 1

2 49.9/NA 0402 2 49.9 0402 1% 2 49.9 0402 1% 2 49.9/NA 0402 2 49.9 0402 1% 2 49.9 0402 1% GND

001

X X X Mid Mid

GND SIO_48M 19 USBCLK_ICH 14 48M_DREFCLK 4 14M_CODEC 14M_ICH 5% 20 13 2 +3V L43 1 2 120Z/100M 1 1608 1 1 +3VCLKCPU

D

D

Mid Mid 0:0V 1:3.3V

Reserved Reserved UNIT: MHz

+3V GND +3V 1 1 1 R864 4.7K/NA 0402 5% FS0 FS1 FS2 2 2 R853 4.7K/NA 0402 5% 2 R860 4.7K 0402 5%

1

1

1

2

2

2

+3VCLK66 R869 4.7K/NA 0402 5% +3VCLKCPU +3VCLKPCI

1

1

1

GND +3V

GND +3VCLK66 L726 1 2 120Z/100M 1 1608 1 1 C822 0.1U 0402 10% 16V C823 2.2U 0603 +/-10% GND +3VCLKANA

C

R894 4.7K 0402 5% 2 2

R848 4.7K 0402 5% 2

2

2

2

46 50 8 14 4 9 15 20 27 31 36 41 47 GND

R824 33

1

2 0402 2 0402 2 0402 2 0402

GND

2

PCICLK_ICH 66M_MCH 66M_ICH 66M_AGP

13 1 4 14 7

R829 33 1 R818 33 1 R819 33/NA 1

1

1

1

1

1

GND

+3V

C

R831 10K 0402 5% 2 31 CORE_CLKEN# 1 R821 0 2 0402 VTT_PWRGD# 5%

C793 10P/NA 0402 +/-10% 50V

C792 10P/NA 0402 +/-10% 50V

C799 10P/NA 0402 +/-10% 50V

C795 10P 0402 +/-10% 50V

C827 0.1U 0402 10% 16V

C802 0.1U 0402 10% 16V

2

2

2

GND +3V L722 1 2 120Z/100M 1 1608 1

2

2

2

2

2

+3VCLKANA

1 37 26 19 32

C778 0.1U 0402 10% 16V

C801 0.1U 0402 10% 16V

C800 0.1U 0402 10% 16V

1 C788 2.2U 0603 +/-10% 1

0402 CLK_PD# 1 R830 2 8.2K/NA 25 CLK_PCI_STOP# 34 1 R882 2 8.2K/NA CLK_CPU_STOP# 0402 2 8.2K/NA 1 53 R886 0402 1 R863 2 8.2K 0402 43 +3V VTT_PWRGD# 28 5%

ITP_CPU 1 R888 2 0402 HCLK_MCH 0/NA HCLK_CPU ITP_CPU# 1 HCLK_MCH# HCLK_CPU# R889 2 0402 0/NA

CLK_ITP_CPU 2 HCLK_MCH 4 HCLK_CPU 2 CLK_ITP_CPU# 2 HCLK_MCH# 4 HCLK_CPU# 2 PCICLK_FWH 23 PCICLK_MINIPCI 19 PCICLK_CARD 17 PCICLK_LAN 16

C262 0.1U 0402 10% 16V

C820 0.1U 0402 10% 16V

C819 0.1U 0402 10% 16V

C239 2.2U 0603 +/-10%

2

2

GND +3V L718 1 2 120Z/100M 1608

GND +3VCLKPCI

5%

2

DEFSSCLK

R865 1

33 33 33

2 0402 2 0402 2 0402 C826 10P/NA 0402 +/-10% 50V C798 10P 0402 +/-10% 50V C791 10P 0402 +/-10% 50V 1 1 1

66M_DEFSSCLK 4 2 PCICLK_1394 PCICLK_KBC 18 22

PCICK_1394 R828 1 PCICK_KBC 13 SUSA# 3,13,31 STOP_CPU# 13 STOP_PCI# 1 R820 0 1 R887 0/NA 1 R881 0 2 0402 2 0402 2 0402 CLK_PD# 5% R817 1

C812 0.1U 0402 10% 16V

C821 0.1U 0402 10% 16V

C803 0.1U 0402 10% 16V

C809 0.1U 0402 10% 16V

1 C811 2.2U 0603 +/-10% GND 2

2

2

GND

WHEN USE INTEGRATE VGA R887/NA

CLK_CPU_STOP# 5% CLK_PCI_STOP# 5% GND 2

2

GND

GND

+3V

+3V 2 +3V R807 10K 0402 5% TV_DDCK 855_TV_COMP CVBS1 1 1 4 DVOVREF 4 DVOCCLK 4 DVOCCLK# 4 DVOCHSYNC XIN 4 DVOCVSYNC R52 0402 1 1M/NA 2 5% X701 1 2 14.318MHZ TXC8X4.5 +3V 1 GND 2 1 1 XOUT 33 18 44 1 12 49 +3VA_TV +3V 2

1

TV ENCODER

DVOVREF G U2 3 57 56 4 5 855_TV_CRMA 38 855_TV_LUMA 37 855_TV_COMP39 CVBS1 36 TV_DDCK TV_DDDA XIN XOUT 15 14 42 43 46 13 48 10 35 47 VREF XCLK XCLK* H V C/R Y/G CVBS/B CVBS SPC SPD XI/FIN XO P-OUT RESET* C/HSYNC AS ISET BCO

2

+1.5V

R63 0 0805

45

1

DVOCD[0..11] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] GPIO[0] GPIO[1] NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 63 62 61 60 59 58 55 54 53 52 51 50 8 7 2 9 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DVOCD0 DVOCD1 DVOCD2 DVOCD3 DVOCD4 DVOCD5 DVOCD6 DVOCD7 DVOCD8 DVOCD9 DVOCD10 DVOCD11 R56 1 0/NA 0402 5% C64 0.1U 0402 +80-20% 50V 1 2 GND

B

C67 0.1U 0402 +80-20% 50V

AVDD_0 AVDD_1

DVDD_0 DVDD_1 DVDD_2

4 MI2CCLK

S D S

D Q702 2N7002 SOT23_FET 288227002006 +3V

DVDDV

Place near to 7011.

1

VDD

DVOCD[0..11]

2 4

B

2

+3V +3V 1 1 R68 8.2K 0402 5% 2 DVOBCINTR# 4 1 R71 330/NA 0402 5% 2 GND GND

GND +3V

+3V 2

R48 75/NA 0402 5% 2

R46 75 0402 5%

2

R53 8.2K/NA 0402 5% 2 1 C53 0.1U 0402 +80-20% 50V GND 2 1 R54 330 0402 5% 2 2

R935 G 1 2 D719 TV_GND BAV99/NA D3 TV_GND BAV99/NA 3 3 3 10K 0402 5% TV_DDDA 2 1 2 1

GND

GND USE 20P 5%

TV_GND D4 BAV99/NA

4 MI2CDATA

S D S

D Q712 2N7002 SOT23_FET 288227002006

C52 20P 0402 +/-10% 50V

C56 20P 0402 +/-10% 50V

1

WHEN USE INTEGRATE VGA ADD R763 R766 U2 R1240

2

J704 1 2 3 4 5 6 7 GND1 GND2 1 2 3 4 5 6 7 GND1 GND2

C344 1 0402 L56 1 C17 1 0402 1 1 C19 1 0402 1 1 1

L19 L20

4 3 2 1

2 33P 25V +/-10% 2 120Z/100M 2 33P 25V +/-10% 2 120Z/100M 2 120Z/100M 2 33P 25V +/-10% 1 1

GND 4 POUT/DET# R47 8.2K/NA 13 TV_PCIRST# 0402 5% GND 4 R49 330 0402 5% R37 1 140 2 R73 1 0/NA 2 DVOCFLDSTL 0402 5%

Default NTSC

ATI_TV_COMP 7 1 0 0 0 1 R1240 1 R763 1 R766 2 0402855_TV_COMP ATI_TV_LUMA 7 2 0402855_TV_LUMA 2 0402855_TV_CRMA 2 ATI_TV_CRMA 7

2

DGND_0 DGND_1 DGND_2 6 11 64

AGND_0 AGND_1 AGND_2

GND_0 GND_1

CH7011A PQFP64_0.5MM

34 40

GND RP2 75*4 1206 +3V +3V L25 +3V 1 1 1 1 1 C38 10U 6.3V 0805 10% GND 2 2 C70 0.1U 0402 +80-20% 50V C43 0.1U 0402 +80-20% 50V C71 0.1U 0402 +80-20% 50V C42 0.1U 0402 +80-20% 50V GND 1 C73 10U 6.3V 0805 10% 1 120Z/100M 2 2012 1 1 C39 10U 6.3V 0805 10% GND 2 2 C40 0.1U 0402 +80-20% 50V 1 C61 0.1U 0402 +80-20% 50V +3VA_TV GND

A

A

7P/RA SUYIN 33007S-07T1-C 331870007007 TV_GND

C782 270P 0402 +/-10% 50V

C15 270P 0402 +/-10% 50V

C21 270P 0402 +/-10% 50V

2

2

2

2

1 0

2

2

R704

C20 100P 0402 10% 50V

C18 100P 0402 10% 50V 5 6 7 8

GND

GND

2

2

2

2

16 17 41

2

Title

8050 MOTHER B/D

Size C Date: Document Number PCB 316680900001/ASSY 411680900011 Sheet 11 of 34

1

Rev R01

Monday, December 29, 2003

5

4

3

2

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

Display (CRT / LCD)

1 1 2 2 DVMAIN +5V_H

D

Pannel ID

LCD_ID0 0 LCD_ID1 0 0 1 1 1 LCD_ID2 1 1 1 0 0 PANEL TYPE 1

C339 0.01U 0402 +80-20% 50V L17 1 2 2012 120Z/100M L8 1

C340 1000P 0402 +/-20% 50V

4,22 BLADJ

BLADJ 0

Inverter

ENABKL_VGA_C 1 R5 2 0402 1

L10 1 L9 1 1608

2 120Z/100M/NA 2 120Z/100M 2 1608 120Z/100M

C8 0.1U/NA 0402 +80-20% 50V 2012

C7 GND 0.1U 0402 +80-20% 50V

INVERTER

J1 1 2 3 4 5 6 7 8 9 10 11 GND1 GND2 MA/11PX1/RA ACES 87213-1100 +5V_H 2 +3V 2 +3VS

1

2

2

1

0 0 1

1 2 R398 10K/NA 0402 5% R365 0/NA 0402 5% 1 1 R370 0/NA 0402 5% 4 +5V_H G 2 FPVDEN FPVEDEN R22 1 0 0402 5% 2

C6 4.7U/NA 0805 +80-20% FA2 8 7 6 5 1 120Z/100M 2012 120OHM/100MHZ 273000610025 1 2 3 4 2 1 C12 0.1U 0402 +80-20% 50V

R16 1M 2 0402 5%

F1 1 2 +3V 2A FUSE_1206 1 2 3 Q9 SI4835DY SO8

D

GND 22,23 BATT_R# 22,23 BATT_G# 22,23 AC_POWER# 23 BATT_POWER# BATT_R# BATT_G# AC_POWER# BATT_POWER# VDD3S L18

2

1

2

R4 10K/NA 0402 5% ENABKL_VGA_C

7

ENAVDD

R20 1 0/NA 0402 5%

2 S D S GND D R19 1 10K 0402 5% 2 1 4 G

R399 20K/NA 0402 1% ENABKL_VGA 1 R1

1 Q4

3

2N7002 SOT23_FET

2

2

1

GND

DTC144TKA/NA 288202240001 R323

2

GND

2 0402 0

1 5%

C11 1U 0402 +80-20% 10V J2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 GND1 GND2 MA/15PX2/ST ACES 88107-300X 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

L15 1 120Z/100M 2012 2

GND R383 22 H8_ENABKL H8_ENABKL 1 0 0402 5% R380 10K 0402 5% 1 +3V 2 BAT54 R372 10K 0402 5% 3 BAT54 22 H8_LIDSW# D15 1 GND GND 0/NA 0402 5% H8_LIDSW# 1 1K 0402 C385 0.1U 0402 +80-20% 50V 5% 30V/0.1A DT006-P11AA-A GND 2

D2

C

2

WHEN USE INTEGRATE VGA ADD R384 DEL R386

4 ENABKL_NB 7 ENABKL R384 1 0402 R386 1 0402 0 5% 0/NA 2 5% BAT54 2 3 1 ENABKL_VGA

When inverter use +5V ADD Q4,R398,R399,R4 and DEL R323

+3VS +3V

2

5 6 7 8

PANEL_ID2 PANEL_ID1 PANEL_ID0 TXOUT1+ TXOUT1TXOUT0+ TXOUT0-

+3V

Cover Switch

D1 1 R2 470K/NA 0402 R3 5% 1 ESD0805A/NA 2

When inverter use +3V ADD R323 and DEL Q4,R398,R399,R4

7,14,24 PANEL_ID3 4 TXCLK+ 4 TXCLK4 TXOUT3+ 4 TXOUT34 TXOUT2+ 4 TXOUT2-

1

1

1

D16 3 1

R379 2 2

R373 470K 0402 5% 2

SW1 2 1 2 3 4

4,13,17,25,31 PWROK

1

2

Check Power Plane is 3VS or 5VS

R1 1 0 0805 CHAGND R703 1 0 0805 CHAGND GND CHAGND 7 8 L13 1 1 2 BEAD_600Z/100M 0603D L7 5 6 7 8 CP2 CHAGND CON_DDCK 15 5 10 14 4 9 13 3 8 12 2 7 11 1 6 16 D701

A

2 D702 1 GND 3 2 5 6 4 2N7002 D D S Q5 S R138 1 0/NA 2 0402 ATI_CRT_DDDA 7 855_CRT_DDDA 4 CHAGND 2 L12 1 2 120Z/100M 1608 G 2N7002 D D S Q6 S R785 1 0/NA 2 0402 855_CRT_DDCK 4 ATI_CRT_DDCK 7 U702 CON_DDDA 1 2 3 SMS05C/NA SSOT6

B

G

CRT

+5V_H

R6 1 0402 R10 1 0402

4.7K 2 5% 4.7K 2 5%

+5V_H

B

+5V_H G 1 S D S Q7 S Q8 47PX4 1206 D S R137 1 0/NA 2 0402 ATI_CRT_HSYNC 7 855_CRT_HSYNC 4 R136 1 0/NA 2 0402 855_CRT_VSYNC 4 ATI_CRT_VSYNC 7 2

ESD41A/NA R9 1 0402 1K 5% 2

CRT_IN#

13,24 L11 1

2 120Z/100M 1608

2N7002 D G

1

R8 0/NA 2 0402 5% 2

C10 100P 0402 +/-10% 50V

1

2 120Z/100M 1608

2N7002 D

J702 17

CON_VSYNC 4 3 2 1 CON_HSYNC CON_DDDA CON_BLUE CON_GREEN CHAGND CRT_BLUE

WHEN USE INTEGRATE VGA DEL R785 R138 R136 R137 R139 R135 R783

R139 R135 R783 1 0/NA 1 0/NA 1 0/NA 2 0402 2 0402 2 0402 855_CRT_BLUE 4 ATI_CRT_BLUE 7 ATI_CRT_GREEN 7 855_CRT_GREEN 4 ATI_CRT_RED 7 855_CRT_RED 4

L58 1 1 1 1 2 220Z/100M 2 220Z/100M 2 220Z/100M 2 L74 1608 120Z/100M L59 L60 4 3 2 1

CRT_GREEN CRT_RED

CON_RED

15P/3R-FM 7312S-15G2T-DC SUYIN

1 3 5 7 CHAGND

2 4 6 8 ESD41A/NA 4 3 2 1

CP1 47PX4/NA 1206

C1 1 50V 10% C2 1 50V 10% C4 1 50V 10%

2 47P 0402 2 47P 0402 2 47P 0402

RP1 75*4/NA 1206

A

5 6 7 8

CHAGND

GND CHAGND GND Title

5 6 7 8

CLOSE TO CRT CONNECTOR

Size C Date:

5 4 3 2

8050 MOTHER B/D

Document Number PCB 316680900001/ASSY 411680900011 Sheet 12 of 34

1

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

D

WHEN USE INTEGRATE VGA ADD R22 DEL R20

Q11

C14 0.22U 0402 +80-20% 16V NEED USE X7R ?

S 7,14,24 7,14,24 7,14,24 4 4 4 4

1

To SB

C

6 5 4

Q2 3 CON_BLUE

SLVU2.8/NA SOT23N CHAGND Q1 1 2 SLVU2.8/NA SOT23N CHAGND Q3 1 2 SLVU2.8/NA SOT23N CHAGND

3 CON_GREEN

3 CON_RED

Rev R01

5

4

3

2

1

SOUTHBRIDGE-ICH4-M(1/2)

U715B 7,24 17,24 17,24 19,24 16,24 17,19,24 18,24

D

+3V

JL1 1 2 JP_NET10 JL2 1 2 JP_NET10 U9A JL3 3 1 2 JP_NET10

ATI_PCIRST#

7 +3V

U715A A5 B2 H6 J1 K6 M10 P6 U1 P12 V10 V16 V18 AC8 AC17 H18 J18 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCCLAN3_3/VCCSUS3_3 VCCLAN3_3/VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCCHI0 VCCHI1 VCCHI2 VCCHI3 VCCLAN1_5/VCCSUS1_5 VCCLAN1_5/VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 V5REF1 V5REF2 V5REF_SUS V_CPU_IO V_CPU_IO V_CPU_IO VCCPLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ICH4-M BGA360_25_36 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS D22 AC23 AC18 AC14 AC10 AC5 AC1 AB20 AB7 AA22 AA16 AA12 AA9 AA3 Y19 Y7 W22 W8 W5 V17 V15 V3 U20 T23 T19 T1 R21 R18 R5 P22 P20 P13 P11 P3 N23 N21 N19 N14 N13 N12 N11 N10 N5 M13 M12 M11 M1 M22 L21 L14 L13 L12 L11 L10 K23 M20 K19 K13 K11 K3 J6 H1 G21 G19 G6 G3 F8 E22 E21 E19 E18 E17 E16 E14 E10 D23 D21 D19 D17 D15 D12 D8 D4

PCI_AD[0..31] AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 C/BE#3 C/BE#2 C/BE#1 C/BE#0 P4 D2 R1 D3 P2 E1 P1 E2 M5 E4 N3 E3 N2 E5 N1 F4 F5 L3 H2 L2 G4 L1 G2 K2 J5 H4 J4 G5 K1 H3 J3 H5 N4 M4 K4 J2 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 PCI_C/BE#[0..3] PCI_C/BE#3 PCI_C/BE#2 PCI_C/BE#1 PCI_C/BE#0

PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# PCI_INTE# PCI_INTF# PCI_INTG# 24 ICH_GPI5 PCI_REQ4# PCI_REQ3# PCI_REQ2# PCI_REQ1# PCI_REQ0#

1

1

1

24 16,24 19,24 18,24 17,24

PCI_REQ4#

PCI_REQ0# SB_CARD_PME# CRT_IN# PCI_GNT4#

B6 C7 B3 A2 B1 A6 B5 D6 B7 A7 E6 C1 C5 E8 F1 L5 F2 M3 F3 G1 L4 M2 K5 W2 U5 P5

REQ# 4 REQ# 3 REQ# 2 REQ# 1 REQ# 0 REQB#/REQ5#/GPIO 1 REQA#/GPIO 0 GNT# 4 GNT# 3 GNT# 2 GNT# 1 GNT# 0 GNTB#/GNT5#/GPIO 17 GNTA#/GPIO 16 FRAME# IRDY# TRDY# DEVSEL# STOP# PAR PERR# PLOCK# SERR# PME# PCIRST# PCICLK ICH4-M BGA360_25_36

GND 2 +3V JL4 1 2 JP_NET10 U9B 4 PCIRST# 6 5 74AHC08_V TSSOP14 7 JL5 1 2 JP_NET10 JL6 1 2 JP_NET10 KBC_PCIRST# 22

C292 10U 6.3V 0805 10% 2

C294 0.1U 0402 16V

C278 0.1U 0402 16V

1

PCI_INTA# R195 1 0/NA 2 PCI_INTB# R854 1 0402G_DFS 0/NA 2 PCI_INTC# R805 1 0402G_DFS 0/NA 2 PCI_INTD# R823 1 0402G_DFS 0/NA 2 PCI_INTE# R192 1 0/NA 2 0402G_DFS PCI_INTF# R199 1 0402G_DFS 0/NA 2 PCI_INTG# R844 1 0402G_DFS 0/NA 2 ICH_GPI50402G_DFS

5% D5 5% C2 5% B4 5% A3 5% C8 5% D7 5% C3 C4

PCI_AD[0..31]

16,17,18,19

PIRQA# PIRQB# PIRQC# PIRQD# PIRQE#/GPI0 2 PIRQF#/GPIO 3 PIRQG#/GPIO 4 PIRQH#/GPIO 5

1 2 74AHC08_V TSSOP14 7

14

1394_PCIRST# 18

PCIRST#0

15,25 +1.5V

C246 0.1U 0402 16V +LAN_3V VDD3S

D

2

24 SB_CARD_PME# 12,24 CRT_IN# 24 16,24 19,24 18,24 17,24 3,24 16,17,18,19,24 16,17,18,19,24 16,17,18,19,24 16,17,18,19,24 16,17,18,19,24 16,17,18,19 16,17,18,19,24 24 16,17,19,24 14,16 PCI_GNT4# PCI_GNT3# PCI_GNT2# PCI_GNT1# PCI_GNT0# B/CB# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_PAR PCI_PERR# PCI_LOCK# PCI_SERR# SB_PME#

14

MCH_PCIRST# 4

2

PCI_GNT0# TP34 1 R409 1 2 0/NA

LAN_PCIRST# 16

C253 0.1U 0402 16V

C244 0.1U 0402 16V

GND +3V PCI_C/BE#[0..3] 16,17,18,19 14 U9C 9 8 10 74AHC08_V TSSOP14 7 JL8 1 2 JP_NET10 JL9 1 2 JP_NET10 JL10 GND 1 2 JP_NET10 TV_PCIRST# 11 1 1 1 1 C223 0.1U 0402 16V C211 0.1U 0402 16V C212 0.1U 0402 16V JL7 1 2 JP_NET10 CARD_PCIRST# 17 GND

+1.5V

E9 F9 E11 F10 V9 V8 V7 F15 F16 F17 F18 K14 K10 K12 K18 K22 P10 T18 V14 U19 L23 M14 P18 T22 F6 F7 E12 R6 T6 U6 G18 E13 F14 E20 V5REF E7 V6 E15 P14 U18 AA23 C22

1

2

PCI_LOCK# SB_PME# PCIRST#

2

1

+VHI_ICH MINIPCI_PCIRST# 19 +1.5V FWH_PCIRST# 23 VDD1.5 1 2

11 PCICLK_ICH

R867 0/NA 0805C_DFS +LAN_1.5V

PCI_PME# R920 1 0/NA 2 5% 0402G_DFS

C

CARDBUS_PME#

CARDBUS_PME# 17

C

1 2

SB_CARD_PME# 1

0/NA 2 R921 0402 +3V U715D R240 1 2 0 J19 H19 K20 HSTPCLK# APICCLK APICD_0 APICD_1 STPCLK# A20M# CPUSLP# CPUPWRGD INTR NMI SMI# IGNNE# A20GATE RCIN# FERR# INIT# SERIRQ LFRAME#/FWH4 LDRQ0# LDRQ1# LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 SUSCLK INTRUDER# RTCRST# PWROK RSMRST# VCCRTC VBIAS RTCX1 RTCX2 DPRSLPVR DPSLP# ICH4-M BGA360_25_36 SLP_S3# SLP_S4# SLP_S5# RI# PWRBTN# SYS_RESET# LANRST# BATLOW#/TP[ 0 ] SUS_STAT#/LPCPD VGATE/VRMPWRGD THERMTRIP# THRM# SMILINK 0 SMLINK 1 SMBDATA SMBCLK SMBALERT#/GPIO 11 SPKR CLK14 Y4 Y2 AA2 Y1 AA1 Y3 Y5 AB2 AB3 V19 W20 V1 AC3 AB1 AB4 AC4 AA5 H23 J23 SLP_S4# SLP_S5# SUSB# 17,22,23,25 AGPBUSY#/GPIO 6 GPIO 7 GPIO 8 GPIO 12 GPIO 13 STP_PCI/GPIO 18 SLP_S1#/GPIO 19 STP_CPU#/GPIO 20 C3_STAT#/GPIO 21 CPUPERF#/GPIO 22 SSMUXSEL/GPIO 23 CLKRUN#/GPIO 24 GPIO 25 GPIO 27 GPIO 28 R2 R3 V4 V5 W3 Y21 W18 W19 T3 Y20 J21 AC2 V2 W1 W4 SUSA# C3_STAT# 1 2 R880 0 0402 KBD_US/JP# EXTSMI# SCI# WAKE_UP# AGPBUSY# 22,24 22,24 22,24 22,24 4,7,24

C285 10U 6.3V 0805 10% 2 2

C224 0.1U 0402 16V

2

GND

C3_STAT#

0402 1 R904

2 8.2K/NA GND

R222 1 0402 2 2 2 2 2 2 2 2

2 10K 5%

+3V 2

DTC144TKA SOT23AN_1 288202240001 SB_PME# 3 R1 Q704

V23 AB23 U21 1 R934 2 0 Y23 AB22 V21 W23 W21 A20_GATE Y22 U22 22 HRCIN# AA21 14 CPU_FERR# 0/NA 2 1 V22 2,23 HINIT# R928 0402G_DFS 5% J22 14,17,19,22 SERIRQ HSTPCLK# HA20M# HSLP# HPWRGD HINTR HNMI HSMI# HIGNNE# 19,22,23 LFRAME# 19 LRDQ0# T5 U3 U4 T2 R4 T4 U2 AA4 W6 W7 AB6 AA6 AB5 Y6 AC7 AC6

+VCCP

2

V5REF_SUS

STOP_PCI# 11 SUSA# 11 STOP_CPU# 3,11,31 0402 1 2 R896 0 CPUPERF# PCLKRUN# SPK_OFF GPIO27 GPIO28 24 16,17,19,24 21,24 24 24 1

1

1

STP_AGP# TP705

7,24 2

C274 10U 6.3V 0805 10% 2

C304 0.1U 0402 10% 16V

1

+1.5V C853 0.1U 0402 10% 16V

1

GPIO27 GPIO28

C219 1U 0402 10V

2

GND

1

PCI_PME#

PCI_PME#

18 MINIPCI_PME# 19 19,22,23 LAD[0..3] 4 SUSCLK LAD[0..3]

LDRQ1# LAD0 LAD1 LAD2 LAD3 SUSCLK INTRUDER# RTC_RST#

0/NA 2 R915 1 0402G_DFS 5% 0/NA 2 R908 1 0402

SB_SUSST# ICH_VGATE

ICH_RI# 16 ICH_PWRBTN# 22 ICH_SYS_RESET# 14 ICH_LAN_RST# 14 ICH_BATLOW# 14 SB_SUSST# 7 CPU_THRMTRIP# 14 SB_THRM# 22 SMLINK0 SMLINK1 SMB_DATA SMB_CLK SMBALERT# SBSPKR 14M_ICH 14 14 14 14 24 14,20 11

+3V

B

R939 1 0402 R270 1 0402 +VCC_RTC

2 10K/NA SB_SUSST# 5% LDRQ1# 2 10K/NA 5%

D1 C23 C21 C19 C17 C15 C6 B22 B20 B18 B16 B12 B9 A22 A20 A18 A16 A4 A1

2

GND

B

4,12,17,25,31 PWROK 22,25 RSMRST# +VCC_RTC VDD3S 1 14,31 DPRSLPVR 2,4 HDPSLP#

RTC_VBIAS RTC_X1 RTC_X2

GND 1 R287 10K +3V 2 R223 0/NA 0805C_DFS 2 R233 0/NA 0805C 2 0402 INTRUDER# 5% +LAN_3V +5V 1

R274 1 0/NA 2 5% V20 0402G_DFS U23

+3V 1

VDD5S 1

VDD5 1

VDD3S 1 R164 1K/NA 0402 5% D10 BAT54 V5REF_SUS C221 0.1U 0402 10% 16V GND

VDD5S 3 2 1 1

U5 VOUT VIN GND0 NC1 NC0 4 5 1 1 2

R276 0/NA 0805_DFS 1 3

+VCC_RTC

1 1 VDD3S C856 1U 0402 +80-20% 10V GND 2 1 180K 0402 5% SLP_S4# RTC_RST# SLP_S5# C315 0.1U 0402 10% 16V GND RTC_VBIAS 1 31 VRMPWRGD PWROK 12 11 13 74AHC08_V TSSOP14 22 0402 5% GND 7 1 +3V D704 2 3 1 BAW56 288100056017 1 2 +3VS R926 4.7K 0402 5% SUSC# 22,26,27 1 0805 1

1

1

R252 1K 0402 5% 2 3 C225 0.1U 0402 10% 16V 1 1

D11 BAT54 V5REF C207 0.1U 0402 10% 16V GND 2

R397 1K 0402 5% 2 1

2 D12 BAV70LT1 288100070006 R288 1 1

C289 2.2U/NA 0603 +/-10%

AME8800AEEV/NA SOT25

C311 4.7U 0805 +80-20% 2

R917 1K 0402 5%

C228 10U 0805 6.3V 10%

C298 1U 0402 10V

C210 1U 0402 10V

2

2

2

2

2

2

GND

2

GND

GND

GND

2

+3V VDD3S 1 1 1 C233 10U 6.3V 0805 10% 2 2 C261 0.1U 0402 10% 16V C305 0.1U 0402 10% 16V C275 0.1U 0402 10% 16V 1 C277 0.1U 0402 10% 16V

2

1 2 1.25MM/ST/MA-2 ACES 85205-0200

14

J710

1

1

1

1

1

R306 2 ICH_VGATE

C245 1U 0402 10V

C206 1U 0402 10V

C213 0.1U 0402 10% 16V

C306 0.1U 0402 10% 16V

C307 0.1U 0402 10% 16V

1 C308 0.1U 0402 10% 16V

A

C841 0.047U 0402 10% 25V

2

Spacing other signal 25 mils

U9D

2

2

2

2

2

2

2

2 2

1

3

A

R296 10M 0402 5% C855 1 50V 22P 0402 2 4 +/-10% 2 RTC_X1 1

GND +VHI_ICH GND R311 1 2 0/NA 1 1 VDD1.5 R932 10K 0402 5% 2 22

4

GND

1

1

R938 X704 10M 0402 32.768KHZ 5% 2 RTC_X2

C861 1 50V GND

5

22P 0402 2 +/-10%

1 0805

2 R234 0/NA 0805C_DFS 2 R245 0/NA 0805C

C229 10U 6.3V 0805 10% GND 2 2

C208 0.1U 0402 10% 16V

C260 1U 0402 10V

C824 0.1U 0402 10% 16V

1

+3V

+1.5V

+LAN_1.5V C269 0.1U 0402 10% 16V Title GND Size C Date:

2

1

1

2

2

1

2

8050 MOTHER B/D

Document Number PCB 316680900001/ASSY 411680900011 Sheet 13 of 34

1

2

A20GATE

R931 1

2 0

3

A20_GATE

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

SOUTHBRIDGE-ICH4-M(2/2)

U715E 15 15 15 15 15 15 USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2R185 R190 R173 R178 R196 R205 1 1 1 1 1 1 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA TP23 TP29 TP33 TP37 TP24 TP28 2 2 2 2 2 2 5% 5% 5% 5% 5% 5% 1 1 1 1 1 1 0402G_DFS 0402G_DFS 0402G_DFS 0402G_DFS 0402G_DFS 0402G_DFS C20 D20 A21 B21 C18 D18 A19 B19 C16 D16 A17 B17 B15 C14 A15 B14 A14 D14 8 7 6 5 J20 G22 F20 G20 F21 H20 F23 H22 G23 H21 F22 E23 F19 B23 A23 1 USBP_0 USBP_0# USBP_1 USBP_1# USBP_2 USBP_2# USBP_3 USBP_3# USBP_4 USBP_4# USBP_5 USBP_5# OC#0 OC#1 OC#2 OC#3 OC#4 OC#5 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 GPIO 42 GPIO 43 CLK48 USBRBIAS# USBRBIAS HI 0 HI 1 HI 2 HI 3 HI 4 HI 5 HI 6 HI 7 HI 8 HI 9 HI 10 HI 11 HI_STB#/HI_STBF HI_STB/HI_STBS HI_COMP HIVSWING HIREF CLK66 LANRXD0 LANRXD1 LANRXD2 LANTXD0 LANTXD1 LANTXD2 LANRSTSYNC LANCLK EE_DIN EE_CS EE_SHCLK EE_DOUT ACSYNC ACSDOUT ACBITCLK ACRST# ACSDIN0 ACSDIN1 ACSDIN2 L19 L20 M19 M21 P19 R19 T20 R20 P23 L22 N22 K21 N20 P21 R23 R22 M23 T21 A10 A9 A11 B10 C10 A12 B11 C11 D11 D10 C12 A8 C9 D9 B8 C13 D13 A13 B13 1 R810 10 0402 5% 2 HI_COMP HI_VSWING HI_VREF 66M_ICH 11 HUB_HI0 HUB_HI1 HUB_HI2 HUB_HI3 HUB_HI4 HUB_HI5 HUB_HI6 HUB_HI7 HUB_HI8 HUB_HI9 HUB_HI10 R856 1 0402 +VCCP HUB_HI[0..10] HUB_HI[0..10] 4 1 R936 56 0402 5% 2 2 HFERR# 1 56 5% 0402 2 56 5% HUB_STB# HUB_STB GND 4 4 13,17,19,22 SERIRQ R392 1 0402 R307 1 0402 2 CPU_FERR# 13 13 ICH_LAN_RST# ICH_LAN_RST# 1 R308 10K 2 8.2K 5% 2 5% 10K/NA 2 0402 5% GND R929 1 0402 R940 1 0402 R933 1 0402 R310 1 0402 R273 2 56 5% 0402 Q20 288203904022 MMBT3904L R266 B 1 1K 5% 0402 +VCCP CPU_THRMTRIP# 13 1 VDD3S +3V 2 47K 5% 2 47K 5% 2 10K 5% 2 10K 5% SMLINK1 SMLINK0 SMLINK1 SMLINK0 13 13 VDD3S

D

+3V VDD3S

R937

13,16 SB_PME#

R907 1 0402

2 10K 5%

D

15 15

USB_OC0# USB_OC1#

USBOC0# USBOC1# USBOC4# USBOC5#

+VCCP 1

WHEN USE INTEGRATE VGA ADD RP26

19,24 7,12,24 7,12,24 7,12,24 7,12,24 24 15,24 19,24 24 24 24 24 WIRELESS_PD# PANEL_ID0 PANEL_ID1 PANEL_ID2 PANEL_ID3 MB_ID2 IDERST# MINIPCI_ACT# MB_ID0 MB_ID1 GPIO42 GPIO43 1 2 3 4

ICH_BATLOW# ICH_SYS_RESET#

RP26 0*4 1206 MB_ID2 MB_ID0 MB_ID1 GPIO43

R269 56 0402 5% R261 1 0/NA 2 5% 0402G_DFS 2 1

ICH_BATLOW# 13 ICH_SYS_RESET# 13

2 CPU_THRMTRIP_OUT# 1 R811 1 0402 TP704 2 10K 5% GND EE_DOUT R812 0 0402 5% 1 2 ACSDOUT ACBITCLK ACRST# ACSDIN0 ACSDIN1 20 20 20 20 20 1

1

1

2 2 13 SMB_DATA

R315 2.2K 0402 5% 2

E

ACSYNC C787 10P/NA 0402 +/-10% 50V

20

1

Q21 1 2 2N7002 R313 0/NA 0402 5% G

R838 18.2 0402 1% 271061180101

R290 0/NA 0402 5% 2 THERM_ERR# 22,25

2

D S

11 USBCLK_ICH

R318 2.2K 0402 5% D

R316 10K 0402 5% 2 S 2

1 R317 10K 0402 5% SMBDATA 6,11

G

C

ICH4-M BGA360_25_36

GND

1 Q22 2 2N7002 R314 0/NA 0402 5%

2

C

VDD3S

D S

13

SMB_CLK

D

S

SMBCLK

6,11

C

GND

GND

GPIO CHARACTERISTIC LIST

1 1

NAME

R809 10K 0402 5%

TYPE I I I I I I I I I I I I O O O O O O OD O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

POWER PLANE MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL RESUME POWER WELL RESUME POWER WELL RESUME POWER WELL RESUME POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL RESUME POWER WELL RESUME POWER WELL RESUME POWER WELL RESUME POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL MAIN POWER WELL

CURRENT DEFINE CRT_IN# SB_CARD_PME# PCI_INTE# PCI_INTF# PCI_INTG# ICH_GPI5 AGPBUSY# KBD_US/JP# EXTSMI# SMBALERT#(Pull high only) SCI# WAKE_UP# X X STOP_PCI# SUSA# STOP_CPU# C3_STAT# CPUPERF# X PCLKRUN# SPK_OFF X X WIRELESS_PD# PANEL_ID0 PANEL_ID1 PANEL_ID2 PANEL_ID3 MB_ID2 IDERST# MINIPCI_ACT# MB_ID0 MB_ID1 X X

A B

R197 10K 0402 5% 2 2

B5 A6 C8

USBOC4#

GPI[0] GPI[1] GPI[2] GPI[3] GPI[4] GPI[5] GPI[6] GPI[7] GPI[8]

D7

USBOC5# +1.5V +1.5V 2 1

C3 C4

STRAPPING

R911 130 0603 1% +3V R1113 ACSDOUT 1 4.7K/NA R912 150 0402 1% EE_DOUT 1 0402 2 5% 2 0402 5% GND

R2 R3 V4

+1.5V R900 HI_COMP 1 48.7 2 HI_VREF 1 1

R883 487 1% HI_VSWING 1 1 1 2

AA5 GPI[11] V5 W3 E8 C5 GPI[12] GPI[13] GPO[16] GPO[17]

1

C829 0.01U 0402 10% 50V

C828 0.1U 0402 10% 16V

R884 150 0402 1% 2

C838 0.01U 0402 10% 50V

C839 0.1U 0402 10% 16V

1

R813 4.7K/NA

2

2

2

2

2

GND

B

GND R275 1 4.7K/NA 1 R286 4.7K 0402 2 5% 2 0402 5%

Y21 GPO[18]

+VHI_ICH

W18 GPO[19] W19 GPO[20] T3

GND +3V

15

PD_D[0..15]

PD_D[0..15] PD_D15 PD_D14 PD_D13 PD_D12 PD_D11 PD_D10 PD_D9 PD_D8 PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0 15 15 15 15 15 15 15 15 15 15 PDIOW# PDDACK# PDDREQ PDIOR# PIORDY PDA0 PDA1 PDA2 PDCS1# PDCS3# Y11 W11 W10 AB10 W9 AC9 Y9 AB9 AA8 Y8 AB8 AA7 AA10 Y10 AC11 AB11 W12 Y12 AA11 AC12 AB12 AA13 AB13 W13 Y13 AB14

U715C PDD 15 PDD 14 PDD 13 PDD 12 PDD 11 PDD 10 PDD 9 PDD 8 PDD 7 PDD 6 PDD 5 PDD 4 PDD 3 PDD 2 PDD 1 PDD 0 PDIOW# PDDACK# PDDREQ PDIOR# PIORDY PDA0 PDA1 PDA2 PDCS1# PDCS3# SDD 15 SDD 14 SDD 13 SDD 12 SDD 11 SDD 10 SDD 9 SDD 8 SDD 7 SDD 6 SDD 5 SDD 4 SDD 3 SDD 2 SDD 1 SDD 0 SDIOW# SDDACK# SDDREQ SDIOR# SIORDY SDA2 SDA1 SDA0 SDCS1# SDCS3# IRQ14 IRQ15 ICH4-M BGA360_25_36 Y17 AA17 Y16 AB16 Y15 AA15 AC15 Y14 AA14 W14 AB15 W15 AC16 W16 AB17 W17 AA18 AB19 AB18 Y18 AC19 AC21 AC20 AA20 AB21 AC22 AC13 AA19 SD_D15 SD_D14 SD_D13 SD_D12 SD_D11 SD_D10 SD_D9 SD_D8 SD_D7 SD_D6 SD_D5 SD_D4 SD_D3 SD_D2 SD_D1 SD_D0

SD_D[0..15]

13,31 DPRSLPVR SD_D[0..15] 15

GPO[21]

Y20 GPO[22] J21 GPO[23]

13,20

SBSPKR

R852 1 4.7K/NA

0402 2 5%

AC2 GPIO[24] V2 W1 W4 GPIO[25] GPIO[27] GPIO[28]

J20 GPIO[32] G22 GPIO[33]

SDIOW# SDDACK# SDDREQ SDIOR# SIORDY SDA2 SDA1 SDA0 SDCS1# SDCS3# IRQ14 IRQ15 15 15 15 15 15 15 15 15 15 15 15 15

F20 GPIO[34] G20 GPIO[35]

STRAPPING AT RISING EDGE OF PWROK

STRAPPING PINS ACSDOUT EEDOUT GNTA# DPRSLPVR FUNCTIONS SAFE MODE RESERVED OP-BLOCK SWAP OVERRIDE HUB INTERFACE TERMINATION SCHEME HUB INTERFACE SCHEME(1.0 OR 1.5) NO REBOOT

F21 GPIO[36] H20 GPIO[37] F23 GPIO[38] H22 GPIO[39] G23 GPIO[40] H21 GPIO[41] F22 GPIO[42] E23 GPIO[43]

A

HUB_ICH_COMP SBSPKR

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 14 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

HDD- PRIMARY IDE CONNECTOR

J714 GND2 GND1 R436 14 PD_D[0..15] PD_D[0..15] PD_D0 PD_D1 PD_D2 PD_D3 PD_D4 PD_D5 PD_D6 PD_D7 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15 1 RSTDRV1# 2 PD_D7 PD_D6 PD_D5 10K/NA PD_D4 0402 PD_D3 5% PD_D2 PD_D1 PD_D0 PDDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDA1 PDA0 PDCS1# HDD_LED# +5V_HDD 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GND2 GND1 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15 +5V 1 R901 2 10K/NA 0402 5% RSTDRV2# 1

CDROM- SECONDARY IDE CONNECTOR

GND R922 1 10K 0402 2 5% CDROM_LEFT CDROM_COM M RSTDRV2# SD_D7 2 5% SD_D6 SD_D5 SD_D4 SD_D3 SD_D2 SD_D1 SD_D0 SDIOW# SIORDY IRQ15 SDA1 SDA0 SDCS1# CD_LED# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 J708 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 CDROM_RIGHT SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 SDDREQ SDIOR# SDDACK# 1 SDA2 SDCS3# TP706 CDROM_RIGHT 20 R919 10K/NA 0402 Q703 5% DTC144TKA/NA R1 2 2 3 20 CDROM_LEFT 20 CDROM_COM M 14 SD_D[0..15] 2 R909 R1 1 0 0402 5% 1 SD_D[0..15] SD_D0 SD_D1 SD_D2 SD_D3 SD_D4 SD_D5 SD_D6 SD_D7 SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 GND R927 1 10K/NA 0402

D

3

GND

D

R1085 1 470 5% 0402 PDA2 PDCS3# +5V_HDD 2 GND

14,24

IDERST#

2

Q705 DTC144TKA/NA

1

+5V GND 1 R492 10K 0402 5% 2 RSTDRV1#

23

HDD_LED#

23

CD_LED# +5V_CDROM R836

+5V_CDROM

GND

HDR/FM/22PX2/2MM SPEED ACE-1A2-0216 GND PCIRST#0 2

R476 10K 0402 5% 2

1

GND Q41

2

R1

3

1 470/NA 0402 5%

2 GND

13,25 +5V_HDD 14 14 14 14 14 14 14 14 14 14 14 PDDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDA1 PDA0 PDA2 PDCS1# PDCS3# PDDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDA1 PDA0 PDA2 PDCS1# PDCS3# R295 1 5.6K/NA 2 0402 5% R1081 1 4.7K 0402 R1074 1 8.2K 0402 2 5% 2 5% +3V 1 1 1 +3V 2 +3V C872 0.1U 0402 10% 16V C877 0.1U 0402 10% 16V 1 C878 10U 0805C 10V +5V L733 2 120Z/100M 2012

PCIRST#0

R1

Q37 1 DTC144TKA 288202240001 14 14 14 14 14 14 14 14 14 14 14 SDDREQ SDIOW# SDIOR# SIORDY SDDACK# IRQ15 SDA1 SDA0 SDA2 SDCS1# SDCS3# SDDREQ SDIOW# SDIOR# SIORDY SDDACK# IRQ15 SDA1 SDA0 SDA2 SDCS1# SDCS3# R879 1 5.6K/NA 2 0402 5% R833 1 4.7K 0402 R834 1 8.2K 0402 2 5% 2 5% +3V +3V 1 1 1 +3V 2 C813 0.1U 0402 10% 16V C816 0.1U 0402 10% 16V

1

DTC144TKA 288202240001

R/A-25PX2/0.8 SPEED K22-102-150X

3

GND

+5V_CDROM 1

GND

L723 2

+5V

C817 120Z/100M 10U 2012 0805C 10V

C

2

2

2

GND

GND

GND

C

GND

GND

GND

USB CONNECOTR

+5VS U701 3 4 1 GND VIN0 VIN1 VOUT0 VOUT1 1 1 5 1 120Z/100M 2012 R701 33K 0402 5% 2 1 1 C701 + 150U 7343 6.3V C702 + 150U/NA 7343 6.3V 1 120Z/100M 2012 R702 47K 0402 5% L702 2 1 +VCC_USB_0 C5 0.1U 0402 +80-20% 50V 3 4 1 +5VS U705 GND VIN0 VIN1 VOUT0 VOUT1 1 1 5 1 120Z/100M 2012 R706 33K 0402 5% 2 1 C713 + 150U 7343 6.3V L708 2 1 C31 0.1U 0402 +80-20% 50V GND_USB1 2 +VCC_USB_2

C703 1U 0402 +80-20% 10V

RT9701-CBL SOT25

L701 2

GND

GND 14 USB_OC0# USB_OC0# 1 1

GND_USB +VCC_USB_1 1 C3 0.1U 0402 +80-20% 50V GND_USB 2

C709 1U 0402 +80-20% 10V

RT9701-CBL SOT25

2

2

2

GND

2

GND 14 USB_OC1# USB_OC1# 1 1 R708 47K 0402 5%

2

2

2

C704 1000P 0402 +/-20% 50V

C711 1000P 0402 +/-20% 50V

2

2

2

B

GND L3 0603D 14 USBP0+ 1 2 L21 0603D BEAD/NA 14 USBP2+ 1 2 BEAD/NA

GND

2

2

2

B

2

2

3

3 L22

L2 1 4 90Z/100M CHOKE_ACM2012 +VCC_USB_0 1 2 3 4 +VCC_USB_1 A1 A2 A3 A4

J701 1 2 3 4 14 USBP2A1 A2 A3 A4 GND1 GND2 GND1 GND2 1 4

90Z/100M CHOKE_ACM2012

+VCC_USB_2

J706 1 2 3 4 GND1 GND2 VCC PP+ GND GND1 GND2 USB/4PX1 SUYIN 2545A-04GXT

1 L23 0603D

2 BEAD/NA

14 USBP0-

1 L1 0603D

2 BEAD/NA

USB/4PX2/DIP SUYIN 2522A-08G1T-K

2

2

2

2

2

2

2

2

2

GND_USB1 JO16 JO15 JO14

L6 0603D 14 USBP1+ 1 2

JO4 BEAD/NA

JO5

JO6

JO3

JO7

JO8 GND_USB 1 1 1

1

1

1

1

1

2

3

1

JO13 L5 1 JO9 GND_USB GND_USB 1 2 SHORT-SMT4 JO702 2 GND BEAD/NA GND SHORT-SMT4 GND_USB GND_USB1 2 90Z/100M CHOKE_ACM2012 SHORT-SMT4 JO17 1 2 SHORT-SMT4 GND_USB1

1

A

4

A

14 USBP1-

1 L4 0603D

2

1

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 15 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

+2.5VS_DDR L732 1 +1.8VS 2 L731 1 2 120Z/100M/NA 2012 1 1 1 1 1

DVDD

LAN-RTL8100CL/RTL8110S

Close to RTL8100C

+3VS MDI0+ MDI01 1 R1087 49.9 0402 1% 2 2 1 R1090 49.9 0402 1% 2 MDI1+ MDI11 R1082 49.9 0402 1% 1 2 1 R1086 49.9 0402 1% 1 1 1 1 1 1 1

C904 0.1U 0402 10% 16V

C894 0.1U 0402 10% 16V

C905 0.1U 0402 10% 16V

C879 0.1U 0402 10% 16V

1 C873 0.1U 0402 10% 16V 2

2 120Z/100M 2012

DVDD

2

2

2

USED IN 93C56

C906 0.1U 0402 10% 16V R1108 1 R1110 1 2 10K/NA 0402 2 3.6K 0603 VCC NC1 NC0 GND 8 7 6 5

+3VS

D

CTRL18

Q707 B

+1.8VS

C863 0.1U 0402 10% 16V

C864 0.1U 0402 10% 16V

C866 0.1U 0402 10% 16V

C880 0.1U 0402 10% 16V

C876 0.1U 0402 10% 16V

C862 0.1U 0402 10% 16V

C865 0.1U 0402 10% 16V

C874 0.1U 0402 10% 16V

C886 0.1U 0402 10% 16V

C891 0.1U 0402 10% 16V

+3VS

1

1

1

2

2

2

2

2

2

2

D

E

ADD if use RTL8110S

DVDD GND 1 0/NA R1100 DVDD_A 2 0402 +3VS AVDDL AVDDH

2

2

2

2

GND EECS EECK EEDI EEDO 1 2 3 4

U723 CS SK DI DO

C870 10U 16V 1206

1

2SB1188/NA

24 32 45 54 64 78 99 110 116 126

26 41 56 71 84 94 107

AVDD33_0 AVDD33_1 NC_24 AVDD33(REG)

NC_18 VDD25_0 NC_19 VDD25_1 NC_20 VDD25_2 VDD25_3 NC_21 NC_22 NC_23

VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 VDD33_6

2

13,14

SB_PME#

NC_25 NC_26

GND

R1008 15K 0402 2 1

U719 ISOLATEB LAN_WAKE PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3 31 23 105 104 103 102 98 97 96 95 93 90 89 87 86 85 83 82 79 59 58 57 55 53 50 49 47 43 42 40 39 37 36 34 33 92 77 60 44 28 65 68 61 29 30 46 25 63 67 76 88 70 75 69 27 PMEB ISOLATEB LANWAKE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBEB0 CBEB1 CBEB2 CBEB3 PCICLK CLKRUNB DEVSELB FRAMEB GNTB REQB IDSEL INTAB IRDYB TRDYB PAR NC_8 PERRB SERRB STOPB PCIRSTB

10 120

GND

1

C867 0.1U 0402 16V 10%

2

1

1

1

2

2

GND

R1006 1K 0402

3 7 16 20

R1067 49.9/NA 0402 1% 2 2 1

R1071 49.9/NA 0402 1% 2

R1063 49.9/NA 0402 1% 1 2

1 R1066 49.9/NA 0402 1% C884 0.01U/NA 0402 +80-20% 50V GND 2 R272 0/NA 0603 MDI3+ 1 2

+5V

93C46 SO8 283467540002

GND

GND

+3VS L737 1 +2.5VS_DDR L738 1 2 120Z/100M 2012

13,17,18,19 PCI_AD[0..31]

PCI_AD[0..31]

GND TX+ TXRX+ RXNC_9 NC_10 NC_11 NC_12 1 2 5 6 14 15 18 19 MDI0+ MDI0MDI1+ MDI1MDI2+ MDI2MDI3+ MDI3R305 0/NA 0603 MDI0+ 1 2 PMDI0+ R303 0/NA 0603 MDI1+ 1 PMDI1+ 2 R285 0/NA 0603 MDI2+ 1 2 PMDI2+

AVDDL AVDDL 1 1 1 C895 0.1U 0402 10% 16V 1 C893 0.1U 0402 10% 16V C887 0.1U 0402 10% 16V C883 0.1U 0402 10% 16V

ADD if use RTL8110S

2 120Z/100M/NA 2012

2

EESK AUX/EEDI EEDO EECS

111 109 108 106

EECK EEDI EEDO EECS

2

2

Change DVDD to +1.8VS, when use RTL8110S

C911 1U 0402 +80-20% 10V

C900 0.01U 0402 +80-20% 50V

C896 0.01U 0402 +80-20% 50V

1C

1

MDI2+ MDI2-

MDI3+ MDI3-

C882 0.01U/NA 0402 +80-20% 50V

PMDI3+

2

1

2

1

2

1

2

L51

L49

L48

L44

+3VS

C

AVDDH L736 1 2 1 1 C903 0.1U/NA 0402 10% 16V

GND

XTAL1 XTAL2

121 122

LAN_XTAL1 LAN_XTAL2

2.Parallel and equal length 3.Not to use via

MDI0-

120Z/100M CORE_ACM2520U 4 2 0603 PMDI0MDI1-

120Z/100M CORE_ACM2520U 4 2 0603 PMDI1MDI2-

120Z/100M/NA CORE_ACM2520U 4 2 0603 PMDI2MDI3-

120Z/100M/NA CORE_ACM2520U 4 2 0603 PMDI3-

3

3

3

3

1

Change AVDDL to +2.5VS_DDR , when use RTL8110S

2

2

2

2

1.50/8/8/8/50

C

120Z/100M/NA 2012

ADD if use RTL8110S

2

C890 0.1U/NA 0402 10% 16V

1 R304 0/NA

1 R297 0/NA

1 R278 0/NA

1 R263 0/NA

2

GND

NC_13 CTRL25 RSET

125 8 127

CTRL18 R1099 1 1% 2 5.6K 0402 GND

ADD if use RTL8110S

13,17,18,19 PCI_C/BE#[0..3]

PCI_C/BE#[0..3]

Change to 2.49K when use RTL8110S

LED0 LED1 LED2 NC_14 117 115 114 113 LED0 LED1 LED2 LED3 2 1 2 DVDD 1 PMDI0+ C889 0.1U 0402 16V 10% 2 120Z/100M 2012 0.01U/NA 2 0402 GND C835 0.1U 2 0402 GND C849 GND GND GND 0.01U/NA 2 0402 1 PMDI2V_DAC PMDI3+ C854 PMDI3V_DAC 5 4 3 2 1 H5007/NA H500X 20 21 22 23 24 MDO22 2 2 MCT2 MDO3+ JO717 JO716 JO715 JO714 MDO3MCT1 1 1 1 1 2 1 PMDI1V_DAC PMDI2+ 8 7 6 17 18 19 PJRXMCT3 MDO2+ 20 20 MODEMP MODEMN MODEMP MODEMN A2 A1 GND1 GND2 C845 1 PMDI0V_DAC PMDI1+ 12 11 10 9 1 2 2 13 14 15 16 PJTX+ JO721 PJTX1MCT4 PJRX+ PJRX+ PJTX1PJTX+ PJRXMDO2MDO2+ MDO3MDO3+ 8 7 6 5 4 3 2 1 JO718 JO719 1 JO720 1 J709 8 7 6 5 4 3 2 1 RJ45

PCI_AD18

11 13,17,19,24 13,17,18,19,24 13,17,18,19,24 13,24 13,24 13,24 13,17,18,19,24 13,17,18,19,24 13,17,18,19 13,17,18,19,24 13,17,19,24 13,17,18,19,24 13

PCICLK_LAN PCLKRUN# PCI_DEVSEL# PCI_FRAME# PCI_GNT3# PCI_REQ3# R947 PCI_INTE# PCI_IRDY# PCI_TRDY# PCI_PAR PCI_PERR# PCI_SERR# PCI_STOP# LAN_PCIRST#

It's should be NA when change to RTL8110S

NC_15 AVDD25 NC_16 NC_17 11 12 72 74 L735 V_12P 1 2

1

100

2 0402

Use H1285 for RTL8100C

U716

GND_45

GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11

NC_6 GND_12 NC_7 GND_13 GND_14 GND_15 GND_16

NC_0 GND_0 NC_1 GND_1 NC_2 NC_3 GND_2 GND_3 NC_4 NC_5

GND RTL8100CL PQFP128A_0.5MM

22 35 48 52 62 73 80 100 112 118

21 38 51 66 81 91 101 119

B

13 17 9 4 123 124 128

1

B

Crystal should be placed far away from I/O port and Tx,Rx,power,magnetics.

LAN_XTAL1 LAN_XTAL2 2 R1101 1 1M 0402 1% X706 2 25MHZ TXC8X4.5 274012500415 1 C915 27P 0402 5% +3V

R1070 1K/NA 0402 5%

A2 RJ11 A1 GND1 GND2 RJ11-2P/RJ45-8P C10037-102XX

ADD if use RTL8110S

GND

2

GND_45 GND_45

R943 AVDDL 2 R944 DVDD 2 1 0/NA 0805 1 0/NA 0805 V_DAC GND

0.01U/NA 2 0402

1

1 C914 27P 0402 5% 1

Add thease caps when use RTL8110S, and C879 change to 0.01U

GND_45

2

2

Add AVDDL to V_DAC, when change to RTL8110S

1 L719 0 0603 TX+ TXC TXRX+ RXC RXNC2 NC3 10 11 9 16 14 15 12 13 MCT4 PJTX1PJTXPJTX+ PJRXPJRX+ 1 2 3 4 R271 1 R277 1 MCT4 MCT3 R152 R930 R262 R254 1 1 1 1 2 2 2 2 2 2 75 0402 75 0402 75 0402 75 0402 75/NA 0402 75/NA 0402 MDO2+ 8 RP27 7 0*4 MDO26 1206MDO3+ MDO35 GND 1 L728 0 0603 GND

2

GND

GND

+3VS PMDI0V_DAC PMDI0+ PMDI1V_DAC PMDI1+ 7 6 8 1 3 2 4 5 KBC_RI# 22 1

U717 TD+ TDC TDRD+ RDC RDNC0 NC1 LF-H80P SOX16

GND_45

2

D707

D708

D709

D710 R1111 2 0 5% 0402 Q709 R1114 1 2 DTC144TKA 0/NA 288202240001 0402 5% 1 2

R1115 10K 0402 5% ICH_RI# 13

A

A

A

A

MCT3

A

CL-190G/NA 1K R1097 510/NA 0402 1% LED0 LED1 LED2 LED3

CL-190G/NA CL-190G/NACL-190G/NA 1K 1K 1K LAN_WAKE 2 R1 R1102 510/NA 0402 1% R1107 510/NA 0402 1% R1109 510/NA 0402 1%

3

GND_45

A

1

Pull high at EC side.

2 2 2 2

GND

MCT2 MCT1

C327 1000P 2KV 1808 10% Title

2

1

8050 MOTHER B/D GND_45

Size C Date: Document Number PCB 316680900001/ASSY 411680900011 Sheet 16 of 34

1

Rev R01

Monday, December 29, 2003

5

4

3

2

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

D

CARD_PCIRST#

R1190 1 0/NA 2 5% 0402G_DFS D1 F3 L3 U7 W12 M17 G19 B14 E11 C9 E7 A11

C984 0.1U 0402 10% 16V G2 J5 P2 P9 R13 P17 K18 E18 F12 B10 E8 C5 M5

2

CB710 IDSEL: AD20 PCI REQ0# PCI GNT0# PCI INTB# INTC#

CardBus & Reader(CB710)

+CARD_VCC +3V VPPD1 VPPD0 1 2

JS5 +CARD_VCC +CARD_VCC GND_C1 1 2 SHORT-SMT4 JS7 1 2 SHORT-SMT4 GND JS4 1 GND_C3 J6 GND CAD0 CAD1 CAD3 CAD5 CAD7 CCBE0# CAD9 CAD11 CAD12 CAD14 CCBE1# CPAR CPERR# CGNT# CINT# CCLK CIRDY# CCBE2# CAD18 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD29 R2_D2 CCLKRUN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND_C1 GND_C3 GND_C2 GND_C4 VCC_SC SC_PWR5EN# SC_PWR3EN# SC_CLK SC_IO SC_RST# SC_CD# SC_LED# SC_OC# SC_C8 SC_C4 MS_PWREN# MS_SCLK MS_CLKIN MS_BS MS_LED# MS_INS# MS_SDIO GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 N14 N15 P18 R17 T19 P15 P19 M14 N18 R19 R18 P12 U12 W13 P11 R12 V12 R11 G17 G18 H15 H14 N17 U11 V11 SC_PWR5EN# 1 R1196 2 SC_PWR3EN# 1 10K/NA 2 0402 R1197 10K/NA 0402 GND R1198 +3V SD_CLK1 1 10 0402 5% 2 1 SD_CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 FM/34PX2/1.27MM ACECON MF-291000000008 291000256843 GND 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 CCD1# CAD2 CAD4 CAD6 R2_D14 CAD8 CAD10 CVS1 CAD13 CAD15 CAD16 R2_A18 CBLOCK# CSTOP# CDEVSEL# CTRDY# CFRAME# CAD17 CAD19 CVS2 CRST# CSERR# CREQ# CCBE3# CAUDIO CSTSCHG CAD28 CAD30 CAD31 CCD2# 2 SHORT-SMT4 JS8 1 2 SHORT-SMT4 GND

D

2

2

2

GND_C2 R1189 43.2K 0402 1% 1 C983 0.1U 0402 10% 16V

R1187 43.2K 0402 1% 1 1

R1188 10K 0402 1

GND F17 F18 F19 E5 U727

CRST# CCLKRUN# CAD11

GND

GND_C4

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11

VPPD2

VPPD1

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11

G_RST

VPPD0

VCCA

NC

+SD_MSVDD 13,16,18,19 PCI_AD[0..31] PCI_AD[0..31] PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 H5 G1 G3 H6 F1 G5 F2 E1 G6 F5 E3 C12 A4 E6 B5 F6 B8 A8 E9 F9 B9 A9 F10 E10 F11 E13 C11 B11 A12 B12 E12 A13 F15 E17 A16 C15 E14 F13 B15 E19 F14 A10 G15 C14 D19 A14 C13 B13 C10 F8 A7 B7 C7 F7 A6 B6 C6 E2 A5 C8 A15 G14 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 VCCD0# VCCD1# PCLK SPKROUT RI_OUT#PME# SUSPEND# PRST# GNT# REQ# IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE0# C/BE1# C/BE2# C/BE3# IRQSER VCC_SD SD_PWREN# SD_CLKIN SD_CLK SD_CMD SD_WP SD_CD# SD_LED# SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 SM_PWR5EN# SM_PWR3EN# SM_WPD# SM_WP# SM_CE# SM_RE# SM_LED# SM_CD# SM_R/B# SM_WE# SM_ALE SM_LVD SM_CLE SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7 V15 P13 V14 P14 R14 V13 U13 W14 W15 U14 W16 U15 J15 H19 H18 K17 J14 J18 H17 N19 K14 K15 J19 K19 J17 L14 L17 L19 M18 M15 M19 L18 L15 SD_PWREN# R1191 1 0/NA 2 5% SD_CLK1 0402G_DFS SD_CMD SD_WP# SDCD# SD_LED# SD0 SD1 SD2 SD3 +VPPOUT GND 1 1

+VPPOUT

C985 0.1U 0402 10% 16V

C986 0.1U 0402 10% 16V

2

C

13,24 13,24

PCI_INTB#

PCI_INTB# R1193 1 0/NA 2 5% 0402G_DFS

PCI_INTC#

13,19,24 PCI_INTF#

0/NA 2 5% PCI_INTC# 1 R1194 0402G_DFS PCI_INTF# CARD_MF1 1 0/NA 2 0402 R1238 5% SERIRQ R1195 1 0/NA 2 0402 5% RI# CARD_ACT PCLKRUN# 13,16,19,24 PCLKRUN# VCC5_EN# VCC3_EN#

SM_PWR5EN# SM_PWR3EN# SM_WPD# SM_WP# 1 SM_CE# SM_RE# SM_LED# SM_CD# SM_R/B# SM_W E# SM_ALE 1 SM_LVD SM_CLE 1 SM_SD0 1 SM_SD1 1 SM_SD2 1 SM_SD3 1 SM_SD4 1 SM_SD5 1 SM_SD6 1 SM_SD7 1

R1192 2 10K R1241 2 10K TP707 R1242 2 10K

1 0402 1 0402

GND

1 0402

TP708 TP709 TP16 TP711 TP712 TP713 TP18 TP715 TP716 TP19

GND

2

C

11 PCICLK_CARD 20 CARDSPK# 13 CARDBUS_PME# 13,22,23,25 SUSB#

1 R1199 1 R1201 10K 10K

R1200

1 4.7K

PCI_AD20

13 CARD_PCIRST# 13,24 PCI_GNT0# 13,24 PCI_REQ0# R1202

2 0402 CARD_PCIRST#

2 0402 2 0402

C987 10P 0402 5% 50V J716 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 GND1 GND2 GND3 GND4 GND5 GND6 MA/15PX2/ST ACES 88025-3000 291000013027 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

13,16,18,19,24 PCI_FRAME# 13,16,18,19,24 PCI_IRDY# 13,16,18,19,24 PCI_TRDY# 13,16,18,19,24 PCI_DEVSEL# 13,16,18,19,24 PCI_STOP# 13,16,18,19,24 PCI_PERR# 13,16,19,24 PCI_SERR# 13,16,18,19 PCI_PAR 13,16,18,19 PCI_C/BE#0 13,16,18,19 PCI_C/BE#1 13,16,18,19 PCI_C/BE#2 13,16,18,19 PCI_C/BE#3 13,14,19,22 SERIRQ

B

1 100 0402 5%

2

MS_PWREN# MS_CLK1 R1204 1 0/NA 2 MS_BS 0402_DFS 5% MS_LED# MS_INS# MS_SDIO +SD_MSVDD 43.2K 43.2K 43.2K 43.2K 43.2K 43.2K 43.2K GND 1 R1205 1 R1206 1 R1207 1 1 1 1 R1208 R1209 R1210 R1211 2 0402 2 0402 2 0402 2 2 2 2 0402 0402 0402 0402

R1203 MS_CLK1 1 GND 10 0402 5% 2

GND MS_SCLK 1 SDCD# MS_SCLK SD_CLK SD1 SD3 MS_INS# SD_WP# SD_CMD SD0 SD2 MS_BS MS_SDIO +SD_MSVDD

2 GND 1% 1% 1% 1% 1% 1% 1% SM_W E# SM_RE# SM_CE# MS_BS MS_SDIO MS_SCLK SM_LVD 2

C988 10P 0402 5% 50V

SERIRQ

+SD_MSVDD

R431 1 0 5% 2 0402 R440 1 0 5% 2 0402 R435 1 0/NA5% 2 0402 R444 1 0/NA5% 2 0402

B

1

CD1#/CCD1# CD2#/CCD2# VS1#/CVS1 VS2#/CVS2 CE1#/CCBE0# A8/CCBE1# A12/CCBE2# REG#/CCBE3# A18/RSVD (R_A18) D2/RSVD (R_D2) D14/RSVD (R_D14) A19/CBLOCK# A20/CSTOP# A21/CDEVSEL# A22/CTRDY# A13/CPAR WE#/CGNT# WP/CCLKRUN# BVD1/CSTSCHG BVD2/CAUDIO WAIT#/CSERR# READY/CINT# A15/CIRDY# A14/CPERR# INPACK/CREQ# RESET/CRST# A23/CFRAME# A16/CCLK

+3VS D3/CAD0 D4/CAD1 D11/CAD2 D5/CAD3 D12/CAD4 D6/CAD5 D13/CAD6 D7/CAD7 D15/CAD8 A10/CAD9 CE2#/CAD10 OE#/CAD11 A11/CAD12 IORD#/CAD13 A9/CAD14 IOWR#/CAD15 A17/CAD16 A24/CAD17 A7/CAD18 A25/CAD19 A6/CAD20 A5/CAD21 A4/CAD22 A3/CAD23 A2/CAD24 A1/CAD25 A0/CAD26 D0/CAD27 D8/CAD28 D1/CAD29 D9/CAD30 D10/CAD31

2

2

C465 0.1U 0402 +80-20% 50V

1 C463 10U 0805 6.3V 10%

GND

2

H2 J1 H1 J3 J2 K1 J6 K3 K5 L1 L2 L6 M1 L5 M3 M2 M6 W4 U5 R6 V5 U6 V6 W6 V7 W7 R8 W10 V10 U10 R10 W11

R1212 10K/NA 0402 1 C989 1 2 0.1U/NA 0402 16V 10% RI#

GND +SD_MSVDD 1 GND GND L54 120Z/100M 2012 273000150013 2 D

H3 R9 U8 P7 K6 N1 T1 P8 N2 P10 K2 N6 N5 R1 R2 N3 P3 U9 CSTSCHG V9 CAUDIO W9 CSERR# W8 CINT# V8 CIRDY# P5 CPERR# P1 CREQ# R7 CRST# W5 CFRAME# R3 2 P6

3 Q714 DTC144WK/NA

1

CCD1# CCD2# CVS1 CVS2 CCBE0# CCBE1# CCBE2# CCBE3# R2_A18 R2_D2 R2_D14 CBLOCK# CSTOP# CDEVSEL# CTRDY# CPAR CGNT#

CB710 BGA_GHK_209

CAD0 CAD1 CAD2 CAD3 CAD4 CAD5 CAD6 CAD7 CAD8 CAD9 CAD10 CAD11 CAD12 CAD13 CAD14 CAD15 CAD16 CAD17 CAD18 CAD19 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD28 CAD29 CAD30 CAD31

R1213 33 0402 +3V 1 CCLK R376 100K 0402 5% 2 2 S

Q24 SI2301DS D S D 1

2

K D36 CL-190G D Q716 S 2N7002 2S

A

R552 1 0402 2 5% 220

+3V

Multi Function pin need pull up.

+3VS R1216 R1218 R1220 1 4.7K/NA 2 0402 1 4.7K/NA 2 0402 1 4.7K/NA 2 0402 CARD_MF1 +3V RI# 2 CARD_ACT +3V R1221 10K 0402 +3V 2

A

2

R1214 0/NA 5% 0402G_DFS CCLKRUN# R1224 R1225 R1226 R1228 R1230 R1231 0402 0402 0402 0402 0402 0402 1% 1% 1% SDCD# SD_WP# MS_INS# SM_CD# SM_WPD# SM_R/B#

1

C341 0.1U 0402 10% 16V

4,12,13,25,31 PWROK

G

1

G

2

+5V

+3V VCC5_EN# VCC3_EN# 1 2 3 4 5 6 7 8

U728 VCCD0 VCCD1 3.3VA 3.3VB 5VA 5VB GND OC TPS2211A SHDN VDDP0 VDDP1 AVCCA AVCCB AVCCC AVPP 12V SSOP16 16 15 14 13 12 11 10 9

43.2K 43.2K 43.2K 8.2K 8.2K 8.2K +CARD_VCC +VPPOUT GND

1 1 1 1 1 1

2 2 2 2 2 2

SD_PWREN# MS_PWREN# (43K) 1

R377 10K 0402 1

2

1

1K 0402 5%

SD_LED# MS_LED#

A

VPPD0 VPPD1

R1229 10K 0402 1

+3V +SD_MSVDD 1 1 1 1 1 1 1 43.2K 43.2K 43.2K/NA 43.2K 43.2K 43.2K 1 R388 1 R1233 1 R1234 1 R1235 1 R389 1 R1237 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 1% 1% 1% 1% 1% 1% SD3 SD_CMD SD_CLK SD0 SD1 SD2 C993 0.1U 0402 10% 16V C994 0.1U 0402 10% 16V C995 0.1U 0402 10% 16V C996 0.1U 0402 10% 16V C997 0.1U 0402 10% 16V C998 0.1U 0402 10% 16V C999 0.1U 0402 10% 16V 1 C1000 0.1U 0402 10% 16V 1 1

1

C991 0.1U 0402 10% 16V

1

C992 0.1U 0402 10% 16V

286302211006 GND 2

C1001 2.2U 0603 +/-10%

C1002 1U 0402 +80-20% 10V

2

2

2

2

2

2

2

2

2

2

Title

2

GND

GND

GND

GND

8050 MOTHER B/D

GND Size C Date:

2

1

G R378

R1217 0/NA 5% 0402G_DFS

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 17 of 34

1

Rev R01

Monday, December 29, 2003

5

4

3

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

2

2

2

VT6307L IDSEL: AD21 PCI REQ1# PCI GNT1# PCI INTG#

D

1

1

C956 0.1U 0402 +80-20% 50V GND

C957 0.1U 0402 +80-20% 50V

1

1394_AVCC:Because of suspend then resume unknow, us suspend power

IEEE1394(VT6307L)

1394_AVCC +3V C936 0.1U 0402 +80-20% 50V

ALL Capacator must close to power pin

+PHYVDD C917 0.1U 0402 +80-20% 50V +3V 1 C923 0.1U 0402 +80-20% 50V C922 0.1U 0402 +80-20% 50V C925 0.1U 0402 +80-20% 50V 120Z/100M 2012 +3VS 1 L742 2 120Z/100M/NA 2012 2 1 1 1 L743 2 1 +3V C921 2.2U +80-20% 0805C +PHYVDD +3VS 1 120Z/100M 2012 1 1 L746 2

D

1

1

+3V

1

1

1

1

C931 0.1U 0402 +80-20% 50V

C954 0.1U 0402 +80-20% 50V

C924 0.1U 0402 +80-20% 50V

C920 0.1U 0402 +80-20% 50V

1

C919 0.1U 0402 +80-20% 50V

C918 0.1U 0402 +80-20% 50V

C916 0.1U 0402 +80-20% 50V

+PHYVDD

GND 2

1

1394_AVCC

2

2

2

2

2

1

2 L739 120Z/100M/NA

C961 2.2U +80-20% 0805C

GND 8 20 33 35 102 113 114 125 GND 65 75 89 62 76 90 24 39 49 VCCARX0 VCCARX1 VCCARX2 VCCATX0 VCCATX1 VCCATX2 54 55 53 52 R1112 12CEEENA I2CFAST CARDBUSENA XTPA0M XTPA0P XTPB0P XTPB0M XTPA1P XTPA1M XTPB1P XTPB1M XTPA2P XTPA2M XTPB2P XTPB2M XTPBIAS0 XTPBIAS1 XTPBIAS2 XCPS XRES XI XO EECS/EEAUTO# EEDO EEDI/SDA EECK/SCL/EEFAST PME# MODE0 MODE1 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 46 48 47 72 73 71 70 1 1 1 80 79 78 77 87 86 85 84 74 81 88 63 66 60 61 29 30 31 32 37 43 42 GND 38 40 44 45 51 56 57 67 XI R1116 XO 1 1M 0402 5% X707 1 2 24.576MHZ TXC8X4.5 274012457406 1 C932 10P 0402 5% 50V GND C929 10P 0402 5% 50V GND 2 XI XO EECS_1394 EEDO_1394 EEDI_1394 EECK_1394 1 R1145 6.34K 0402 1% 2 1 TPBIAS R1144 54.9 0402 1% 2 2 1 R1143 54.9 0402 1% R1141 54.9 0402 1% TPBIAS 1 TPA-_6307 TPA+_6307 TPB+_6307 TPB-_6307 1 2 4.7K/NA 0402 5% +3V PCI_AD[0..31] PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 28 27 23 22 21 19 18 17 14 13 12 11 10 7 6 5 120 119 118 117 116 112 110 109 106 105 104 101 100 99 98 97 15 4 122 107 123 127 126 124 95 96 108 91 93 92 3 2 128 58 U724 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# TRDY# IRDY# PGNT# PREQ# IDSEL INTA# PCICLK PCIRST# PAR PERR# STOP# PHYRST#

GND

C955 0.1U 0402 +80-20% 50V

2

2

2

2

2

2

VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7

VCCRAM VCCSUS[0] VCCSUS[1]

13,16,17,19 PCI_AD[0..31]

PHYPC0 PHYPC1 PHYPC2 PHYCMC

1394_AGND

R1142 54.9 0402 1% 2

1

2

C

R1148 4.99K 0402 1% 2

1

2

C965 270P 0402 +/-10% 50V

C964 0.33U 0402 +80-20% 16V

C

2

13,16,17,19 PCI_C/BE#0 13,16,17,19 PCI_C/BE#1 13,16,17,19 PCI_C/BE#2 13,16,17,19 PCI_C/BE#3 13,16,17,19,24 13,16,17,19,24 13,16,17,19,24 13,16,17,19,24 13,24 13,24 13,24 11 13 13,16,17,19 13,16,17,19,24 13,16,17,19,24 PCI_FRAME# PCI_DEVSEL# PCI_TRDY# PCI_IRDY# PCI_GNT1# PCI_REQ1# PCI_INTG# PCICLK_1394 1394_PCIRST# PCI_PAR PCI_PERR# PCI_STOP#

GND C958 47P 0402 +/-10% 50V GND 2 PCI_PME# 13

GND

R1146 1 1

1K/NA 2 0402 5%

+3V +3V U722 EECS_1394 EECK_1394 EEDI_1394 EEDO_1394 1 2 3 4 CS SK DI DO VCC NC1 NC0 GND 8 7 6 5 1 C907 1U 0402 +80-20% 10V GND 2

2

R1147 1K 0402 5%

PCI_AD21 R1117 1 0402

100 2 1%

2

93C46 SO8 283467540002

GNDATX0 GNDATX1 GNDATX2 GNDRAM GNDSUS[0] GNDSUS[1]

GNDARX0 GNDARX1 GNDARX2

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10

C928 0.1U 0402 +80-20% 50V GND

Configuration Straps

I2CEEENA I2C EEPROM. 0: 4-wire EEPROM interface(Default) 1: 2-wire I2C EEPROM interface using SCL/SDA I2C EEPROM Fast Mode 0: Disable (Default) 1: Enable CARDBUSENA CardBus Mode 0: Disable (PCI)(Default) 1: Enable PHYCMC Programmable Contender / Bus Manager Capable High specifies that the node is capable of being a bus manager.

1

1 9 16 26 34 36 94 103 111 115 121

VT6307L PQFP128A_0.5MM

64 68 82

59 69 83 25 41 50

2

B

1

GND

1394_AGND

GND 2

I2CFAST

B

R1149

1 0/NA

2 0402

5%

3

4

L740 TPB-_6307 TPB+_6307 TPBTPB+ R1139 R543 TPA-_6307 TPA+_6307

A

2

1

120Z/100M CORE_ACM2520U

J718 1 2 3 4 5 6 D706 ESD0805A/NA 1 2 3 4 GND0 GND1 4PX1/0.8MM-MA MOLEX 54030-0411 331000004009 L87 1 120Z/100M 2012 2 GND 1394_AGND 1 120Z/100M 2012

A

1 0/NA 1 0/NA

2 0402 5% 2 0402 5% A A A A 2 2 2 2 D28 D711 D30

2

TPATPA+ 3 4

L747 2

JO53 JO48 JO52 JO49 L83 120Z/100M CORE_ACM2520U ESD0805A/NA ESD0805A/NA ESD0805A/NA K K K 1 1 1 1 K

2

1

R534

1 0/NA

2 0402

5% 1394_GND 1394_GND 1394_GND GND

Because of EMC notice, change L547 to 0 ohm 0805

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 18 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

MINI-PCI FROM LYNX-AMD

+3V

MINI-PCI

AD17 PCI_INTD# REQ2#/GNT2#

MINIPCI_PD +3V

13,16,17,18 PCI_AD[0..31]

PCI_AD[0..31] J713 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 GND1 GND2 TIP RX+ RXPJ7 PJ8 LED1_GRNP LED1_GRNN CHSGND INTB# 3.3V[0] RESERVED0 GROUND0 CLK GROUND1 REQ# 3.3V[1] AD[31] AD[29] GROUND2 AD[27] AD[25] RESERVED1 C/BE[3]# AD[23] GROUND3 AD[21] AD[19] GROUND4 AD[17] C/BE[2]# IRDY# 3.3V[2] CLKRUN# SERR# GROUND5 PERR# C/BE[1]# AD[14] GROUND6 AD[12] AD[10] GROUND7 AD[8] AD[7] 3.3V[3] AD[5] RESERVED2 AD[3] 5V[0] AD[1] GROUND8 AC_SYNC AC_SDATA_IN AC_BIT_CLK AC_CODEC_ID1# MOD_AUDIO_MON AUDIO_GND0 SYS_AUDIO_OUT SYS_AUDIO_OUT_GND AUDIO_GND1 RESERVED3 VCC5VA GND1 GND2 124P/0.8MM/H6 SPEED 291000251246 SPEED-B27-101-0038 1 RING TX+ TXPJ4 PJ5 LED2_YELP LED2_YELN RESERVED4 5V[1] INTA# RESERVED5 3.3VAUX[0] RST# 3.3V[4] GNT# GROUND9 PME# RESERVED6 AD[30] 3.3V[5] AD[28] AD[26] AD[24] IDSEL GROUND10 AD[22] AD[20] PAR AD[18] AD[16] GROUND11 FRAME# TRDY# STOP# 3.3V[6] DEVSEL# GROUND12 AD[15] AD[13] AD[11] GROUND13 AD[9] C/BE[0]# 3.3V[7] AD[6] AD[4] AD[2] AD[0] RESERVED_WIP4[0] RESERVED_WIP4[1] GROUND14 M66EN AC_SDATA_OUT AC_CODEC_ID0# AC_RESET# RESERVED7 GROUND15 SYS_AUDIO_IN SYS_AUDIO_IN_GND AUDIO_GND2 MPCIACT# 3.3VAUX[1] 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124

+5V

D

D

R1007 1 10K 0402 5% R1003 1 0 0402 2 5%

2

MINIPCI_LPCAD1 MINIPCI_LPCAD2 R1068 1 0 R1077 1 0 R1078 1 0/NA R1080 1 0 PCI_PME# MINIPCI_LPCAD3 PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 R1092 1 0402 PCI_AD22 PCI_AD20 PCI_PAR PCI_AD18 PCI_AD16 PCI_FRAME# PCI_TRDY# PCI_STOP# PCI_DEVSEL# PCI_AD15 PCI_AD13 PCI_AD11 PCI_AD9 PCI_CBE#0 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 R1094 1 0 5% 2 0402 MINIPCI_PD 100 2 1% PCI_AD17 2 0402 2 0402 2 0402 2 0402 5% PCI_INTD# 13,24 MINIPCI_PCIRST# 13,24 13 MINIPCI_GPORESET# 1 5% PCI_GNT2# MINIPCI_PME# 13 PCI_PAR 13,16,17,18 +5V PCI_FRAME# PCI_TRDY# PCI_STOP# 13,16,17,18,24 13,16,17,18,24 13,16,17,18,24 1 2A R558 470 0402 5% D38 CL-190G LED_CL190 K PCI_C/BE#0 13,16,17,18 R1095 1 0/NA 2 0402 5% 3 PCI_DEVSEL# 13,16,17,18,24 TP721 TOUCHPAD_10

13,17,24 PCI_INTF# 11 PCICLK_MINIPCI PCICLK_MINIPCI 1 R1079 1 0 0402 2 5% C885 10P/NA 0402 +/-10% 50V

R1064 1 0/NA 2 0402 5%

MINIPCI_LPCDRQ#

5% MINIPCI_PCIRST# 5%

13,24 PCI_REQ2#

R1083 1 0 0402 5%

2

MINI_REQ2# PCI_AD31 PCI_AD29 PCI_AD27 PCI_AD25

+3V

GND 1 1 1 1 C875 2.2U 0603 +/-10% C888 0.1U 0402 +80-20% 50V C898 0.1U 0402 +80-20% 50V C901 0.1U 0402 +80-20% 50V MINIPCI_LPCFRAME# 13,16,17,18 PCI_C/BE#3

2

PCI_CBE#3 PCI_AD23 PCI_AD21 PCI_AD19 PCI_AD17 PCI_CBE#2 PCI_IRDY# PCLKRUN# PCI_SERR# PCI_PERR# PCI_CBE#1 PCI_AD14 PCI_AD12 PCI_AD10

2

2

2

+3V

GND 13,16,17,18 PCI_C/BE#2 13,16,17,18,24 PCI_IRDY# 13,16,17,24 PCLKRUN# 13,16,17,24 PCI_SERR# 13,16,17,18,24 PCI_PERR# 13,16,17,18 PCI_C/BE#1

1

1

1

C910 0.1U 0402 +80-20% 50V

C892 0.1U 0402 +80-20% 50V

C899 0.1U 0402 +80-20% 50V

1 C909 0.1U 0402 +80-20% 50V GND 2

2

2

C

2

2

C

PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 PCI_AD1 MINIPCI_LPCAD0 2 +5V

2

R1

Q710 1 DTC144TKA 288202240001

WIRELESS_PD# 14,24 MINIPCI_PCISERIRQ GND

R1093 0/NA 0402 5%

MINIPCI_SIO48M

1

R1138 R1076

1 0

2 0402

5% +3V +3VS

MINIPCI_ACT# 14,24

1 0/NA 2 0402 5% R1072 1 0/NA 2 5% 0402G_DFS

13,22,23 LAD0 13,22,23 LAD1 13,22,23 LAD2 13,22,23 LAD3 13 13,14,17,22 13,22,23 11

B

R1096 R1065 R1069 R1088 R1075 R1118 R1091 R1137

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

2 2 2 2 2 2 2 2

0402 0402 0402 0402 0402 0402 0402 0402

5% 5% 5% 5% 5% 5% 5% 5%

MINIPCI_LPCAD0 MINIPCI_LPCAD1 MINIPCI_LPCAD2 MINIPCI_LPCAD3 MINIPCI_LPCDRQ# MINIPCI_PCISERIRQ MINIPCI_LPCFRAME# MINIPCI_SIO48M

C881 0.1U 0402 +80-20% 50V

PIN24, 124 ARE AUX_POWER

LRDQ0# SERIRQ LFRAME# SIO_48M

GND

GND GND

GND

2

B

A

A

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 19 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

AUDIO CODEC(ALC655)

VA C460 0.1U 10% 16V 0402 0.1U C457 1 2 U17 CARDSPK#1 C458 0.1U 0402 16V 10% 2 1 1 1 2 3 R442 47K 0402 5% 2 2 R443 47K 0402 5% A B GND VCC Y 5 4 R438 1 10K 0402 5% 2 1 1 1 0402 2 5 GND C456 2 1U 0402 10V +80-20% PC_BEEP 1 C475 10U 1210 10V 2 1 16V 4 R484 180K/NA 0603 1% 1 10% VA L64 120Z/100M/NA 2 1 2012 U18 2 OUT ADJ IN GND EN 1 2 3 +5V 1 MIC1 BEAD_600Z/100M L734 0603D 1 2 1 + L70 1 0603D 2 2 BEAD_600Z/100M C942 47P/NA D5.8/H2.0 0402 EM147TK +/-10% 339115000046 50V JO724 D705 SPARKGAP_6 ESD0805A/NA 0603B_0805C 1 2 AGND 2 R1150 1 0 0603 L741 120Z/100M/NA CORE_ACM2520U 2 1 1

13,14 SBSPKR

D

SBSPKR

17

CARDSPK#

MIC5205BM5 SOT25 AGND

D

2

1

L66 120Z/100M 2012 1

3

2

2

4

AGND 2

R452 470K/NA 0402 5%

2

C467 0.01U 0402 +80-20% 50V

1 C509 2200P 0402 +/-20% 50V CAGND 5 J719 4 3 6 2 1 2 RA/D6/6P 2SJ-SB2014D3 CONN_JACK_SB2014 291000920605 CAGND 1 CAGND 2

NC7S32 SOT25

R437 1K 0402 5%

1

2

C455 100P 0402 +/-10% 50V

AGND

AGND GND

2

+3V

AGND

R1151 1 1 1 C491 10U 0805 6.3V 10% C501 0.1U 0402 10% 16V C481 0.1U 0402 10% 16V AVDD 0402 1 1 1 4.7/NA 2 5% MIC_VREF 1

R1154 2 4.7K 0402 5% 1 1 C973 4.7U/NA 0603 6.3V +80-20% 1

R1153 2

MIC_INT 0402 1 C971 0.1U/NA 0402 +80-20% 50V

L57

BEAD_600Z/100M 0603D 1 2 MIC_EXT R1155 1 0 0603 L744 BEAD_600Z/100M 0603D JO725 2 2 C948 100P/NA 0402 +/-10% 50V 1

ACBITCLK C476 22P/NA 0402 +/-10% 50V 1 GND

GND

GND 25 38 U726

C968 C938 0.1U 0.1U 0402 0402 +80-20% +80-20% 50V 50V AGND AGND 2 2 C974 0402 C969 0402 MIC1 C975 0402 MIC2 C970 0402 C513 0402 C507 0402 C515 0402 C979 0402 C980 0402 C976 0402 C516 0402 2 1U 10V +80-20% 2 1U 10V +80-20% 2 1U 10V +80-20% 2 1U 10V +80-20% 2 1U 10V +80-20% 2 1U 10V +80-20% 2 0.22U 16V +80-20% 2 1U/NA 10V +80-20% 2 1U/NA 10V +80-20% 2 1U 10V +80-20% 2 1U 10V +80-20% AOUT_L AOUT_R C519 1 0402 C937 1 0402 1 1 1 1 2 0.1U/NA 16V 10% 2 0.1U 16V 10% 2 1U 10V 2 1U 10V 2 1000P 50V 10% 2 1000P 50V 10%

5% 0 C972 0.1U/NA 0402 +80-20% 50V

2

2

2

2

2

1 9

AGND LINE-L LINE-R MIC1 MIC2 CD-R CD-L 23 24 21 22 20 18 19 16 17 14 15 35 36 13 37 39 1 1 1 1 1 1 1 1 1 1 1 LINE_IN/L LINE_IN/R MIC 1 5%

AGND AGND 1 R1164 2 22K/NA 0402 R1157 0 2 0402 AGND R547 1 R538 1 R550 1 1 1 1 2 6.8K 0402 2 6.8K 5% 0402 5% 5% CDROM_RIGHT CDROM_LEFT CDROM_COM M 1%

DVDD1 DVDD2

AVDD1 AVDD2

GND

2

2

2

1

D718 AGND 1

C

14 14 14 14 14

ACRST# ACSDOUT ACSDIN0 ACSYNC ACBITCLK

ACRST# ACSDOUT ACSDIN0 ACSYNC ACBITCLK L69

SPARKGAP_6 2

R530 1 0402 1 0

2 22 5% 2 1608 R498 1 0402 2 22 5%

11 5 8 10 6 2

RESET# SDATA-OUT SDATA-IN SYNC BIT-CLK XTL-IN

ESD0805A/NA 0603B_0805C CDROM_RIGHT 15 CDROM_LEFT 15 CDROM_COM M 15

C

FOR EMI REQUEST CHANGE TO 0 OHM

L73 1 2 120Z/100M 2012 AGND 1 L88 2 120Z/100M 2012 AGND

11

14M_CODEC

R472 1 0 0402 5%

2 3 1 R516 1M/NA X2 1 2 C959 0402 C953 0402 C952 0402 C945 0402 1 1 1 1 2 1U 10V +80-20% 2 1U 10V +80-20% 2 1U/NA 10V +80-20% 2 0.1U/NA 16V 10% 31 32 33 34 40 43 44 45 46 47 48 24.576MHZ/NA TXC8X4.5 274012457406 2 PC_BEEP 0402 12

CD-GND XTL-OUT JD2 PC-BEEP JD1/GPIO1 AUX-L VRDA FRONT-MIC2 NC_0 FRONT-MIC1 NC_1 CEN-OUT LFE-OUT JD0/GPIO0 XTLSEL SPDIFI/EAPD SPDIFO AUX-R LINE-OUT-L LINE-OUT-R PHONE MONO-OUT S-OUT-L S-OUT-R AFILT1 AFILT2 DVSS1 DVSS2 AVSS1 AVSS2 VREF VREFOUT ALC655 PQFP48_0.5MM

2 0 0402

R546 6.8K 0402 5% 2 2

R537 6.8K 0402 5% 2

R549 6.8K 0402 5%

GND

GND

L65 1 AGND AGND AGND R559 1 0402 1 1 10K/NA 2 5% MODEM_SPK MONO_OUT C933 1000P/NA 0402 10% 50V 2 R560 1K/NA 0402 5% 1 GND 120Z/100M 2012 AGND GND 2 1

L62 2 120Z/100M 2012 AGND

1

C477 22P/NA 0402 +/-10% 50V

1 GND 2

C504 22P/NA 0402 +/-10% 50V

GND

2

AGND

C939 +80-20% 0402 C940 41 +80-20% 0402 C962 29 0402 C960 30 0402 27 20mil 28

C518 0.1U/NA 0402 10% 16V

2

21 21

SUB_OUTL SUB_OUTR

SUB_OUTL SUB_OUTR

R497 1 0402 R503 1 0402

0/NA 2 5% 0/NA 2 5% 0 5% 0 5%

2

AGND

AGND

AOUT_L AOUT_R

R1130 1 4.42K 2 0402 5% R1127 1 4.42K 2 0402 5% 1 R1126 27K/NA 0402 5% 2 2 1 R1129 27K/NA 0402 5%

R1135 1 0402 R1128 1 0402

2 2

AMP_LEFT AMP_RIGHT SUB_LEFT SUB_RIGHT

21 21 21 21

GND

26 42

4 7

B

GND

R1124 2

0 0402

1 5% GND

21 21

EAPD SPDIFOUT

C963 1U 0402 +80-20% 10V

1

1

R1123 2 0/NA 0402

1 5%

1

R542 5.6K 0402 5% 2

C967 0.1U 0402 10% 16V

1 C966 1U AGND 0402 +80-20% 10V 2

JD0

2

B

AGND AGND

2

AGND R535 R532

AGND 1 0402 1 0402 0 0 2 2 MIC_VREF 5% 2464_VREF 5% AGND 2464_VREF 21 R324 LINE_IN/L LINE_IN/R 1 1 1 C159 100P/NA 0402 +/-10% 50V 1 1 5% 0 2 L53 0402

273000130006

BEAD_600Z/100M 0603D 1 2 R.CH 1 2 0603D L.CH 5 J721 4 3 6 2 1 RA/D6/6P 2SJ-SB2014D3 CONN_JACK_SB2014 291000920605 L751 2 120Z/100M 1608 1

1 R519 2 L76 5% 0 0402 C499 100P/NA 0402 +/-10% 50V 2 R325 22K 0402 1% 2 R520 22K 0402 1%

BEAD_600Z/100M 1 1 1 2 C498 100P 0402 +/-10% 50V C330 100P 0402 J10 +/-10% 50V CAGND 2 1

2

2

J717 MONO_OUT 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 C926 0.1U 0402 10% 10V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 FM/0.8MM/H2.4 AMP C-179373 291000023008 2 1

+3V

+5V R1134 1 0/NA 1 C913 0.1U 0402 10% 10V MODEM_SPK 5%

MDC

2 0402 2

J11

CAGND AGND 2

2

CAGND CAGND

AGND

+3V

+3VS

R1132 1 4.7K

0402 2 5%

GND R1131 1 22 5% 2 0402 R1121 1 22/NA 2 0402 5% R1120 1 22 1 ACSYNC ACSDIN1 ACSDIN1 14 J715

L725

120Z/100M/NA 2 1 2012

A

A

1

1

2

C927 0.1U 0402 10% 10V

2 1 R1136 1K 0402 5% HDR/MA-2 ACES 85204-0200 291000020206 1 5

3

5% 2 0402ACBITCLK

CLOSE TO MDC

R1133 0/NA 0402 5%

C912 10P/NA 0402 +/-10% 50V

L724 50UH CHOKE_WLT04020201 120Z/100M/NA 2 1 2012 1 F2 2

R849 560-2010/NA 0805 2

1

ACSDOUT ACRST#

C148 1 C806 1 MODEMP MODEMN

2 1808 2 1808 MODEMP MODEMN

1000P 1000P 16 16

2KV 10% 2KV 10%

1

GND_45

2

2

L721

2

JP, use 4pcs of 2kV 1000P cap US, use 2pcs of 2kV 1000P cap UK, use 4pcs of 3kV 1000P cap

2

2

Title

GND

GND

GND

GND

GND

MINISMDC014-2 POLYSW_MINISMDC110

8050 MOTHER B/D

Size C Date: Document Number PCB 316680900001/ASSY 411680900011 Sheet 20 of 34

1

Rev R01

Monday, December 29, 2003

5

4

3

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

+3V

+5V 1

AUDIO AMPLIFIER

1 1 R477 100K 0402 5% +5V +5V AMP_SHUTDOWN R1239 4.7K 0402 5% 2 2 3 OPTIN# 1 AMP_OFF 2 R1 Q52 1 BAW56 288100056017 2 C977 1U 0402 10V 3 1 AMPVDD 1 1 1 + C466 D715 2 R1158 1.3M 0402 1% SPK_OFF# L67 1 2 120Z/100M 2012 +5V

DEVICE_DECT#

DECT_HP#/OPT

REMARK

2

0

0

HP in OPT in no this condition on device

D

D22 20 13,24 EAPD SPK_OFF 1 2 BAT54C D27 A RLS4148 K R454 1K 0402 5% 1 3 AMP_OFF 1

3 Q38 DTC144TKA 288202240001

2

R1

0

1

1

0

1

1

D

22

KBC_MUTE

2

VA

GND

1 R322 4.7K 0402 5% 2 DEVICE_DECT# AGND DECT_HP#OPT

GND GND

100U 6.3V L752 20% 1 2 120Z/100M 2012 CAGND 1 1 L52 2 600Z/100M 2 600Z/100M L50 1608 1608

2 R1183 10K 0402 600Z/100M 2 1608 2 1608 600Z/100M L55 1608 1 600Z/100M 2 2 1608 5 4 2 3 1 8 7 9 Drive IC LED L754 1 L755 1 1

DTC144TKA 288202240001

C949 0.1U 0402 10% 16V

C934 0.1U 0402 10% 16V

2

2

2

J7 1 2 HDR/MA-2 ACES 85204-0200 291000020206 J3 L14 L16 1 1 2 600Z/100M 2 600Z/100M 1608 1608 1 2 HDR/MA-2 ACES 85204-0200 291000020206 20 SPDIFOUT

R1302 1

0 0402 J720

2

CAGND

AGND 20 AMP_RIGHT AMP_RIGHT C492 1 0402 C497 1 0402 1U 10V +80-20% 1U 10V +80-20% 1 2 100K 1 2 100K/NA 1 2 100K 1 2 100K/NA 2 1U 10V +80-20% 2 1U 10V +80-20% 20 23 8 14 0402 0402 0402 0402 5% 5% 5% 5% 2 3 15 17 20 2 R367 10K 0402

C

U524 RHPIN RLINEIN RIN PC-BEEP VDD GAIN0 GAIN1 SEBTL HP/LINE LLINEIN LHPIN LIN G6 G7 G8 G9 G10 TPA0212_GND TSSOP24_TPA0102 BYPASS SHUTDOWN GND0 GND1 GND2 GND3 LOUT+ LOUTG1 G2 G3 G4 G5 ROUT+ ROUTPVDD0 PVDD1 21 16 7 18 1 1 19 11 22 1 12 13 24 4 9 1 25 26 27 28 29 2 1 1 1 C485 1 0402 SPK_OFF# AGND 2 1U 10V +80-20% 2 ROUT+ ROUT-

AGND

C935 2 0402 C950 2 0402 AMPVDD AMPVDD

1 1 R1159 R1160 R1161 R391

L757 1 600Z/100M 1 C1003 100P/NA 0402 +/-10% 50V

VA

GND R329 2 22 R528 2 22 1 0402 1 0402 5% 5% L80 L78 2 600Z/100M 2 600Z/100M 1608 1608 1

2

AGND AMP_LEFT C484 1 0402 C480 1 0402 C493 1 0402 AGND 2 1U 10V 2 1U 10V 2 1U 10V

100U 6.3V 20%

100U 6.3V 20%

2

2

+ C474 2

+ C489

GP1FD310TP SHARP CONN_GP1FD310TP L758 600Z/100M 1608

AMP_LEFT

5 6 10 30 31 32 33 34 AGND

1 1

+3V Q711 288221371002 1 AGND 1 C978 1U/NA 0402 10V +80-20% 2

L759 600Z/100M 1608

DEVICE_DECT

DEVICE_DECT#

2

R1

Q23 1 DTC144TKA 288202240001

R529 1K 0402 1% 2

R328 1K 0402 1%

C150 100P 0402 10% 50V

C503 100P 0402 10% 50V

C354 100P/NA 0402 10% 50V

C356 100P/NA 0402 10% 50V

DTA144WK 1 SOT23AN_1 2 R1185 10K 0402 1 2

1

1

3

CAGND

1

C

3

2

2

2

AGND AGND AGND AGND AGND CAGND CAGND

2

OPTIN#

GND 3

AGND

R1

Q713 DTC144TKA 288202240001 2

DECT_HP#OPT

1

DEVICE_DECT#

SUBWOOFER AMP(LM4871)

+5VS_SUBAMP 1 C471 1 1000P SUB_OUTR C496 1 0402 C483 1 0402 0.22U 2 +80-20% 16V 0.22U 2 +80-20% 16V R496 0402 1 10.2K 1% 2 R502 0402 1 10.2K 1% 2 R1122 1 22.1K 0603 1% U725 Q35 2N7002/NA G R451 2 5% 1 0402 10K/NA 3 4 2 1 7 9 10 11 12 1 +IN -IN BYPASS SHDWN GND GND1 GND2 GND3 GND4 LM4871 LLP8A VO1 VO2 VDD GND5 GND6 GND7 5 8 GND 6 13 14 15 1 2 C930 1U 0402 +80-20% 10V R26 R27 1 1 0 0 1 D5 1 ESD0603/NA 1 2 2 0805 2 0805 HDR/MA-2 ACES 85204-0200 291000020206 J705 2 AGND 2 2 0603 10% 120Z/100M 2012 + C951 100U 6.3V 20% GND 1 JO10 2 2 1 L63 2 D6 1 ESD0603/NA JO12 2

B

+5V

B

USE 3K 1% R506 1 2 3K/NA 0402 5% R507 18K 0402 1% SUB_OUTL AGND AGND 1 1 C487 2 D 1

SUB_OUTL

R521 1

0 0402

2

USE 2200P 10% 1

AMP_SHUTDOWN DEVICE_DECT

D17 D19

A

K

R1125 1

VA 2

1

8

AGND SUB_OUTL

1

C469 0.1U 0402 +80-20% 50V

1

C494 2200P 0402 +/-20% 50V

1U/NA 10V 0805 2

R471 D 1M/NA S 0402 5%

0 0402

2

RLS4148 A K RLS4148

2

S

VA 2

C345 1U/NA 0402 +80-20% 10V

C941 4.7U +80-20% 0805

2

C490 20 SUB_LEFT 1 2 0.15U 0603 1

R509 2 1%

2464VREF1

3 2

+ -

1

R460 47K/NA 0402 5% 1 2

AGND AGND AGND

22.1K 0402

U19A LMV822 MSOP8

4

AGND

C462 0.1U/NA 0402 +80-20% 50V

3

Q30 R1

TP49 2 1 R510 R511 1 100 2 0402 1% 1 C500 2 1% 2464VREF1

2

DTC144TKA/NA

1

2

USE 3K 1% USE 2200P 10% 1 R478 1

A

1

AGND R461 1 R462 18K 0402 1% 3K/NA 0402 5% 1U/NA 10V 0805 2 2 1 C479 2 Q36 2N7002/NA G R459 2 5% 1 0402 10K/NA SUB_LEFT AGND 7 SUB_OUTR AGND SUB_RIGHT R512 1 0/NA 2 0402 5% SUB_OUTR R491 1 0/NA 2 0402 5% SUB_OUTL D 1 AGND R489 D 1M/NA S 0402 5%

20

2464_VREF

2

22.1K 0402 10U 6.3V 0805 10%

1

0 0402

2

2

R463 1 2 1% 2464VREF2

A

VA 8

C470 2200P 0402 +/-20% 50V

AGND

22.1K 0402

2

SUB_OUTR

S

2

C482 20 SUB_RIGHT 1 2 1 0.15U 0603

R479 2 1%

2464VREF2 RIN_2464

5 6

SUB_OUTL SUB_OUTR

20 20

+ -

22.1K 0402

U19B LMV822 MSOP8

4

Title

AGND Size C Date:

5 4 3 2

8050 MOTHER B/D

Document Number PCB 316680900001/ASSY 411680900011 Sheet 21 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

J5 KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 KO8 KO9 KO10 KO11 KO12 KO13 KO14 KO15 KI7 KI6 KI5 KI4 KI3 KI2 KI1 KI0 C543 100P C541 100P C539 100P C537 100P C535 100P C533 100P C531 100P C529 100P C527 100P C525 100P C523 100P C521 100P 1 1 1 1 1 1 1 1 1 1 1 1 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V C542 100P C540 100P C538 100P C536 100P C534 100P C532 100P C530 100P C528 100P C526 100P C524 100P C522 100P C520 100P 1 1 1 1 1 1 1 1 1 1 1 1 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V GND FPC/FFC/1MM/26P ACES 85202-26-00 291000152603 GND 1 1 1 C93 10U 16V 1206 C94 0.1U 0402 +80-20% 50V R88 10K 0402 5% G 12 1 C104 0.1U 0402 +80-20% 50V 2 R87 0 0402 5% FAN# G 13,19,23 LAD[0..3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 KO8 KO9 KO10 KO11 KO12 KO13 KO14 KO15 KI7 KI6 KI5 KI4 KI3 KI2 KI1 KI0 KBD_US/JP# 13,24 GND 13 HRCIN# VDD3 1

20MIL

L61 2 120Z/100M/NA 0805C

VDD3_AVREF

Pull HIGH at Other End

+3V 1 +3V 2

WINBOND KBC

+VCC_CORE 2 13 BATT_DEAD# +3V 3 1 +3V 2 SB_THRM#

PULL HIGH at SB END

DTC144TKA SOT23AN_1 288202240001 1 H8_THRM# 1 13,24 SCI# 3 H8_RSMRST G Q32 R1 2 H8_SCI S D D S

RSMRST#

13,25

R1

+KBC_CPUCORE R424 1 22 0402 5% C453 0.1U 0402 +80-20% 50V GND

R395 10K 0402 2 3

Q27 R394 1 0/NA 2 0402 +3VS DTC144TKA SOT23AN_1 288202240001 1 Q706 R267 0402 1 0/NA 2 5% 13,24 WAKE_UP# H8_HRCIN# Q26 DTC144TKA SOT23AN_1 288202240001 WAKE_UP# 3 R381 0402 GP51/INT20#/S0 GP47/SRDY1#/S1 GP44/RXD GP45/TXD GP70/SIN2 P71/SOUT2 GP72/SCLK2 GP73/SRDY2#/INT21 GP74/INT31 GP75/INT41 GP20/FD0/LPCEN GP21/FD1 GP22/FD2/SDA1/RXD1 GP23/FD3/SCL1/TXD1 GP24/FD4 GP25/FD5 GP26/FD6 GP27/FD7 GP56/DA1/PWM01 GP57/DA2/PWM11 GP60/AN0/INT5 GP61/AN1/INT6 GP62/AN2/INT7 GP63/AN3/INT8 GP64/AN4/INT9 GP65/AN5/INT10 GP66/AN6/INT11 GP67/AN7/INT12 RESET# XIN XOUT VREF VCC VSS AVSS CNVSS 16 18 H8_PWRON 2 H8_HRCIN# K RLS4148/NA T_DATA T_CLK SUSC# H8_THRM# H8_WAKE_UP# BATT_G# BATT_R# EXTSMI# CAP# NUM# SCROLL# BLADJ H8_I_CTR PWRBTN# KBC_RI# AC_POWER# H8_I_LIMIT H8_PROCHOT# +KBC_CPUCORE H8_RESET# KBC_X+ KBC_XVDD3_AVREF VDD3 72 71 30 73 24 R414 1 0/NA 2 5% 0402G_DFS 1 1 C449 0.1U 0402 +80-20% 50V C448 0.1U 0402 +80-20% 50V 1 C445 10U 0805 6.3V 10% H8_RESET# 25 C454 0.1U 0402 +80-20% 50V H8AGND 23 23 H8_PWRON_SUSB# 25 13,26,27 A A20GATE D20 H8_LIDSW# H8_PWRON 12 26,27 2

Q42 FDV301N SOT23_FET

D

D

DTC144TKA SOT23AN_1 288202240001 GND VDD3S 1 R453 10K 0402 5%

2

1

33

BATT_DEAD

2

R1

Q39 DTC144TKA SOT23AN_1 288202240001 1

GND

2

3

R1

R925 10K 0402

R1 1 H8_WAKE_UP# 0/NA 2 5% 13 ICH_PWRBTN# 3

+5V

11 PCICLK_KBC 13,14,17,19 SERIRQ LAD[0..3] LAD3 LAD2 LAD1 LAD0 R393 1 0 2 0402 SW_VDD3 BATT_DEAD# H8_ADEN# LEARNING H8_SUSB H8_SCI BAT_DATA BAT_CLK 12 H8_ENABKL 33 CHARGING H8_ENABKL CHARGING 70 69 68 67 66 65 64 63 17 15 14 23 22 19 3 2 27 26 13 12 KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 KO8 KO9 KO10 KO11 KO12 KO13 KO14 KO15 KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 62 61 60 59 58 57 56 55

U16 GP80/SD0 GP81/SD1 GP82/SD2 GP83/SD3 GP84/SD4 GP85/SD5 GP86/SD6 GP87/SD7 GP50/A0 GP52/INT30#/R GP53/INT40#/W GP42/INT0/OBF00 GP43/INT1/OBF01 GP46/SCLK1/OBF1 GP76/SDA GP77/SCL GP40/XOUT/PWM2 GP41/XCIN/PWM3 GP54/CNTR0 GP55/CNTR1 GP0/P3REF/FA0 GP1/FA1 GP2/FA2 GP3/FA3 GP4/FA4 GP5/FA5 GP6/FA6 GP7/FA7 GP10/FA8 GP11/FA9 GP12/FA10 GP13/FA11 GP14/FA12 GP15/FA13 GP16/FA14 GP17/FA15 GP30/PWM0/FCTRL0 GP31/PWM10/FCTRL1 GP32/FCTRL2 GP33/FCTRL3# GP34/BANK0 GP35/BANK1 GP36/CE# GP37/OE# W83L950D

1

2

Q31 R1 2 ICH_PWRBTN

0 21 R439 1 0402 20 9 8 7 6 5 4 38 37 36 35 34 33 32 31 11 10 1 80 79 78 77 76 75 74 25 28 29

A20GATE

13

13 KBC_PCIRST# 13,19,23 LFRAME#

J707

GND 1 2 3 D703 A K

3V LEVEL

25,32 ADEN# D21 K

25 32

SW_VDD3 A RLS4148 LEARNING

T_DATA H8_RSMRST ICH_PWRBTN T_CLK

DTC144TKA SOT23AN_1 288202240001

2

2

S

GND

FAN

Q14 SI2301DS

D

2

H8_SUSB BATT_G# BATT_R# EXTSMI# CAP# NUM# SCROLL# 12,23 12,23 13,24 23 23 23 VDD3_AVREF 3 GND D18 BAV70LT1 SOT23N 288100070006 3 Q49 R1 2 SUSB# 13,17,23,25

+3V

1.25MM/ST/MA-3 ACES 85205-0300 291000010303 GND

C

1

RLS4148

10MIL

R95 10K 0402 5% 1 R99 R96 33 1M/NA 0402 0402 5% 5%

1

1

2

1

1

2

1

2

1

1

GND

2

2

Processor Hot Protection

+VCC_CORE 2 DTC144TKA 288202240001 HPROCHOT# 1 R1

2

H8_PROCHOT# 3 Q29

2

2

2

2

11

G

B

H8_THRM_DATA

2

S D S Q33

D G

2

2

H8_THRM_CLK

KBC_RI# 32 33 4,12 I_LIMIT I_CTRL BLADJ I_LIMIT I_CTRL R428 1 R483 1 0 0 2 0402 H8_I_LIMIT 2 0402 H8_I_CTR BLADJ R450 2 10K/NA 1 0402 +3VS

16

1

1

1

GND

C478 0.1U 0402 +80-20% 50V

L68

BEAD_600Z/100M 0603D 1 2

C450 22P 0402 +/-10% 50V

8MHZ TXC8X4.5

1

1

2

2

2

THERMAL SENSOR / FAN CONTROLLER

+3VS 5 6 7 8 10K*4 4 1206 3 2 1 RP719 +2.5VS_DDR 2 R1002 0 1 +2.5VIN/SMBALERT VCC TP720 1 FAN# 15 5 8 6 7 4 9 PWM1 PWM2/SMBALERT PWM3/ADDRESS ENABLE TACH1 TACH2 TACH3 TACH4/ADDRESS SELECT/THERM ADT7460 QSOP16B D1+ D1D2+ D2GND 14 +3VS U706

A

1

H8_THRM_DATA H8_THRM_CLK

2

1

TP718 TP719 14,25 THERM_ERR#

1 FAN_SPEED 1 THERM_ERR#

2 1 C871 4.7U 0805 +80-20% 2

1

2

2

5

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

D S

2

FAN_SPEED

23 BATT_LED# 25 KBC_PWRON_VDD3S

DTC144TKA SOT23AN_1 288202240001

C

C133 0.1U 0402 +80-20% 50V

AC_POWER#

12,23

GND

BAT_VOLT BAT_TEMP BAT_CLK BAT_DATA

8 7 6 5

RP45

1 2 3 4

C459 0.1U 0402 +80-20% 50V H8AGND

BAT_V BAT_T BAT_C BAT_D

32 32 32 32

22*4 RPSOA_8C

For External flash

VDD3

VDD3 BAT_CLK BAT_DATA R448 1 2.7K R449 1 2.7K 2 1% 0402 2 1% 0402 VDD5

HPROCHOT#

2

R447 GND GND 0/NA 0402 5% R446 150 0402 1%

R0A

add

BAT_CLK BAT_DATA

R419 1 2.7K/NA 2 1% 0402 R455 1 2.7K/NA 2 1% 0402

C Version 284583950002

PQFP80_0.5MM +5VS 2N7002 BAT_DATA 2N7002 KBC_XR486 1 0 0402 2 S D S D Q40 BAT_CLK KBC_RI# R445 1 0 0402 2 KBC_MUTE 21 KBC_X+ R404 1M 2 0402 5% X1 1 2 C447 22P 0402 +/-10% 50V +5VS

KBC IC :284583950002 F/W ASSY:481677700002

Closed to KB CONN

H8_THRM# R390 0402 H8_ENABKL R425 0402 1 10K/NA 2 5% 1 10K/NA 2 5%

+3V

R473 1

0 0402

ADD-->R0B

B

+5V R430 10K 0402 5% T_DATA T_CLK KI5 R482 2 10K 5% 1 0402 R481 2 10K 5% 1 0402 R385 1 0/NA 0402 5% 2 GND

GND 0:internal flash 1:external flash

0:for external flash

H8_SCI R475 0402

1 10K 5%

2

VDD3

GND H8AGND GND

GND +3VS H8_PROCHOT# R413 RP46 2 10K 5% 1 0402 1 H8_ADEN# 2 BATT_DEAD# 3 PWRBTN# 4 5 RP10KX8 RPSOE_10 RP44 VDD3 KI4 KI5 KI6 KI7 10 9 8 7 6 1206 4.7K*8 1 2 3 4 5

POWER BUTTON

SW2 PWRBTN# R7 1 1K 0402 5% C9 1000P 0402 +/-20% 50V X7R 2 1 3 2 4 5 TC010-PSS11CET 297004010001 GND

VDD3 H8_RSMRST H8_SUSB ICH_PWRBTN

10 9 8 7 6

VDD3

16 1

SDA SCL

KI0 KI1 KI2 KI3 VDD3

A

3 13 12 11 10

C869 2200P 0402 +/-20% C728 50V 2200P 0402 +/-20% 50V

CPU_THERMDA 2 CPU_THERMDC 2 VGA_THERMDA 9 VGA_THERMDC 9

GND

Title

8050 MOTHER B/D

Size C Document Number PCB 316680900001/ASSY 411680900011 Sheet 22 of 34

1

Rev R01

GND

4 3 2

Date:

Monday, December 29, 2003

5

4

3

2

1

FWH TOUCH_PAD

D

+3V

D

11 PCICLK_FWH 13 FWH_PCIRST# 1 1 R387 1 8.2K 5% 2 0402 GND 4 3 2 1 32 31 30 U15 GND GND GND C908 4.7U 0603 6.3V +80-20% C897 0.1U 0402 10% 10V 1 C902 0.1U 0402 10% 10V 2 LFRAME# +5V L716 2 120Z/100M 2012 1 50V 22 T_DATA L36 1 120Z/100M 1608 L37 SW4 1 3 1 120Z/100M 1608 2 2 TP_DATA TP_CLK R132 1 0/NA 2 5% 0402G_DFS R151 1 0/NA 2 5% 0402G_DFS TP_LEFT TP_RIGHT HDR/MA-6 ACES 87151-0607 GND DQ1/LAD1 DQ2/LAD2 GND DQ3/LAD3 DQ4/RSV DQ5/RSV DQ6/RSV TP_VDD 1 1 F701 2 GND 0.5A/POLYSW C771 2 2 R402 1 8.2K 5% 2 0402 R411 1 8.2K 5% 2 0402

miniSMDC050

0.1U 0402 +80-20% GND J4 6 5 4 3 2 1 +3V

22 T_CLK

R427 1 8.2K 5% 2 0402 R422 1 8.2K 5% 2 0402 R417 1 4.7K 5% 2 0402 R408 1 4.7K 5% 2 0402 R403 1 8.2K 5% 2 0402 R412 1 8.2K 5% 2 0402 R418 1 8.2K 5% 2 0402 R423 1 8.2K 5% 2 0402

A8/RSV A9/RSV RESET# VPP VDD R-C#/CLK A10/GPI4

SW_LEFT

2 4 5

5 6 7 8 9 10 11 12 13

A7/RSV A6/RSV A5/RSV A4/RSV A3/RSV A2/RSV A1/RSV A0/RSV LAD0/DQ0

MODE GNDA VCCA GND VDD OE#/INIT# WE#/LFRAME# NC DQ7/RSV

29 28 27 26 25 24 23 22 21

R364

1 4.7K 5%

2 0402 GND INIT# 13,19,22

1

2

2

2

2

1

TC010-PSS11CET 297004010001 D29 1 2 ESD0805A/NA SW5

C

1

1

1

1

2

C143 C144 C154 C172 47P 47P 47P 47P 0402 0402 0402 0402 +/-10% +/-10% +/-10% +/-10% 50V 50V 50V 50V GND

+3V

GND 1 JO18 JO20 1 LAD0 LAD1 LAD2 LAD3

2 R1089 1 SST49LF004A R1084 1.5K 0402 5% C 2 B Q708 MMBT3904L 288203904022 E E R1073 2,13 HINIT# 1 330 0402 5% 2 B 330 0402 5% INIT# C 1

1 3

2 4 5 TC010-PSS11CET 297004010001 D23 1 2

JO19 2 2

JO21

13,19,22 13,19,22 13,19,22 13,19,22

LAD0 LAD1 LAD2 LAD3

14 15 16 17 18 19 20

SW_RIGHT

C

GND

SYS BIOS Vendor List: SST49LF004A : 283467490001 GND

GND

Q718 MMBT3904L 288203904022

2

ESD0805A/NA GND J8 TP_RIGHT TP56 TP57 1 1 TP_LEFT TP_CLK TP_DATA TP_VDD 1 2 3 4 5 6 7 8 9 10 11 12 HDR/MA-12/NA ACES 87151-1207 291000141204 15

2

LED

D721 R415 AC_BATT_LED# HDD_LED# 1 0/NA R416 1 0 D32 CL-190G 15 12,22 CD_LED# BATT_G# R458 1 0 R465 1 0/NA 2 0402 D33 CL-190G

B

2 0402 2 0402 K A

R433 1 0402 2 220/NA 5% R553 1 0402 2 5% 470 R434 1 0402 2 220/NA 5% R554 1 0402 2 5% 470

VDD3S +5V VDD3S +5V

15 15

CD_LED# HDD_LED#

2 3 1 BAW56/NA

IDE_LED#

GND

2 0402

K

A

When 8050N ADD J722 and DEL J4

B

When 8050 ADD J4 and DEL J722

4 R466 1 0/NA 2 0402 2

D31 VG 3 1 SR 19-22SRVGC/TR8/NA R467 1 0402 220/NA 2 5%

12,22

BATT_R#

VDD3S

R441 1 0402 2 5% 470/NA R420 22 NUM# NUM# IDE_LED# R421 22 22 22 CAP# NUM# SCROLL# CAP# 1 0 R426 1 0/NA R429 SCROLL# 1 0 R432 1 0/NA R457

A

+5V

1 0

2 0402

K D34 CL-190G

A

R555 1 0402 220

2 5%

+3V

2 0402 2 0402 2 0402 2 0402

K D35 CL-190G K D37 CL-190G

A R556 1 0402 220

2 5%

A

R557 1 0402 220

2 5%

22

CAP#

+3VS 2 0402

+3VS

+3VS

A

AC_BATT_LED# R468 BATT_POWER#

1 0/NA 2 0402

12 BATT_POWER#

1 0

Q720 DTC114TKA 288202215001 R1 2

14

14

4

74AHC14_V TSSOP14 3

6

74AHC14_V TSSOP14 5

14

U703B

U703C

U703D 74AHC14_V TSSOP14 9 1 R1152 1M

3

3

8

13,17,22,25 SUSB# 22 BATT_LED# BATT_LED#

2

R1

Q719 DTC114TKA 1 288202215001 1 1 7 7 7

2 0402 5%

R1303 2 12,22 AC_POWER# 1 0/NA 2 0402 GND

C947 4.7U 0805 +80-20%

Title GND GND Size C

8050 MOTHER B/D

Document Number PCB 316680900001/ASSY 411680900011 Sheet 23 of 34

1

Rev R01

1 R1140 180K

5 4 3

2 0402

5%

2

Date:

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

PULL -HIGH

PCI PULL HIGH

+3V 8.2K 8.2K 8.2K 8.2K

D

AGP PULL HIGH

7,13 13,17 13,17 13,19

1 1 1 1 +3V

R187 R847 R1119 R808

2 2 2 2

0402 0402 0402 0402

PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD#

GPIO PULL HIGH

+3V 12,13 CRT_IN# CRT_IN# 0402 1 R804 0402 1 R916 ICH_GPI5 AGPBUSY# KBD_US/JP# STP_AGP# 0402 1 R815 0402 2 R788 0402 1 R165 0402 2 R780 0402 1 R410 2 8.2K 2 10K 5% 2 8.2K 1 20K 1% 2 10K 5% 1 20K/NA 1% 2 8.2K/NA

8.2K 8.2K 8.2K 8.2K

1 R191 1 R194 1 R841 1 R868 +3V

2 0402 2 0402 2 0402 2 0402

PCI_INTE# PCI_INTF# PCI_INTG# PCI_LOCK#

13,16 13,17,19 13,18 13

WHEN USE INTEGRATE VGA DEL ALL RESISTOR

+1.5V

D

13 SB_CARD_PME# 13 ICH_GPI5

4,7,13 AGPBUSY# R180 R1005 R179 R814 R803 2 2 2 2 2 0402 0402 0402 0402 0402 PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_REQ4# 13,17 13,18 13,19 13,16 13 13,22 KBD_US/JP# 7,13 3,13 STP_AGP# B/CB#

8.2K 8.2K 8.2K 8.2K 8.2K

1 1 1 1 1 +3V

100K/NA 1 R837 VDD3S 100K/NA 1 R866

2 0402 2 0402

5% 5%

AGP_AD30 AGP_AD13

4,7 4,7

8.2K 8.2K 8.2K 8.2K 8.2K

1 1 1 1 1 +3V

R186 R207 R802 R201 R200

2 2 2 2 2

0402 0402 0402 0402 0402

PCI_GNT0# PCI_GNT1# PCI_GNT3# PCI_GNT4# PCI_GNT2#

13,17 13,18 13,16 13 13,19

13,22 13

EXTSMI# SMBALERT#

0402 1 R396 0402 2 R309 0402 1 R464 0402 1 R382

SMBALERT# SCI#

13,22

13,22 WAKE_UP# R211 R231 R230 R241 R244 R212 R218 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 PCI_FRAME# PCI_SERR# PCI_IRDY# PCI_PERR# PCI_DEVSEL# PCI_TRDY# PCI_STOP# 13,16,17,18,19 13,16,17,19 13,16,17,18,19 13,16,17,18,19 13,16,17,18,19 13,16,17,18,19 13,16,17,18,19

2 10K 5% 1 10K 5% 2 10K 5% 2 10K 5%

GND

+2.5VS_DDR JS708 1 2 SHORT-SMT4 JS709 2 SHORT-SMT4 JS710 2 SHORT-SMT4

+2.5VS_DDR_P

8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K

1 1 1 1 1 1 1

+VCCP

1 13 CPUPERF# 0402 1 R280 0402 1 R1004 2 200 5% 2 8.2K 5%

13,16,17,19 PCLKRUN#

+3V

1

C

+3VS R284 1 0/NA 2 5% 0402G_DFS R283 1 0/NA 2 0402 VDD3S +3V JS711 1 2

+3VS_P +1.25V_DDR JS11 1 2 SHORT-SMT4 JS12 1 2 SHORT-SMT4 +1.25V_DDR_P

C

13 GPIO27 13 GPIO28 13,21 SPK_OFF

GPIO27 0402 1 R282 GPIO28 0402 1 R281 SPK_OFF 0402 1 R905

2 8.2K 2 8.2K

2 8.2K R897 1 R906 1

0/NA 2 0402 0 2 0402

+3VS VDD3S

1

SHORT-SMT4 JS713 2 SHORT-SMT4 JS715 2 SHORT-SMT4 +1.8V

1 +3V

+1.8V_P JS716

14,19 WIRELESS_PD#

R1098 1 10K 0402 5%

2 +3V +5VS +5VS_P 1

2

JS718 14,15 14,19 14 14 IDERST# MINIPCI_ACT# GPIO43 GPIO42 R843 R851 R840 R842 2 2 2 2 10K 10K 10K 10K 1 1 1 1 0402 0402 0402 0402 5% 5% 5% 5% 1 2 SHORT-SMT4 JS719 2

1

SHORT-SMT4 JS717 2 SHORT-SMT4

1 +3V

+1.35V JS720 1 2 SHORT-SMT4 JS722 2 SHORT-SMT4

+1.35V_P

7,12,14 7,12,14 7,12,14 7,12,14

PANEL_ID0 PANEL_ID1 PANEL_ID2 PANEL_ID3

PANEL_ID0 10K 1 PANEL_ID1 10K 1 PANEL_ID2 10K 1 PANEL_ID3 10K 1

R11 R12 R13 R14

2 2 2 2

0402 0402 0402 0402

SHORT-SMT4 JS721 1 2 SHORT-SMT4

1

+3V

B

+1.2V/1.0V_M10 R845 1 R232 1 R215 1 14 14 14 2 10K/NA 0402 0402 2 10K 2 10K/NA 0402 MB_ID0 MB_ID1 MB_ID2 MB_ID0 R846 1 MB_ID1 R239 1 MB_ID2 R221 1 0402 2 10K 2 10K/NA 0402 0402 2 10K 1

VGA_1.2/1.0

+1.5V JS723

+1.5V_P

B

JS724 2 SHORT-SMT4 JS726 2 SHORT-SMT4 JS727 2 SHORT-SMT4

1

2

1

SHORT-SMT4 JS725 2 SHORT-SMT4

GND

1

1

+VCCP JS728 1 2 SHORT-SMT4 JS729 1 2 SHORT-SMT4 JS730 2 SHORT-SMT4

+1.05V_P

1.05V

1

A

A

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 24 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

POWER ON PERPHERIAL CIRCUIT

PWR_VDDIN 1 VDD3_AVREF F3 2 8 2 7 3 1 R374 10K/NA 0402 5% 2

D

U14 IN SENSE F/B SHUTDN LP2951-3.3/NA SO8 2 5VTAP OUT ERRGND 6 1 5 4 K 1 1 C383 10U 0805 6.3V 10% C381 0.1U 0402 +80-20% 50V A K D25 RLZ3.6B/NA MLL34B

Q48 SI2301DS D S 1 D S VDD3 S

Q43 SI2301DS D S D PWR_VDDIN U11 8 2 7 3 1 R321 10K 0402 5% Q47 2 DTC144WK 288202237002 IN SENSE F/B SHUTDN LP2951-02 SO8 A 5VTAP OUT ERRGND 6 1 5 4 1 C310 0.1U 0402 10% 10V G VDD5 3 +3VS VDD3S U6 VIN VOUT 1 GND/ADJ AME1117 SOT223 GND R259 1 1K 1 R253 200 0402 1% 2 2 0402 1% GND 2 1 C295 2.2U 0603 +/-10% VDD1.5

FUSE_1206 3216FF-1 1A-1206

G G

1

2

K

D26 UDZS3.6B/NA SOD323 A

D13

2

1

C517 4.7U 0805 +80-20%

R525 100K 0402 5%

2

G

GND U13 1 GND INPUT OUTPUT 3

GND

GND

GND

GND GND 3 GND

22

SW_VDD3

SW_VDD3

R523 1 0 R522 1 0/NA

2 0402 5% 2 0402 5%

2

GND

GND GND

GND

1

C355 10U 1206 10V

2

AMS3107 SOT223 286303107001

2

13,15

PCIRST#0

1

2

UDZ5.6B SOD323

C342 10U 0805 6.3V 10%

2

D

GND GND GND GND U10 MAX809 SOT23N 286300690001 3 1 VCC GND RESET# 2 PWROK 1 4,12,13,17,31

H8 RESET# / RSMRST#

PWROK Q51 Q13 VDD5 SI2301DS D S S 1 D 1 VDD5 C24 2.2U 0603 +/-10% R561 100K 0402 5% R375 10K 0402 5% 2 D7 A K BAS32L 3 1 3 +3VS Q12 R1 2 R25 0/NA 2 5% 1 0402G_DFS 1 Q50 R1 2 R551 1 0/NA 2 5% 0402G_DFS C506 0.01U 0402 +80-20% 50V VDD3S 1 ADEN# A ADEN# 22,32 2 G 1 G 1 VDD5S S VDD3 SI2301DS R1 L71 D S D 1 120Z/100M 2012 L72 C508 2.2U 0603 +/-10% +3VS 2 120Z/100M/NA 2012 1 2 VDD3S DTC144TKA 288202240001 3 VDD3 2 PWROK 4,12,13,17,31 R501 1 Q44 0 0402 5% 2 1 2 THERM_ERR# THERM_ERR# 14,22 +3VS

+3V

C326 0.1U 0402 10% 10V

809S 2.93V

2

R312 100K 0402 5%

2

VDD3

VDD3S

GND GND

R28 100K 0402 5%

C

G

1

1

GND

1

1

2

D24 K BAS32L

R531 10K 0402 5% ADEN# 2 3 4

R456 4.7K/NA 0402 5% Q34 3 2 2

1

R358 4.7K 0402 5% RSMRST# 13,22

2

2

2

1

KBC_PWRON_VDD3S 22 2

IMP811 SOT143

1

H8_RESET# R508 100K 0402 5%

1

2

2

1

2

GND GND

R362 10K 0402 5% 2 2 22 H8_PWRON_SUSB# 13,17,22,23 SUSB#

1

GND R368 10K/NA 0402 5% R480 1 0/NA 2 5% 0402G_DFS R548 1 0/NA 2 0402 5% PWRON_SUSB# PWRON_SUSB# 26,28,29,30,31

2

1

PWRON_SUSB# 1 Q25

2

+5VS

B

U704 AO4403 3 2 1 SO8 8 7 6 5

G DTC144TKA 288202240001 +5V_H D S

C

R1

U21 MN VCC RESET GND 2 1 1

DTC144TKA/NA H8_RESET# 22

R474 294K/NA 0402 1%

DTC144TKA 288202240001 GND

C486 10U/NA 0805 6.3V 10%

+3VS

+5VS

VDD3

GND

GND R366 10K/NA 0402 5% 3 R355 1 0/NA 2 0402 5% VCC_ON

DTC144TKA/NA

R1

+5V 120Z/100M 2 2012 L704 120Z/100M 1 2 2012 C707 2.2U 0603 +/-10% 1 L703

+3VS

U707

+3V 8 7 6 5 1 120Z/100M 2 2012 L706 120Z/100M 1 2 2012 1 1 L707

+2.5VS_DDR U8 4 3 2 1 SOURCE3 SOURCE2 SOURCE1 VIN SI4788CY/NA SO8 U7 GND 8 7 6 5 D G S SI4800DY SO8 3 2 1 DRAIN3 DRAIN1 DRAIN2 GND

For Lan

3 2 1

AO4403 SO8

For ATI VRAM

L46 5 6 7 8 1 120Z/100M 2012 1 L47 1 120Z/100M 2012 GND GND 2 2 2

+2.5V_M10

B

D

1

1

1

1

1

1

1

1

C706 1U 0402 +80-20% 10V

2

2

2

2

2

2

2

2

2

1 100K 0402 5%

2 1

1 100K 0402 5%

2 1

GND

GND GND GND R21 1K 0402 5% 2

R1249 0/NA 0805 GND 2

GND

GND

GG S Q10

D S

2

SI2301DS/NA GG S Q701

2

D

Q721

R707 1K 0402 5%

D

D

D S

Q722 SI2301DS/NA DVMAIN C313 1 0.047U 1 2 0603 2 4

DVMAIN

S

1

GND C16 0.1U 0402 +80-20% 50V

D

D S

2N7002 G OD5 2N7002 G 1 OD3 C708 0.1U 0402 +80-20% 50V

Q18 DTA144WK/NA SOT23AN_SC70_1

D S S

GND

D 2

D

R251 220K 0402 5% GND

R250 1M 1 0402 5%

1

2 R260 1 22K/NA 2 0402 1% Q17 3 D S S 2N7002/NA G PWRON_SUSB#

2

GND R17 PWRON_SUSB#

A

2

1 0 5% 1 0

2 0402 2 0402 5%

OD3 OD5

GND

+3VS

G S

D Q19 S 2N7002

PWRON_SUSB# R18

GND

A

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

2

R15

C13 0.1U 0402 +80-20% 50V

R1248 0/NA 0805

C705 10U 0805C 10V

C710 1U 0402 +80-20% 10V

R705

C712 0.1U 0402 +80-20% 50V

4

1

C715 10U 6.3V 0805 10%

C717 2.2U 0603 +/-10%

C329 1U 0402 +80-20% 10V

1 C284 10U 6.3V 0805 10% C283 2.2U 0603 +/-10%

VCC_ON

S

4

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

G

G

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 25 of 34

1

Rev R01

Monday, December 29, 2003

5

4

3

2

1

DVMAIN JS703 1 2 1 SHORT-SMT4 PL716 1 2 2012 120Z/100M PC791 0.01U 0402 10% 50V

+2.5VS_DDR_P/+1.25V_DDR_P

2

D

1

GND 1 PC801 0.01U 0402 10% 50V GND 2 4.7 0603 1% PR111 +5VS_P PJL2 JP_NET20 1 6 5 D G PC793 1000P 0402 10% 50V 4 2 S 3 PU708A AO4900 SO8 1 2 1 0 0402 5% 2 288100056017 2 1 PD7 BAW56 SOT23N PC67 INTVCC12 1 10U 16V 1206 1 PC66 0.1U 0805 10% 1 4.7 0603 1%

D

2 1 1 PC792 0.01U 0402 10% 50V PC794 10U 1210 25V 20%/X5R 2 1 PC795 1000P 0402 10% 50V 2 PR110 2 5 6 PU709A D G 4 S AO4900 SO8 1 3.0UH SPC-05703 30% PU709B D G 1 2 S AO4900 SO8 SENSE1.25+ SENSE1.251000P 0402 50V 10% 1 1 2 3 PL717 2 1.25V_2 1 .012 2010 1% PR744 2 +1.25V_DDR_P PU15 LTC3728L HVQFN32_1 16 15 14 13 12 11 10 9 2 GND PC799 10U 1210 25V 20%/X5R PJL1 JP_NET20 1 1 PC796 10U 1210 25V 20%/X5R 2 GND PR109 1 2 2 GND 2 1 PC65 0.1U 0805 10% PC68 0.1U 0402 +80-20% 50V 24 23 22 21 20 19 18 17 BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2 25 26 27 28 29 30 31 32 33 34 35 36 37 1 GND GND +2.5VS_DDR_P PR742 1 0.008 2512 1% PC789 + 330U/NA 7343 4V 2 PC788 + 330U 7343 4V 2 1 PC787 + 330U 7343 4V 2 1 PC790 0.1U 0402 +80-20% 50V S 1 2 1 3.9UH SPC-08045 30% PL715 2 PU708B 8 7 D G 2 1 AO4900 SO8 SW1 TG1 PGOOD RUN/SS1 NC2 SENSE1+ SENSE1NC3 SGND1 SGND2 SGND3 SGND4 SGND5 2 2 3

C

NC1 SW2 TG2 RUN/SS2 SENSE2+ SENSE2NC0 VOSENSE2 VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 3.3VOUT ITH2

C

1

7 8

1 PC797 10U 1210 10V 1

K

1

K PD724 BZV55C2V4/NA PC798 + 150U 7243 6.3V A

PD723 BZV55C3V3/NA A

PC70 PC71 1000P 0402 1 2 10% 50V 1000P GND 0402 50V SENSE2.5+ 10% 2 SENSE2.5-

PC800 0.1U 0402 +80-20% 50V

2

1 2 3 4 5 6 7 8

1 1 1 2

2

1

1 PR118 43.2K 0402 1%

2

1

1

GND

PR124 2K 0402 1% PR117 20K 0402 1% 2

PC74 47P 0402 10% 50V

PC73 220P 0402 10% 50V PR121 1K 0402 1%

1

PC75 220P 0402 10% 50V

PR122 15K 0402 1% 2

PC76 PR116 100P 11.8K 0402 0402 +/-10% 1% 50V PR113 20.5K 0402 1% 1 2

1

1

2

2

1

PC69 1000P 0402 10% 50V JS6 1 SHORT-SMT1 2

2

2

2

1

2

2

B

GND PR120 0 0402 5% SGND1

2

PC72

2

B

VDD5 2

VDD5 1 1 PR114 100K 0402 1% 2 G S D PR119 10K 0402 1% D S PQ22 2N7002 2 2 INTVCC1 1 PR112 100K 0402 1% G S D SGND1 D S S PQ21 2N7002 25,28,29,30,31 PWRON_SUSB# R356 0402 1 0 5% 2 1 1 G C367 0.1U/NA 0402 +80-20% 50V 2 PR115 1M 0402 1% 2 SGND1

A A

D

D D S PQ20 2N7002

22,27 H8_PWRON 13,22,27 SUSC#

1

R369 0402 R371 0402

1 1

0 5%

2 1

G PR123 1M 0402 1% 2 S

D S

PQ23 2N7002

0/NA 2 5%

C382 0.1U/NA 0402 +80-20% 50V

2

SGND1

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 26 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

DVMAIN

+3VS_P/+5VS_P

JS704 1 2 1 2012 120Z/100M 1 PC710 0.01U 0402 10% 50V 1 GND 1 PC708 0.01U 0402 10% 50V GND 2 4.7 0603 1% PR11 +5VS_P PJL4 JP_NET20 1 6 5 D G PC707 1000P 0402 10% 50V 4 2 S 3 PU702A AO4900 SO8 1 2 1 0 0402 1 5% 10U 16V 1206 1 PC7 0.1U 0805 10% G 4 S 3 PR707 1 PL702 10UH D124C 20% D G 2 S 1 2 PU701B AO4914 SO8 1 2 5V_2 1 .012 2010 1% 2 +5VS_P 5 6 2 288100056017 2 1 PD1 BAW56 SOT23N PC8 INTVCC02 1 1 4.7 0603 1% PR2 2

D

PL701 2

SHORT-SMT4

D

2

2 1 1 PC709 0.01U 0402 10% 50V PC705 10U 1210 25V 20%/X5R 1 GND 2 1 PC706 1000P 0402 10% 50V 2 D PU701A AO4914 SO8 PU2 LTC3728L HVQFN32_1 16 15 14 13 12 11 10 9 2 GND PC703 10U 1210 25V 20%/X5R 1 PJL3 PC704 10U 1210 25V 20%/X5R JP_NET20 1 2 GND PR3 2 2 PC4 0.1U 0805 10% PC10 0.1U 0402 +80-20% 50V 24 23 22 21 20 19 18 17 1 GND 2 2 GND PR711 1 +3VS_P .012 2010 1% 1 PC719 + 150U 7343 6.3V 2 PL703 10UH D124C 20% PU702B 8 7 D G 2 1 S 1 1 AO4900 SO8 2 1 2 25 26 27 28 29 30 31 32 33 34 35 36 37 BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2 3 2

C

PD708

1

BZV55C4V3/NA 1 2 PC725 + 150U/NA 7343 6.3V 2 A

PC737 0.1U 0402 +80-20% 50V

PC17 PC20 1000P 0402 1 2 10% 50V 1000P GND 0402 50V SENSE3+ 10% 2 SENSE3-

SW1 TG1 PGOOD RUN/SS1 NC2 SENSE1+ SENSE1NC3 SGND1 SGND2 SGND3 SGND4 SGND5

NC1 SW2 TG2 RUN/SS2 SENSE2+ SENSE2NC0 VOSENSE2 VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 3.3VOUT ITH2

C

7 8

1 PC721 10U 1210 10V PC713 + 150U/NA 7343 6.3V 2 1

K

K PD707 BZV55B5V6/NA A

PC717 0.1U 0402 +80-20% 50V

2

PR35 1 1 2

1

2 1000P 0402 50V 10% 1

SENSE5V+ SENSE5V-

1

1

PR41 20K 0402 1% 2

PC23 47P 0402 10% 50V

1

GND

PR42 63.4K 0402 5%

PR46 2K 0402 1% 2

12

1

2

1

1

2

PC24 180P 0402 10% 50V PR54 200K 0402 1%

2

1

PC25 180P 0402 10% 50V

1

107K PC26 0402 47P 1% 0402 10% 50V PR36 19.6K 0402 1%

PR55 200K 0402 1% 2

PC14 1000P 0402 10% 50V JS1 1 SHORT-SMT1 2

2

2

1

2

2

B

1

GND PR48 0/NA 0402 5% SGND0

2

PC19

PC712 + 150U 7343 6.3V

1 2 3 4 5 6 7 8

B

G S VDD5

D S

PQ3 2N7002

2

INTVCC0 G VDD5 S

D D S PQ4 2N7002 1 SGND0 PR10 100K 0402 1% 2 PQ2 D D S S 2N7002 G 1 PR25 0402 PR27 1M 0402 1% 2 R23 0402 1 1 1 0 5% 2 H8_PWRON SUSC# 22,26 13,22,26

PR47 10K 0402 1%

D

1

PR9 100K 0402 1% 2

SGND0

D

22,26 H8_PWRON

R24 0402

1

0 5%

2 1 1

G S

D S

PQ1 2N7002

2

C23 0.1U/NA 0402 +80-20% 50V 2

PR26 1M 0402 1%

C22 0.1U/NA 0402 +80-20% 50V

0/NA 2 5%

2

A

SGND0 SGND0

2

A

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 27 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

+1.5V_P/+1.05V_P

DVMAIN JS10 1 2 1 1 2012 120Z/100M PC31 0.01U 0402 10% 50V GND 1 2 PC739 10U 1210 25V 20%/X5R PJL5 JP_NET20 1 1 SHORT-SMT4

D

PL3 2

D

2

1 PC38 0.01U 0402 10% 50V GND 2 4.7 0603 1% PR713 +5VS_P PJL6 JP_NET20 1 6 5 D G PC30 1000P 0402 10% 50V 4 2 S 3 PU4A AO4900 SO8 1 PC715 0.1U 0805 10% 2 1 0 0402 5% 1 PC718 0.1U 0402 +80-20% 50V 24 23 22 21 20 19 18 17 2 288100056017 2 1 PD705 BAW56 SOT23N PC716 INTVCC32 1 10U 16V 1206 1 PC714 0.1U 0805 10% 1 4.7 0603 1%

1

1

1

PC32 0.01U 0402 10% 50V

PC743 10U 1210 25V 20%/X5R

PC744 10U 1210 25V 20%/X5R 1

2

2

GND PR709 PR708 2 2 5 6 PU6A D G 4 PU703 LTC3728L HVQFN32_1 2

PC40 1000P 0402 10% 50V

2

2

GND

2

GND

1

GND

GND +1.5V_P 1 .012 2010 1% PR719 2 1 3.9UH SPC-08045 30% PL706 2 PU4B 8 7 D G 2 K 1 1 PD710 BZV55C2V4/NA A 2 PC728 PC729 + 220U/NA + 220U 7343 7343 4V 4V 2 1 2 S PC726 1 1000P 0402 50V 10% 1 1 AO4900 SO8 25 26 27 28 29 30 31 32 33 34 35 36 37 SW1 TG1 PGOOD RUN/SS1 NC2 SENSE1+ SENSE1NC3 SGND1 SGND2 SGND3 SGND4 SGND5

BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2

C

2

2

3

C

S AO4900 SO8 1 3.9UH SPC-08045 30% 3 PL707 2 1 .012 2010 1% PR732 2 +1.05V_P

NC1 SW2 TG2 RUN/SS2 SENSE2+ SENSE2NC0 VOSENSE2 VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 3.3VOUT ITH2

16 15 14 13 12 11 10 9 G 2 PC727 1000P 0402 50V 10% 2 2 1

7 8

PU6B D

1 PC749 + 220U 7343 4V 1 PC746 0.1U 0402 +80-20% 50V 2

K PD716 BZV55C2V4/NA A

PC730 0.1U 0402 +80-20% 50V

PC731 2 1000P GND 0402 50V 10%

S AO4900 SO8 SENSE1.05+ SENSE1.051 2

1 PC742 + 220U/NA 7343 4V 2

2

1 2 3 4 5 6 7 8

SENSE1.5+ SENSE1.5-

PR721 6.49K 0402 1% 1 1 PC734 220P 0402 10% 50V 1

12

1

1

2

B

PR715 100K 0402 1% 2 31 VCCP_PWRGD 1

PR726 20K 0402 1% PR717 2 0 0402 5%

PC736 100P 0402 +/-10% 50V

1

2

1

GND

1 PC724 1000P 0402 10% 50V JS701 1 SHORT-SMT1 2

B

+3VS_P

PR718 18K 0402 1%

1

1

2

PR725 2K 0402 1%

PC738 180P 0402 10% 25V PR728 15K 0402 1%

PC735 100P 0402 +/-10% 50V PR722 20K PR727 0402 15K 0402 1% 1% 2 1 2

2

1

2

2

1

2

2

GND PR723 0/NA 0402 5% SGND3

D D S S PQ705 2N7002 1 PR724 10K 0402 1% 2

G VDD5

2

INTVCC3

1

SGND3 PR733 100K 0402 1%

D G D S S PQ703 2N7002 SGND3

D 25,26,29,30,31 PWRON_SUSB# 1 R714 0402 1 0 5% 2 1 G PR730 1M 0402 1% S SGND3

A

2 D S PQ706 2N7002 C714 0.1U/NA 0402 +80-20% 50V 2 2

A

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 28 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

+1.8V_P/+1.35V_P

DVMAIN JS706 1 2 1 1 2012 120Z/100M PC765 0.01U 0402 10% 50V GND 2 PJL7 1 PC766 0.01U 0402 10% 50V GND 2 4.7 0603 1% PR92 +5VS_P PJL8 JP_NET20 1 6 5 D G PC776 1000P 0402 10% 50V 4 2 S 3 PU705A AO4900 SO8 1 2 1 0 0402 5% 2 288100056017 2 1 PD6 BAW56 SOT23N PC53 INTVCC22 1 10U 16V 1206 1 PC52 0.1U 0805 10% G 4 S AO4900 SO8 1 3.0UH SPC-06703 30% 3 PL714 2 1.2V_2 1 .012 2010 1% PR741 2 +1.35V_P

C

PL712 2

SHORT-SMT4

D

2

D

JP_NET20 1 PR90 1 4.7 0603 1% 2 PC777 1000P 0402 10% 50V 2 5 6 PU707A D PU14 LTC3728L HVQFN32_1 GND 16 15 14 13 12 11 10 9 G 1 2 S AO4900 SO8 SENSE1.2+ SENSE1.21000P 0402 50V 10% 1 1 2 PC780 0.1U 0402 +80-20% 50V 2 7 8 1

1

1

1

PC50 0.01U 0402 10% 50V

PC774 10U 1210 25V 20%/X5R 2

PC779 10U 1210 25V 20%/X5R 1

2

2

PR91

GND

1

PC51 0.1U 0805 10%

PC54 0.1U 0402 +80-20% 50V 24 23 22 21 20 19 18 17 BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2

1

GND

C

GND +1.8V_P 1 .012 2010 1% PR739 2 1 3.0UH SPC-06703 30% PL713 2 PU705B 8 7 D G 2 K 1 PD719 2 PC770 + 150U 7343 6.3V 1 S 1 1 AO4900 SO8 25 26 27 28 29 30 31 32 33 34 35 36 37 SW1 TG1 PGOOD RUN/SS1 NC2 SENSE1+ SENSE1NC3 SGND1 SGND2 SGND3 SGND4 SGND5

2

2

3

2

NC1 SW2 TG2 RUN/SS2 SENSE2+ SENSE2NC0 VOSENSE2 VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 3.3VOUT ITH2

PU707B D

1 PC783 + 150U/NA 7343 6.3V 2

K PD722 BZV55C2V4/NA A

BZV55C2V4/NA

PC767 0.1U 0402 +80-20% 50V

PC56 PC59 3300P 0402 1 2 10% 50V 1000P GND 0402 50V SENSE1.8+ 10% 2

1 PC782 + 150U 7343 6.3V 2

A

2

1 2 3 4 5 6 7 8

PC57 1 1 1 2 2

SENSE1.81 1 PR98 24.9K 0402 1% 2 1 1 PC61 180P 0402 10% 50V PR105 15K 0402 1%

1

GND

+3VS_P

PR99 19.6K 0402 1%

1

PR101 2K 0402 1% PC60 100P 0402 +/-10% 50V

12

1

PC63 180P 0402 10% 50V

PR96 13.7K 0402 PC62 1% 100P 0402 PR107 +/-10% 50V 15K 0402 PR97 1% 19.6K 0402 1% 1 1 2 2

2

PC55 1000P 0402 10% 50V JS3 1 SHORT-SMT1 2

B

2

2

2

2

B

PR93 100K 0402 1% 2 PR94 31 MCH_PG 1 0 0402 5% 2

1

2

2

GND PR103 0 0402 5% SGND2

2

1 PR102 10K 0402 1%

2

INTVCC2

VDD5 D G 1 PR95 100K 0402 1% 2 S D S PQ17 2N7002

SGND2 G

D D S S PQ16 2N7002

A

A

D 25,26,28,30,31 PWRON_SUSB# 1 R103 0402 1 0 5% 2 1 G S PR106 1M 0402 1% D S PQ18 2N7002 C142 0.1U/NA 0402 +80-20% 50V

SGND2 Title

2

2

8050 MOTHER B/D

SGND2 Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 29 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

+1.2V/1.0V_M10

DVMAIN

D

JS707 1 2 1 1 SHORT-SMT4

PL718 2 2012 120Z/100M/NA PC802 0.01U/NA 0402 10% 50V

D

2 1 1 PC806 0.01U/NA 0402 10% 50V GND 1 PR72 1M/NA 0402 5% 2 1 10/NA 0402 5% PC803 10U/NA 1210 25V 20%/X5R 2 PC804 10U/NA 1210 25V 20%/X5R 1 PJL10 PC805 10U/NA 1210 25V 20%/X5R JP_NET20 1 PC807 1000P/NA 0402 10% 50V 2 GND +5VS_P PR100 2 A GND PD725 1 PC37 0.1U/NA 0402 +80-20% 50V GND EC10QS04/NA K 1 PC64 2 PR108 4.7/NA 0603 1% 10U/NA 16V 1206 2 GND

C

2

1

2

GND 2

C

25,26,28,29,31 PWRON_SUSB#

1

PC77 0.1U/NA 0402 +80-20% 50V

PC81 0.1U/NA 0805 10% 4

5 6 7 8

1

PR125 0402 0/NA 2 5% 1

2

1

D G

PU710 SI4800DY/NA SO8 +1.2V/1.0V_M10

PU16 1 2 3 4 5 6 7 EN/PSV VIN VOUT VCCA FB PGOOD AGND SC1470/NA TSSOP14 BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 1 PR126 8.2K/NA 0402 5% 4 2

2

2

S 1 2 3

2

SGND7

PL719 1 5 6 7 8 2 2.2UH/NA IHLP5050CE-01 20% 1 PC814 + 330U/NA 7343 4V 2

1 PC811 + 330U/NA 7343 4V 1 2 1 PC815 + 330U/NA 7343 4V 2

D G

PU712 AO4410/NA SO8 288204410010

1

PC78 0.01U/NA 0402 10% 50V

PC79 0.1U/NA 0402 +80-20% 50V

K PD726 PC816 BZV55C2V4/NA 0.1U/NA 0402 +80-20% 50V A

1

2

2

1

S 1 2 3 K

PD727 EC31QS04-TE12L/NA DC2010

JS9 1 SHORT-SMT1

B

2

A

2

GND SGND7

B

1 PR127 10K/NA 0402 1% 1

2

PR128 24.9K/NA 0402 1% D 2

1 PR129 10K/NA 0402 1% 2 SGND7

7 SW_1.5V/1.25V

1 PR130 100K/NA 0402 1%

2 1

G S PC80 0.1U/NA 0402 10% 10V SGND7 2

D S

PQ19 2N7002/NA

A

A

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 30 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

+5VS_P

CPU_CORE

1 PR4 10K 0402 1% 2 1 PR5 10 0402 1% 2 MCH_PG 29

PR6 1 PC6

D

2 2.2K 0402 1% VRMPWRGD PR7 0 0402 5% 1 13

D

1

2 1U 0402 10V +80-20% 2

GND_A PR14 13,14 DPRSLPVR 2 PM_PS 1 1 0 0402 5% 2 PR32 0 0402 5% 1 1 PC15 100P 0402 +/-10% 50V PR30 100K 0402 VOS-1% 1 PR18 1 0402 1% 2 2 1 2 PC18 1000P 0402 50V 2 +80-20%

PR712 0 0402 5% +5VS_P A

1

1

DVMAIN PR710 1.96K 0402 1% +3V 1

PL5 120Z/100M 2012 1 PF2 2 1 PL4 120Z/100M 2012 PC41 1000P 0402 +/-20% 50V 2 2

DD_CPU

2 2

1 PR13 0 0402 5%

2 PD706 EC10QS04 K 1 PR8 4.7 0603 1% 2 2

2

7A/24VDC 1

1

1

1

1

1

1

1

3,11,13 STOP_CPU#

1

PC755 10U 1210 25V 20%

PC750 10U 1210 25V 20%

PC754 10U 1210 25V 20%

PC753 10U 1210 25V 20%

PC757 10U 1210 25V 20%

PC752 10U 1210 25V 20%

PC751 0.01U 0402 10% 50V

2 PJL9 JP_NET20 1 1 PC58 1000P 0402 +/-20% 50V GND 2

2

2

2

2

2

2

PC9 0.1U 0805 X7R

GND GND

5 6 7 8

5 6 7 8

DPRSLPVR

FREQSET

MCH_PG

SGND1

PSIB

VFB

PR28 576K 0402 1% PR29 1 2 13.3K 0402 1% GND_A PC21 1000P 0402 10% 50V 1

PGOOD

BOOST

SVCC

D G TG SW PVCC BG PGND VID5 VID4 VID3 24 23 S 22 1 2 3 4

PU9 D FDS6694 G SO8 4 S 1 2 3

PU8 FDS6694/NA SO8 4

5 6 7 8

1

GND_A PC11 220P 0402 10% 50V 1 VOA+ 2 3 4 5 6 7 8 VOA-

2

33

32

31

30

29

28

27

26

25

1

PU3 D G PU10 FDS6694 SO8

2

2

S 1 2 3

GND_A

C

OAOUT STP_CPUB SGND SENSE+ SENSERDPRSLP RDPSLP RUN/SS RBOOT VID0 VID1 VID2

S1+

21 20 19 1 18 17 GND 5 6 7 8 5 6 7 8 5 6 7 8 0.68UH IHLP-5050CE 15% PU11 FDS7788 SO8 PL711 2 1

1 PR37 10 0402 1%

2 1

PR740 .001 2512C 1% 2

2

+VCC_CORE

C

S1-

1 PR38 10 0402 1%

2

2

1

PR39 2.32K 0402 1% 2

S1-

1

S1+

1

D PR31 0 0402 5% G 4 S +5VS_P 1 2 3

LTC3734 HVQFN32 2

10

11

12

13

14

15

16

9

4 S 1 2 3

4 S 1 2 3 K PD718 EC31QS04-TE12L DC2010 1 A

2

1 PC784 + 220U 7243 2V PD720 BZV55C2V4/NA 2

PU12 FDS7788 SO8

D G

PU13 FDS7788 SO8

D G

PC785 + 220U 7243 2V

PC778 + 220U 7243 2V 2

1 PC773 0.1U 0402 +80-20% 50V 2

ITH

GND_A PR15 PR12 1 1 PC5 100K 1000P0402 0402 1% +80-20% 50V PR19 1 13.3K 0402 1% 2 2 1 56.2K 0402 1 1% 2 1 PR44 0 0402 5% 2 1 2

NC

1

1

2

1

GND_A

2

1

PR16 1.3M 0402 1 1% PR17 12.7K 0402 1% 1 2 PR43 499K 0402 1%

PR52 0 0402 5%

PR33 0 0402 5% 2

PC13 10U 1206 10V

PC12 0.1U 0402 +80-20% 50V

PC786 + 220U/NA 7243 2V 2 2

PC775 + 220U 7243 2V 2

PC781 + 220U 7243 2V A 2 PR104 0 0402 5% VOS-

1

1

2

2

B

RUN/SS 2

PR40 0 0402 5%

PR34 0 0402 5% VID5 VID4 VID3 VID2 +3VS VID1 VDD3

2

2

1

JS2 1 SHORT-SMT1 GND_A 2 GND

1

K

B

PR53 1K 0402 1% 1 2 PC22 100P/NA 0402 +/-10% 50V

1

1 +3V 1 PR731 2K 0402 1% 1 PR51 2K/NA 0402 1% 2 PR57 0 0402 5% 1 VDD3 D 1 1 PR56 0 0402 5% PR68 1.91K/NA 0402 1% 2 1 PR73 0/NA 0402 5%

2

VCCP_PWRGD 28

VDD3 1 PC29 1000P 0402 10% 50V 1 1 VID0

2

2

2

CORE_CLKEN# 11

PR729 249K 0402 1% 2 2

PR64 249K/NA 0402 1%

1 PR59 1M 0402 1% 2

2

B 1 E

PR60 1 2 B

D

2

G S D

A

D S

PQ5 2N7002 SOT23_FET 2

1

PR49 100K 0402 1%

RUN/SS

1

C

PQ9 MMBT3904L 288203904022

S

3

VID[0..5]

VID0 VID1 VID2 VID3 VID4 VID5

C

VID[0..5]

GND_A VDD5

G

D S

PQ8 2N7002 SOT23_FET 2

PR58 4.12K 0402 1%

2

PWROK

4,12,13,17,25

PR66 80.6K 0402 1% PR50 1M 0402 1% 2

GND_A 43.2K 0402 1% PC35 1U 0402 +80-20% 10V E

PQ10 MMBT3904L 288203904022

GND_A 2

1

GND_A

A

PR61 25,26,28,29,30 PWRON_SUSB# 1 0 0402 5% 2 1 1 G S PR62 1M 0402 1%

1 PC27 100P 0402 +/-10% 50V

D S

1

PQ7 2N7002 SOT23_FET

C26 0.1U/NA 0402 +80-20% 50V

PC28 3300P 0402 10% 50V

GND_A

2

2

2

2

GND_A 3

PD4 2 1 BAT54C

Title

8050 MOTHER B/D

Size C Date:

2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 31 of 34

1

Rev R01

Monday, December 29, 2003

5

4

3

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

VMAIN/DISCHARGE

PD702 1 3 2

D

PWR_VDDIN

PD704 2 3 1 BAV70LT1 288100070006

D

BAV70LT1 288100070006

PL1 120Z/100M 2012 2 PJ701 2DC-S107B200 1 2 1 JACK-2P 331910002006 3 4 A1 1 2

JO701 1 OPEN-SMT4 PQ701 AO4407 SO8 A4 1 3 2 1 S G PR702 470K 0402 5% 2 8 7 6 5 1 1 1 1 1 PC818 0.01U 0402 +80-20% 50V PC819 0.01U 0402 +80-20% 50V PC820 1000P 0402 +/-20% 50V PC821 1000P 0402 +/-20% 50V 2 PR704 4.7K 0805 2 ADINP 33 1 3 2 1 1 1 1 1 1 1 SBM1040 PR706 4.7K 0805 1 100K 0402 5% 4 G GND 1 PR45 33K 0402 5% D 2 2 PC82 0.01U 0402 +80-20% 50V PC83 0.01U 0402 +80-20% 50V PC84 1000P 0402 +/-20% 50V PC85 1000P 0402 +/-20% 50V PC711 1000P 0402 +/-20% 50V PC740 0.01U 0402 10% 50V 1 PC86 0.01U 0402 +80-20% 50V 2 DVMAIN PD703

PF1 1

7A/24VDC A2 2

2 PL2 120Z/100M PC2 2012 0.01U 0402 10% 50V

1

A3 K

1 PR701 .01 2512 1%

2

D

1

PC701 1U 0805 25V

1 PC702 0.01U 0402 10% 50V

PD701 RLZ24D MLL34B A

4

2

2

2

2

2

2

2

2

2

2

2

PR720 2 PQ704 AO4407 SO8

1

2

2

1

SPARKGAP_6

SPARKGAP_6

GND 2

D

2

1

1

22 LEARNING

C

LEARNING 1

G S PR705 1M 0402 5% 2

D S

PQ702 2N7002

2

PJO701 OPEN-SMT4 ADEN# 22,25

GND PU1 4 5 6 1 RS+ RSOUT VCC GND1 GND0 3 2 1

5 6 7 8

G S

1

D PQ6 S 2N7002 SOT23_FET

1

PR1 10 0402 5% 2

MAX4173FEUT-T SOT26

PC1 0.01U 0402 10% 50V

2

GND 1 PC733 0.01U 0402 +80-20% 50V 1 GND 3 PC732 1000P 0402 +/-20% 50V

GND I_LIMIT 1 PC3 1U 0805 10V 2 GND PF702 1 7A/24VDC 2 1 B2 2 PL704 120Z/100M 2012 22 PL705 120Z/100M 2012 2

PQ24 DTC144WK 288202237002

2

GND

2

1 1 B3 1 PR716 499K 0402 1% 1 2 PC722 0.01U 0402 10% 50V BAT_V 1 PR714 100K 0402 1% 2 1 PC723 0.1U 0402 +80-20% 50V 22 3 2 VDD5 8 BATT 33 GND

VDD3S

PC720 0.01U 0402 10% 50V

J703

B

1

GND PR20 4.99K 0402 1% 2

7 6 5 4 3 2 1

R/A-7P-2.5MM SUYIN 250233-MR007G123ZU

PR21 20K 0402 1% 2

1

7 6 5 4 3 2 1

2

+ -

1

1 PU5A LMV393M SSOP8

2

GNDB 2 B1 1

PC16 0.1U 0402 +80-20% 50V

GND

2

GND

GND 1

PR23 2 0 0402 5% PR24 1 2 0 0402 5% PD2 2 3 1 PD3 3 1 BAV99 2 288100099012 VDD3 BAT_C 22

BAT_D

22

VDD3

2

2

BAV99 288100099012 JP1 SPARKGAP_6 GND GND

A

JO11 SPARKGAP_6 1 1

4

BAT_T

22

2

GND

GND

5

4

3

2

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

D

S

JO1

JO2

PR703 100K 0402 5%

PR71 226K 0402 1%

1 2 3

GND

2

C

BATT

33

B

A

Title

8050 MOTHER B/D

Size C Date: Document Number PCB 316680900001/ASSY 411680900011 Sheet 32 of 34

1

Rev R01

Monday, December 29, 2003

5

4

3

2

1

CHARGING

PQ707 AO4407 SO8

D

PF703 32 ADINP 1 2 TR/3216FF-3A 1

L2

C

PC747 0.01U 0402 10% 50V

PC748 0.01U 0402 10% 50V

PC745 10U 1210 25V 2

PR87 4.7K 0603 2

PR88 4.7K 0603

PC756 10U 1210 25V

B GND PD5 1 PR86 0 1206 5% PQ13 DTA144WK SOT23AN_1 3 1 2 K BAS32L MLL34B A E

PQ15 MMBT2222A 288202222019

PR89 100K 0402 5% A 2

PD714 EC31QS04 DC2010 GND GND

3.0UH PC758 SPC-06703 0.01U 30% 0402 10% 50V

K

PL708 1 2 BEAD_120Z/100M 0805D 1 1

L3

3 2 1 S G

8 7 6 5

D

PL710 L4 1 33UH CDRH124 2 L5 1

PL709 2 A

PD713 K

12.65V BATT K 32

D

1

EC31QS04 DC2010 PD709 1 BZV55C15V PC39 PR75 20K 1000P 0402 0402 0.1% 50V 10% 2IN+ 2 1 1

1

1

1

4

1

PC741 10U 1210 25V

PD711 RLZ20C/NA MLL34B A GND

2

2

2

K

1

2

2

A

2

1

2

PR74 13.7K 0402 0.1% 2

PR76 249K 0402 1% 2 2 PJ1 OPEN-SMT4

2

22 CHARGING

C

S

1

PU7 PC48 0.01U 0402 10% 50V 9 10 11 12 13 14 15 16 E1 C1 E2 GND C2 RT VCC CT OUTPUTCTRL DTC REF FEEDBACK 2IN1IN2IN+ 1IN+ TL594C SO16 1 8 7 6 5 4 3 2 1 1 PC43 1 2 PR85 0 0402 5% 2 22 CHARGING G

D

G

PQ14 D 2N7002 S SOT23_FET

PC49 0.01U/NA 0402 50V +80-20% 1 2

D

PQ12 D 2N7002 S SOT23_FET 1

C

2IN+ GND

PC42 2 1 1 2 0.01U 0402 50V +80-20% PC45 REF 1 2 0.1U 0402 50V +80-20%

0.01U 0402 50V +80-20% PC46 1U 0805 10V

1

PR83 100K 0402 5%

1

1

PC47 1000P 0402 10% 50V

PR84 7.5K 0402 5% 2

1

PR79 124K 0402 1% 2 PR22 1 2 .02 2512 1% PR77 2.49K 0402 1% 2 2 GND GNDB

PR82 10K 0402 1% 2

2

PC44 1 2 0.1U 0402 16V 10% 1

2

PR81 2 6.19K 0402 1% PR80 1 1

63.4K/NA 0402 5%

B

PJS1 PR78 2 SHORT-SMT3 0 0402 5% 2 1

B

22 I_CTRL

1

VDD5

DVMAIN

1

PR70 3.3K 0402 5% 2

1

PC34 0.01U 0402 10% 50V 2

1

PR65 590K 0402 1% 8

1

GND 1.25V 2 PQ11 SCK431LCSK-.5 SOT23N 3 2

PR69 100K 0402 5% 2

2

5 6 1

+ 4

7 PU5B LMV393M SSOP8

BATT_DEAD =8.56V 1 PC36 0.01U 0402 10% 50V

22

1

1

PC33 0.1U 0402 +80-20% 50V

PR63 80.6K 0402 5%

A

2

2

S

2

A

GND

GND

Title

8050 MOTHER B/D

Size C Date:

5 4 3 2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 33 of 34

1

Rev R01

Monday, December 29, 2003

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

5

4

3

2

1

VGA_THRMDA/VGA_THRMDC CPU_THRMDA/CPU_THRMDC SIO_48M

(DEBUG CARD ONLY) 14.318MHZ

D

8050 BLOCK DIAGRAM

CLK_ITP_CPU+/- 100MHZ HCLK_CPU+/- 100MHZ

LCD PANEL (XGA) CPU INTEL BANIAS/DOTHAN LVDS

D

CLOCK GENERATOR ICS950810

14M_CODEC HOST 400MHZ

BATT-Adapter

RGB

LVDS/NA RGB/NA

CRT

D/D Power LTC3728L +2.5V/+1.25V

HCLK_NB+/- 100MHZ

D/D Charger TL-594C D/D CPU Core LTC3734

North Bridge

66M_MCH

DREFCLK_48MHZ

I-LIMIT OP MAX4173F

DIMM1

DIMM0 CLK_DDR2+/CLK_DDR1+/CLK_DDR0+/CLK_DDR3+/CLK_DDR4+/CLK_DDR5+/-

855GME

AGP VGA_M10

27MHZ

CH7011

D/D Power LTC3728L

TV

I -LIMIT

+3V/+5V D/D Power LTC3728L +1.5V/+1.05V

C

DDR 266

C

PCICLK_FWH

66M_AGP 66M_ICH 66MHZ 66MHZ

32.768KHZ

D/D Power SC1470

D/D Power LTC3728L +1.8V /+1.35V AC-Adapter

USBCLK_ICH 48MHZ PCICLK_ICH 33MHZ

CDROM

+1.2V/1.0V

USB 0~2

33MHZ

14M_ICH

Sourth Bridge ICH4-M

SECONDARY IDE HDD PRIMARY IDE

x3

33MHZ 33MHZ

VRAM 16MBx4

D/D

PCICLK_MINIPCI

PCI_1394_CLK PCI_CRAD_CLK

14M_CODEC (CLK GEN)

AC97 PCI

B

B

ADT7460

LPC BUS

24.576MHZ / NA

PCICLK_LAN Fan

25MHZ

RTL8100CL

SMBUS

MDC MODULE

AUDIO CODEC ALC655

PH163112

Keyboard BIOS WINBOND W83L950D

8MHZ

SYSTEM BIOS 512K

IEEE1394 VIA VT6307L

PCMCIA CARD READER CB710

MINIPCI CP2211

AMPLIFIER TPA0212

EXT MIC. INT MIC LINE IN

LM4871

KEY MATRIX

PS/2

A

NA I -LIMIT

Internal Keyboard

24.576MHZ

CABLE CARD REARDER SOCKET

HP JACK

SPEAKER SUB WOOFER

SPEAKER

A

RJ45/ RJ11

TOUCH PAD

PCMCIA/ CARDBUS SLOT

4 3

CardReader Transition Board

Title

8050 MOTHER B/D

Size C Date:

2

Document Number

PCB 316680900001/ASSY 411680900011 Sheet 34 of 34

1

Rev R01

Monday, December 29, 2003

5

PDF created with FinePrint pdfFactory trial version http://www.fineprint.com

REFERENCE MATERIAL

Intel Mobile Pentium-M Processor/BANIAS Processor ... Intel 855GME North Bridge' ... Intel ICH-4 South Bridge' WINBOND KBC Clock Syntherizer VT6307L IEEE1394 Host Controller System Explode View 8050 Hardware Specification Intel, INC. Intel, INC. Intel, INC. WINBOND, LTD. ICS,INC AMPRO Computers, INC Technology Corp / MiTAC Technology Corp / MiTAC

SERVICE MANUAL FOR 8050

Sponsoring Editor : Jesse Jan Author : Grass Ren Assistant Editor : Ping.Xie Publisher : MiTAC International Corp. Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C. Tel : 886-3-5779250 First Edition : Feb.2004 E-mail : Willy .Chen @ mic.com.tw Web : http: //www.mitac.com http: //www.mitacservice.com Fax : 886-3-5781245

Information

178 pages

Report File (DMCA)

Our content is added by our users. We aim to remove reported files within 1 working day. Please use this link to notify us:

Report this file as copyright or inappropriate

791424


You might also be interested in

BETA
Servers: Database consolidation on Dell PowerEdge R910 servers
Microsoft Word - x3850-x3950 X5 Product Guide 03-10.doc
Microsoft Word - BC-HS22 Product Guide 083109.doc