Read XB06 Datasheet text version

1.0 µm BCD Process


Modular 1.0µm 350V Trench Insulated BCD Process


XDM10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 110V net supply. The typical breakdown voltage of the HV-DMOS devices is >350 V or >275V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die. Trench (dielectric) insulated thick 6 inch SOI wafers are the base for the XD10 process. With the dielectric insulation the necessary area needed for 350V insulation is significantly smaller then with junction insulation (especially for high voltage applications) leading to smaller chip sizes. Use of dielectric insulation insures a bi-directional insulation between adjacent components. The quasi vertical DMOS transistor is the basic HV component of the XD10 technology. The device structure and process parameters are optimised The 14 layers core process module is available for 350V breakdown voltage of the HV DMOS. This process module provides trench insulation, single level poly with thick gate oxide, a third level metal with power metal. With this core module an optimised self-aligned poly-gate n-channel quasi-vertical DMOS transistor and some bipolar transistors can be made, other process modules can be added to integrate CMOS transistors, high voltage PMOS transistors, further bipolar elements and a third poly for poly-poly capacitors and high value resistors. to obtain a drain breakdown voltage of >350V and >275V respectively and maximum drain saturation current with a low on-resistance. The electrical characteristics depend on channel width and length, drift-layer length, drift-layer doping and extendedsource field-plate effect. The DMOS device is fabricated with a double-diffused process with a deep p-tub to prevent secondary breakdown. A wide variety of different voltage levels is possible on the same die.


Key Features

A high number of different devices are available: High and medium voltage n-channel DMOS Medium voltage PMOS CMOS transistors with different voltage levels NPN and PNP transistors with different voltages NEW: DEPLTRA module (N channel CMOS depletion transistors) , PODCAP module (Poly on diffusion resistor) NEW: Scaleable DMOS & PMOS transistors with different numbers of centrepiece NEW: OTP option: Zener Zap High voltage and zener diodes Gate oxide and high voltage capacitors Poly resistors with different sheet resistivities Triple level metal, third metal 2.3µm Optional third poly for high value resistor or poly-poly capacitor Doped oxide / polyimide passivation 1µm design rules enable the integration of complex CMOS logic


The DIMOS technology is suitable for high voltage ICs where breakdown voltages up to 350V and medium currents are necessary. Despite of the expensive SOI wafer material this technology is competitive especially when more then one insulated switch has to be integrated due to the reduction of assembly costs. X-FAB spends a lot of effort to improve the product quality and reliability and to provide competent support to the customers. This is maintained by the direct and flexible customer interface, the reliable manufacturing process and complex test and evaluation conceptions, all of them guided

Possible applications are driver ICs for capacitive, inductive and resistive loads; analog switch ICs; driver ICs for EL and piezo elements; high voltage DMOS arrays; half and full bridges with driver and logic as well as high input voltage linear regulators.

Quality Assurance

by strict quality improvement procedures developed by X-FAB. This comprehensive, proprietary quality improvement system has been certified to fulfill the requirements of the ISO 9001, QS 9000, VDA 6, ISO TS 16949 and other standards.


- PCM tested wafers - Optional production services: wafer sort - Optional Engineering services: Multi Project Wafer (MPW) and Multi Layer Service (MLM)

Data Sheet XDM10 · Rev. 2.0 ·Mar 2009

... because the world is analog.


Process Modules

Module Name CORE No. of Masks 14 Remarks trench insulation, DMOS, 1P, metal 1, metal 2, power metal 3 Remarks CMOS module, n-well, p-well, 1Poly Capacitor/ resistor module, additional Poly2 Depletion transistor module, additional implant Polysilicon on diffusion capacitor module additional implant Typical Primitive Devices Applications 275V, 350V DMOS bipolars, diodes and resistors for power applications Typical Primitive Devices Applications 5V, 7V and 20V NMOS and PMOS, 300V PMOS for analog applications double poly capacitor, Poly2 resistors (high resistive/ low TC) for analog applications 7V Depletion transistor for analog applications polysilicon on diffusion capacitor for analog applications

This main module can be combined with one or more of the following additonal modules.

Module Name CMOS CAPRES a) DEPLTRA a) PODCAP a) No. of Masks 5 1 1 1

Notes: a) For this module, refer to "Restrictions for Module Combinations" as listed in the following table. Based on combination of these modules, the XDM10 process family offers a wide variety of proven processes.

Process Options

- The CORE module can be combined with the CMOS module. - CORE and CMOS can be combined with CAPRES, DEPLTRA and/or PODCAP modules. - Backside grinding.

Restrictions for Module Combinations

Module Name CAPRES DEPLTRA PODCAP Use of the module also requires use of following modules CMOS CMOS CMOS Use of the module is not available in combination with the following modules

Primitives Devices

- Pre-defined 350V and 275V n-channel DMOS transistors with different on-resistances - Scaleable 5V, 7V and 20V CMOS transistors - Pre-defined medium voltage PMOS for different voltages - Pre-defined bipolar transistors for different voltages up to 80V

- Poly silicon resistors (low TC and high value resistor) - Implanted resistors - Poly-Poly and gate oxide capacitor - 350V sandwich capacitor - Zener diode and protection diodes for different voltages

Basic Design Rules

Mask TRENCH DIFFD POLYD DIFF POLY1 CAPRES CONT MET1 VIA MET2 VIA2 MET3 Min. width [µm] = 4.0 4.0 1.0 0.8 1.0 2.0 1.2 1.1 1.7 1.4 4.0 3.0 Min. spacing [µm] 10.0 3.0 1.2 2.0 1.2 2.4 1.0 1.5 1.6 1.7 4.0 3.0

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Process Flow

Thick SOI wafer

Core Module

Trench Trench cover DMOS active area DMOS polysilicon DMOS p-well n-well p-well CMOS active area Chstop ND implant P implant CMOS polysilicon 1 CMOS polysilicon 2 N+ implantation P+ implantation Contact Metal 1 Via Metal 2 Via 2 Metal 3 Pads PCM test Back side grinding (on customer request) Final control

mask steps



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Additional Modules


Schematic Cross Sections

Figure 1:


Figure 2:


Figure 3:

SEM cross-section of upper trench area

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Device Parameters

The following devices can be used for circuit designs. They are well characterized and part of a primitive device library. The device names correspond with the SPICE model names. Different reliability tests gave the maximum allowed operating conditions; Values in brackets denote absolute maximum ratings. See also the availability with different options.

Active Devices (typical data)

DMOS devices Device 350V DMOS, 360 350V DMOS, 36 350V DMOS, scaleable 275V DMOS, 2k 275V DMOS, 600 275V DMOS, 140 275V DMOS, scaleable


Device Name nd32a nd32b nd32cs 1) nd25a nd25b nd25c nd25ds 2)


|VTsat| [V] 1.65 1.05 1.7 1.65 1.55 -

|BVDS| [V] > 350 > 350 > 275 > 275 > 275 -

RDSON [] 360 36 2200 600 140 -

max. ID [mA] 20 120 2.8 8 70 -

max. ID*VDS [mW] 1800 4000 240 600 2250 -

Maximum VGS for all DMOS devicess: 20V The nd32cs is a scaleable device, where the number of centrepieces can be varied. An nd32cs device with twelve centrepieces is identical to the nd32b device. The nd25ds is a scaleable device, where the number of centrepieces can be varied. An nd25ds device with zero centrepieces is identical to the nd25b device. An nd25ds device with five centrepieces is similar to the nd25c device. CMOS Devices Device 5V NMOS 7V NMOS 20V NMOS 15V NMOS 5V PMOS 7V PMOS 20V PMOS 20V PMOS HV MOS Devices Device 275V PMOS 320V PMOS 320V PMOS



Device Name ne nea nme nmea pe pea pme pmea


|VT| [V] 0.8 0.9 0.8 0.78 0.95 0.90 0.75 0.62

min. gate length [µm] 1.2 5.0 = 3.5 = 3.0 1.3 1.7 = 5.5 = 4.5

|BVDS| [V] 16 16 40 28 16 16 45 50

IDSAT [µA/µm] 150 150 90 100 65 65 32 43

max. VDS [V] 5.5 7.0 20 15 5.5 7.0 20 20

max. VGS [V] 5.5 5.5 15 15 5.5 5.5 15 15

Device Name pha phc phes 3)

Available with module CMOS CMOS CMOS

|VT| [V] 0.85 0.85 -

|BVDS| [V] 290 375 -

IDS leakage [nA] <0.2 <0.2 -

RDSON [k] 5.8 6.5 -

max. VDS [V] 240 300 300

max. VGS [V] 15 15 15

The phes is a scaleable device, where the number of centrepieces can be varied. A phes device with zero centrepieces is similar to the phc device.

Special MOS Devices Device Depletion NMOS Bipolar Transistor Device 80V vertical NPN 20V lateral PNP 40V high gain vertical NPN 80V lateral PNP 5.5V vertical NPN Device Name qna qpa qnb qpb qnvc Available with module CORE CORE CMOS CMOS CMOS BETA 80 100 1100 16 800 VA [V] 1100 6 67 60 60 Page 5 VBE [mV] 690 590 630 540 590 BVCEO [V] >100 > 26 120 > 100 > 20 max. VCE [V] 80 20 40 80 5.5 Device Name ndep Available with module DEPLTRA |VT| [V] 1.1 |BVDS| [V] 16 IDSAT [µA/µm] 100 Body effect [V1/2] 1.23 max. VDS [V] 7.0 max. VGS [V] 5.5


Device Parameter (continued) Passive Devices (typical data)

Capacitors 4) Device Device Name csandwt cpp cpod Available with module CORE CAPRES PODCAP Area Cap. [fF/µm2] 0.037 0.39 0.69 Perimeter cap. [fF/µm] 0.045 0.095 0.076 Linearity [ppm/V] 250 BV [V] > 22 max. Vterm1term2 [V] 350 15 20

POLYD-MET2-MET3 sandwich POLY1-POLY2 POLY1-Gate Oxide-N+


devices variants with underlying NWELL with identical parameters but realized an improved description of parasitics.

Resistors and Conductors Device PWELLD PWELL POLYD POLY1 NDIFF PDIFF high resistive POLY2 high resistive POLY2 HV low TC POLY2 MET1 MET2 MET3


Device Name rpwd rpw rpd rpd_3 5) rp1 rp1_3 5) rdiffn rdiffp rp2hr rp2hr_3 5) rp2hrhv rp2hrhv_3 5) rp2ltc rp2ltc_3 5) rm1 rm2 rm3


RS [/] 1530 3300 190 22.5 26 120 10000 10000 335 0.047 0.045 0.0135

Thickness/Junction depth [µm] 5 0.43 0.7 0.7 2.3

max. I/width [mA/µm] 0.4 1.5 0.08 0.08 0.4 0.8 0.8 7.0

max. VTB [V] 50 25 350 50 8 13 50 320 50 100/350 6) 100/350 6) 100/350 6)


These devices are variants of the corresponding basic device with an underlying well, but not crossing a well boundary. The models realise an improved description of bulk voltage dependency. MET / MET_MV values.

Diodes Device N+ diffusion / P-well P+ diffusion / N-well PDIFFD / NSUB PWELLD / NSUB PWELL / NSUB/NWELL Device Name dn dp dpd dpwd dpw Available with module CMOS CMOS CORE CORE CMOS BV [V] 18 21 40 140 45 Area Capacitance [fF/µm2] 0.260 0.320 0.065 0.050 0.050 Junction Potential [V] 0.87 0.83 0.55 0.55 0.50

Special Diodes Device 15V diode 45V diode 200V diode Device 4.8V Zener diode Device Name dnda dpda dpwda Device Name dzeb Available with module CORE CORE CORE Available with module CORE BV [V] 20 85 < 360 Zener voltage [V] 4.95 Page 6 Forward voltage [V] 0.93 0.77 0.76 Forward voltage [V] 0.85 Leakage current [pA] < 10 @ Vref=12V < 10 @ Vref=40V < 30 @ Vref=200V Leakage current [µA] 0.1 @ Vref = 2V Zener Impedance @ Iref = 100µA [V/A] 1000


Device Parameter (continued) Misc. Devices (typical data) (continued)

Programmable Device Device Zener Zap Device Name dzap Available with module CMOS Zener breakdown voltage [V] 4.8 Leakage current [nA] 50 Zapped zener resistance [] 50

Digital Core Library Cells



X-FAB provides a standard cell library optimized for most typical applications in mixed signal ASIC. The XDM10 standard cells can be used double-metal routing. The following Digital Standard Cell Core Library is available in X-FAB XDM10 technology

Voltage Range 5.0V


Category standard

Density 7) ML2: 0.5

r_factor 8) ML2: 2.86

Main feature standard digital applications

library density: kGE/mm at given routing factor (GE = NAND2 Gate Equivalent) ML2: 2 metal layer routing 8) r_factor = Routing_factor Place&Route_area = Cell_area * Routing_factor (averaged value: because routing factor, means wiring overhead, is netlist dependent) Utilization [%] = 1/routing_factor * 100, e.g. r_factor = 2.68; utilization = 1/2.86 * 100 = 35%

Digital I/O Cells

The digital I/O library contains I/O cells divided into distinct inputs, outputs and bidirectionals cells as Digital well as some special analog I/O cells. The digital I/O library has the following features: - I/O library cells are available for core-limited designs. - The I/O cell library requires the CMOS module. - I/O cells are optimized for 5.0V +/-10% operating voltage and are fully functional down to 3.3V +/-10% with derated current and speed. - The TTL and CMOS level detection circuits use low noise power rails. - CMOS Schmitt Trigger cells optimized for the 5V and 3.3V operating voltages are available. - Inputs and bi-directional cells are available with gated pull-up and pull-down options. - Outputs are available with selectable speeds to maintain low noise independent from DC outputdrive and can be configured as tri-state, bi-state, open drain or open source. - Special bi-state, open drain or open source output buffer cells are available. - All input and output cells are non-inverting.

Core Limited I/O Cells

Input Schmitt Trigger Cells CMOS/TTL Input Option Gated Pull-up Gated Pull-down Input Hold Gated CMOS Input NAND Tree

CMOS or TTL Level /

Tri-state Output 1, 4mA

Output Output Drive Slew Rate Control

Configurations Cell Height Cell Width / Pad Pitch

Bi-state Output Tri-state Output Open Drain Output Open Source Output 286.3µm variable, depending on I/O cell 2kV (HBM) Page 7

Cell Size

ESD Robustness


Examples for measured and modeled parameter characteristics

Figure 4: device ne: drain current matching vs. Vgs (typical value) legends show the drawn transistor lengths and widths

Figure 5: device pe: drain current matching vs. Vgs (typical value) legends show the drawn transistor lengths and widths

Figure 6: Output characteristic of a typical wafer (nd32a) VGS = 2.5, 3.0, 3.5, 4.0, 4.5, 5.0V + = measured, solid line = SPICE model

Figure 7: On resistance Vs. Number of centrepieces of a typical wafer for device nd32cs

Figure 8: Output characteristic of a typical wafer (phc) -VGS = 1.0, 2.0, 3.0, 4.0, 5.0V, VSB = 0V + = measured, solid line = SPICE model

Figure 9: On resistance Vs. Number of centrepieces of a typical wafer for device phes

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Supported EDA Tools


Frontend Design Environment

Digital Simulation

Timing, Power, Signal-Integrity Analysis

MixedSignal Simulators

Analog Simulators

Mixed Signal Environment

Floorplanning, Place & Route

Layout / Chip assembly drawing

Verification & SignOff

Tape Out / GDSII

Note: Diagram shows overview of reference flow at X-FAB. Detailed information of supported EDA tools for major vendors like Cadence, Mentor and Synopsys can be found on X-FAB's online technical information center, X-TIC.

X-FAB's IC Development Kit "TheKit"

The X-FAB IC Development Kit is a complete solution for easy access to X-FAB technologies. TheKit is the best interface between standard CAE tools and X-FAB's processes and libraries. TheKit is available in two versions, the Master Kit and the Master Kit Plus. Both versions contain documentation, a set of software programs and utilities, digital and I/O libraries which contain full front-end and back-end Marketing & Sales Headquarters X-FAB Semiconductor Foundries AG Haarbergstr. 67, 99097 Erfurt, Germany Tel.: +49-361-427 6160 Fax: +49-361-427 6161 Email: [email protected] Web: Quality Data are available on request. Contact:

information for the development of digital, analog and mixed signal circuits. Tutorials and application notes are included as well. The Master Kit Plus additionally provides a set of general purpose analog functions mentioned in section "Analog Library Cells" and is subject to a particular license. Information [email protected] Technology & Design Support [email protected] Silicon Foundry Services [email protected] X-FAB Semiconductor Foundries AG Quality Assurance Haarbergstr. 67 99097 Erfurt, Germany


Quality Data

Important Notice

Products sold by X-FAB are covered by the warranty provisions appearing in its Term of Sale. X-FAB makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. X-FAB reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with X-FAB for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as medical life-support or life-sustaining equipment are specifically not recommended without additional processing by X-FAB for each application. The information furnished by X-FAB is believed to be correct and accurate. However, X-FAB shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of X-FAB's rendering of technical or other services. © 1999-2009 by X-FAB Semiconductor Foundries AG. All rights reserved.

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XB06 Datasheet

9 pages

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