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Objectives

EDK 9.1 PowerPC Tutorial in Virtex-4

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System Requirements

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PowerPC Tutorial WT001 (v4.0) March, 2007

Note: This tutorial can be completed on Linux or Solaris, but the screenshots and directories illustrated in this tutorial are based on the Windows Platform.

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Note: It should be noted that other hardware could be used with this tutorial. However, the completed design has only been verified on the board specified above. The following design changes are required:

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EDK 9.1 PowerPC Tutorial in Virtex-4 WT001 (v4.0) March, 2007

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EDK 9.1 PowerPC Tutorial in Virtex 4

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PowerPC Tutorial WT001 (v4.0) March, 2007

: Tutorial Design Memory Map

Note: For more information on the MSS file, refer to the "Microprocessor Software Specification (MSS)" chapter in the Platform Specification Format Reference Manual.

Note: For more information on the MHS file, refer to the "Microprocessor Hardware Specification (MHS)" chapter in the Platform Specification Format Reference Manual.

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EDK 9.1 PowerPC Tutorial in Virtex-4 WT001 (v4.0) March, 2007

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EDK 9.1 PowerPC Tutorial in Virtex 4

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PowerPC Tutorial WT001 (v4.0) March, 2007

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PowerPC Tutorial WT001 (v4.0) March, 2007

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EDK 9.1 PowerPC Tutorial in Virtex-4 WT001 (v4.0) March, 2007

EDK 9.1 PowerPC Tutorial in Virtex 4

PowerPC Tutorial WT001 (v4.0) March, 2007

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EDK 9.1 PowerPC Tutorial in Virtex-4 WT001 (v4.0) March, 2007

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EDK 9.1 PowerPC Tutorial in Virtex 4

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PowerPC Tutorial WT001 (v4.0) March, 2007

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EDK 9.1 PowerPC Tutorial in Virtex-4 WT001 (v4.0) March, 2007

EDK 9.1 PowerPC Tutorial in Virtex 4

PowerPC Tutorial WT001 (v4.0) March, 2007

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EDK 9.1 PowerPC Tutorial in Virtex-4 WT001 (v4.0) March, 2007

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EDK 9.1 PowerPC Tutorial in Virtex-4 WT001 (v4.0) March, 2007

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EDK 9.1 PowerPC Tutorial in Virtex-4 WT001 (v4.0) March, 2007

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-------------------------------------------------------------------------------- system_stub.vhd ------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_stub is port ( fpga_0_RS232_Uart_RX_pin : in std_logic; fpga_0_RS232_Uart_TX_pin : out std_logic; fpga_0_LEDs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3); fpga_0_Push_Buttons_Position_GPIO_IO_pin : inout std_logic_vector(0 to 4); fpga_0_SRAM_256Kx32_Mem_A_pin : out std_logic_vector(9 to 29); fpga_0_SRAM_256Kx32_Mem_BEN_pin : out std_logic_vector(0 to 3); fpga_0_SRAM_256Kx32_Mem_WEN_pin : out std_logic; fpga_0_SRAM_256Kx32_Mem_DQ_pin : inout std_logic_vector(0 to 31); fpga_0_SRAM_256Kx32_Mem_OEN_pin : out std_logic_vector(0 to 0); fpga_0_SRAM_256Kx32_Mem_CEN_pin : out std_logic_vector(0 to 0); fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin : out std_logic; fpga_0_SRAM_CLOCK : out std_logic; sys_clk_pin : in std_logic; sys_rst_pin : in std_logic ); end system_stub; architecture STRUCTURE of system_stub is component system is port (

26

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EDK 9.1 PowerPC Tutorial in Virtex-4 WT001 (v4.0) March, 2007

EDK 9.1 PowerPC Tutorial in Virtex 4 fpga_0_RS232_Uart_RX_pin : in std_logic; fpga_0_RS232_Uart_TX_pin : out std_logic; fpga_0_LEDs_4Bit_GPIO_IO_pin : inout std_logic_vector(0 to 3); fpga_0_Push_Buttons_Position_GPIO_IO_pin : inout std_logic_vector(0 to 4); fpga_0_SRAM_256Kx32_Mem_A_pin : out std_logic_vector(9 to 29); fpga_0_SRAM_256Kx32_Mem_BEN_pin : out std_logic_vector(0 to 3); fpga_0_SRAM_256Kx32_Mem_WEN_pin : out std_logic; fpga_0_SRAM_256Kx32_Mem_DQ_pin : inout std_logic_vector(0 to 31); fpga_0_SRAM_256Kx32_Mem_OEN_pin : out std_logic_vector(0 to 0); fpga_0_SRAM_256Kx32_Mem_CEN_pin : out std_logic_vector(0 to 0); fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin : out std_logic; fpga_0_SRAM_CLOCK : out std_logic; sys_clk_pin : in std_logic; sys_rst_pin : in std_logic ); end component; begin system_i : system port map ( fpga_0_RS232_Uart_RX_pin => fpga_0_RS232_Uart_RX_pin, fpga_0_RS232_Uart_TX_pin => fpga_0_RS232_Uart_TX_pin, fpga_0_LEDs_4Bit_GPIO_IO_pin => fpga_0_LEDs_4Bit_GPIO_IO_pin, fpga_0_Push_Buttons_Position_GPIO_IO_pin => fpga_0_Push_Buttons_Position_GPIO_IO_pin, fpga_0_SRAM_256Kx32_Mem_A_pin => fpga_0_SRAM_256Kx32_Mem_A_pin, fpga_0_SRAM_256Kx32_Mem_BEN_pin => fpga_0_SRAM_256Kx32_Mem_BEN_pin, fpga_0_SRAM_256Kx32_Mem_WEN_pin => fpga_0_SRAM_256Kx32_Mem_WEN_pin, fpga_0_SRAM_256Kx32_Mem_DQ_pin => fpga_0_SRAM_256Kx32_Mem_DQ_pin, fpga_0_SRAM_256Kx32_Mem_OEN_pin => fpga_0_SRAM_256Kx32_Mem_OEN_pin(0 to 0), fpga_0_SRAM_256Kx32_Mem_CEN_pin => fpga_0_SRAM_256Kx32_Mem_CEN_pin(0 to 0), fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin => fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin, fpga_0_SRAM_CLOCK => fpga_0_SRAM_CLOCK, sys_clk_pin => sys_clk_pin, sys_rst_pin => sys_rst_pin ); end architecture STRUCTURE;

PowerPC Tutorial WT001 (v4.0) March, 2007

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.8 erug iF n i nwohs s a dl ei f em aN n oi tarugi fnoC e h t n i f n o c _ d h v _ h c n e b t s e t t r e s ni d n a e m a N n o i t a r u gi f n o C e s U t c e l e s , s n 0 ot e mi t n u r n o i t a l u m i s e h t e g n a h C ... s e i t r e p o r P t c e l e s d n a l e d o M l a r o i v a h e B e t a l u mi S n o k ci l c - t h g i r n e h t w o d n i w s s e c o r p e h t n i r o t al u m i S m i S l e d o M e h t d n a p x E . w o d n i W e c r u o S E S I e h t n i d h v . h c n e b t s e t t c e l e S .el if dhv.hc neb tset e ht eso lc dn a evaS

configuration testbench_vhd_conf of testbench_vhd is for behavior for uut: system_stub for STRUCTURE for system_i: system use configuration work.system_conf; end for; end for; end for; end for; end testbench_vhd_conf;

: e l i f d h v . h c n e b t s e T e h t n i t n e m e t a t s " ; D N E " l a ni f e h t r e t f a g n i w ol l o f e h t d d A . d e zi li t u e b t s u m t n e m e t a t s n o i t a r u g i f n o c a , n o i t a c i l p p A y r o m e M _ p p A t s e T e h t h ti w s M A R B e h t e t a l u p o p ot r e d r o n I

fpga_0_RS232_Uart_RX_pin <= fpga_0_RS232_Uart_TX_pin;

PowerPC Tutorial WT001 (v4.0) March, 2007

add wave -radix ascii /testbench_vhd/uut/inst_system /rs232_uart/rs232_uart/opb_uartlite_core_i/opb_uartlite_tx_i/fifo_dout

EDK 9.1 PowerPC Tutorial in Virtex 4

sys_rst_pin <= '0'; wait for 5 us; sys_rst_pin <= '1'; wait; END PROCESS;

www.xilinx.com 1-800-255-7778

39

eht no kcilC

stluser noitalumiS :93 erugiF

. 9 3 e r u g i F n i n w o h s e n o e h t o t r al i m i s m r o f e v a w m i s l e d o M a ees dl uo hs uoY .sen i tuor f tnirp eht fo esu aceb n gi sed e ht f o ytil a n oitcn uf eh t eta lu m is o t ng ised eht nur o t S u d n a s u o h t l a r e v e s e k a t l l i w t I . n oi t a l u m i s e h t g n i n n u r n i g e b o t " s u 0 0 3 n u r " e p yt t p m o r p d n a m m o c e h t t A 4 - x e t r i V ni l ai r o t u T C P r e w o P 1 . 9 K D E

40

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EDK 9.1 PowerPC Tutorial in Virtex-4 WT001 (v4.0) March, 2007

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Microsoft Word - EDK9.1_ppc_se.doc

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